1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
13 #include <linux/genalloc.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/altera-sysmgr.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/notifier.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/panic_notifier.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/types.h>
27 #include <linux/uaccess.h>
29 #include "altera_edac.h"
30 #include "edac_module.h"
32 #define EDAC_MOD_STR "altera_edac"
33 #define EDAC_DEVICE "Altera"
35 #ifdef CONFIG_EDAC_ALTERA_SDRAM
36 static const struct altr_sdram_prv_data c5_data
= {
37 .ecc_ctrl_offset
= CV_CTLCFG_OFST
,
38 .ecc_ctl_en_mask
= CV_CTLCFG_ECC_AUTO_EN
,
39 .ecc_stat_offset
= CV_DRAMSTS_OFST
,
40 .ecc_stat_ce_mask
= CV_DRAMSTS_SBEERR
,
41 .ecc_stat_ue_mask
= CV_DRAMSTS_DBEERR
,
42 .ecc_saddr_offset
= CV_ERRADDR_OFST
,
43 .ecc_daddr_offset
= CV_ERRADDR_OFST
,
44 .ecc_cecnt_offset
= CV_SBECOUNT_OFST
,
45 .ecc_uecnt_offset
= CV_DBECOUNT_OFST
,
46 .ecc_irq_en_offset
= CV_DRAMINTR_OFST
,
47 .ecc_irq_en_mask
= CV_DRAMINTR_INTREN
,
48 .ecc_irq_clr_offset
= CV_DRAMINTR_OFST
,
49 .ecc_irq_clr_mask
= (CV_DRAMINTR_INTRCLR
| CV_DRAMINTR_INTREN
),
50 .ecc_cnt_rst_offset
= CV_DRAMINTR_OFST
,
51 .ecc_cnt_rst_mask
= CV_DRAMINTR_INTRCLR
,
52 .ce_ue_trgr_offset
= CV_CTLCFG_OFST
,
53 .ce_set_mask
= CV_CTLCFG_GEN_SB_ERR
,
54 .ue_set_mask
= CV_CTLCFG_GEN_DB_ERR
,
57 static const struct altr_sdram_prv_data a10_data
= {
58 .ecc_ctrl_offset
= A10_ECCCTRL1_OFST
,
59 .ecc_ctl_en_mask
= A10_ECCCTRL1_ECC_EN
,
60 .ecc_stat_offset
= A10_INTSTAT_OFST
,
61 .ecc_stat_ce_mask
= A10_INTSTAT_SBEERR
,
62 .ecc_stat_ue_mask
= A10_INTSTAT_DBEERR
,
63 .ecc_saddr_offset
= A10_SERRADDR_OFST
,
64 .ecc_daddr_offset
= A10_DERRADDR_OFST
,
65 .ecc_irq_en_offset
= A10_ERRINTEN_OFST
,
66 .ecc_irq_en_mask
= A10_ECC_IRQ_EN_MASK
,
67 .ecc_irq_clr_offset
= A10_INTSTAT_OFST
,
68 .ecc_irq_clr_mask
= (A10_INTSTAT_SBEERR
| A10_INTSTAT_DBEERR
),
69 .ecc_cnt_rst_offset
= A10_ECCCTRL1_OFST
,
70 .ecc_cnt_rst_mask
= A10_ECC_CNT_RESET_MASK
,
71 .ce_ue_trgr_offset
= A10_DIAGINTTEST_OFST
,
72 .ce_set_mask
= A10_DIAGINT_TSERRA_MASK
,
73 .ue_set_mask
= A10_DIAGINT_TDERRA_MASK
,
76 /*********************** EDAC Memory Controller Functions ****************/
78 /* The SDRAM controller uses the EDAC Memory Controller framework. */
80 static irqreturn_t
altr_sdram_mc_err_handler(int irq
, void *dev_id
)
82 struct mem_ctl_info
*mci
= dev_id
;
83 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
84 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
85 u32 status
, err_count
= 1, err_addr
;
87 regmap_read(drvdata
->mc_vbase
, priv
->ecc_stat_offset
, &status
);
89 if (status
& priv
->ecc_stat_ue_mask
) {
90 regmap_read(drvdata
->mc_vbase
, priv
->ecc_daddr_offset
,
92 if (priv
->ecc_uecnt_offset
)
93 regmap_read(drvdata
->mc_vbase
, priv
->ecc_uecnt_offset
,
95 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
98 if (status
& priv
->ecc_stat_ce_mask
) {
99 regmap_read(drvdata
->mc_vbase
, priv
->ecc_saddr_offset
,
101 if (priv
->ecc_uecnt_offset
)
102 regmap_read(drvdata
->mc_vbase
, priv
->ecc_cecnt_offset
,
104 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, err_count
,
105 err_addr
>> PAGE_SHIFT
,
106 err_addr
& ~PAGE_MASK
, 0,
107 0, 0, -1, mci
->ctl_name
, "");
108 /* Clear IRQ to resume */
109 regmap_write(drvdata
->mc_vbase
, priv
->ecc_irq_clr_offset
,
110 priv
->ecc_irq_clr_mask
);
117 static ssize_t
altr_sdr_mc_err_inject_write(struct file
*file
,
118 const char __user
*data
,
119 size_t count
, loff_t
*ppos
)
121 struct mem_ctl_info
*mci
= file
->private_data
;
122 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
123 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
125 dma_addr_t dma_handle
;
128 ptemp
= dma_alloc_coherent(mci
->pdev
, 16, &dma_handle
, GFP_KERNEL
);
130 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
131 edac_printk(KERN_ERR
, EDAC_MC
,
132 "Inject: Buffer Allocation error\n");
136 regmap_read(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
138 read_reg
&= ~(priv
->ce_set_mask
| priv
->ue_set_mask
);
140 /* Error are injected by writing a word while the SBE or DBE
141 * bit in the CTLCFG register is set. Reading the word will
142 * trigger the SBE or DBE error and the corresponding IRQ.
145 edac_printk(KERN_ALERT
, EDAC_MC
,
146 "Inject Double bit error\n");
148 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
149 (read_reg
| priv
->ue_set_mask
));
152 edac_printk(KERN_ALERT
, EDAC_MC
,
153 "Inject Single bit error\n");
155 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
156 (read_reg
| priv
->ce_set_mask
));
160 ptemp
[0] = 0x5A5A5A5A;
161 ptemp
[1] = 0xA5A5A5A5;
163 /* Clear the error injection bits */
164 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
, read_reg
);
165 /* Ensure it has been written out */
169 * To trigger the error, we need to read the data back
170 * (the data was written with errors above).
171 * The READ_ONCE macros and printk are used to prevent the
172 * the compiler optimizing these reads out.
174 reg
= READ_ONCE(ptemp
[0]);
175 read_reg
= READ_ONCE(ptemp
[1]);
179 edac_printk(KERN_ALERT
, EDAC_MC
, "Read Data [0x%X, 0x%X]\n",
182 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
187 static const struct file_operations altr_sdr_mc_debug_inject_fops
= {
189 .write
= altr_sdr_mc_err_inject_write
,
190 .llseek
= generic_file_llseek
,
193 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info
*mci
)
195 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
201 edac_debugfs_create_file("altr_trigger", S_IWUSR
, mci
->debugfs
, mci
,
202 &altr_sdr_mc_debug_inject_fops
);
205 /* Get total memory size from Open Firmware DTB */
206 static unsigned long get_total_mem(void)
208 struct device_node
*np
= NULL
;
211 unsigned long total_mem
= 0;
213 for_each_node_by_type(np
, "memory") {
214 ret
= of_address_to_resource(np
, 0, &res
);
218 total_mem
+= resource_size(&res
);
220 edac_dbg(0, "total_mem 0x%lx\n", total_mem
);
224 static const struct of_device_id altr_sdram_ctrl_of_match
[] = {
225 { .compatible
= "altr,sdram-edac", .data
= &c5_data
},
226 { .compatible
= "altr,sdram-edac-a10", .data
= &a10_data
},
229 MODULE_DEVICE_TABLE(of
, altr_sdram_ctrl_of_match
);
231 static int a10_init(struct regmap
*mc_vbase
)
233 if (regmap_update_bits(mc_vbase
, A10_INTMODE_OFST
,
234 A10_INTMODE_SB_INT
, A10_INTMODE_SB_INT
)) {
235 edac_printk(KERN_ERR
, EDAC_MC
,
236 "Error setting SB IRQ mode\n");
240 if (regmap_write(mc_vbase
, A10_SERRCNTREG_OFST
, 1)) {
241 edac_printk(KERN_ERR
, EDAC_MC
,
242 "Error setting trigger count\n");
249 static int a10_unmask_irq(struct platform_device
*pdev
, u32 mask
)
251 void __iomem
*sm_base
;
254 if (!request_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
),
255 dev_name(&pdev
->dev
))) {
256 edac_printk(KERN_ERR
, EDAC_MC
,
257 "Unable to request mem region\n");
261 sm_base
= ioremap(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
263 edac_printk(KERN_ERR
, EDAC_MC
,
264 "Unable to ioremap device\n");
270 iowrite32(mask
, sm_base
);
275 release_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
280 static int altr_sdram_probe(struct platform_device
*pdev
)
282 const struct of_device_id
*id
;
283 struct edac_mc_layer layers
[2];
284 struct mem_ctl_info
*mci
;
285 struct altr_sdram_mc_data
*drvdata
;
286 const struct altr_sdram_prv_data
*priv
;
287 struct regmap
*mc_vbase
;
288 struct dimm_info
*dimm
;
290 int irq
, irq2
, res
= 0;
291 unsigned long mem_size
, irqflags
= 0;
293 id
= of_match_device(altr_sdram_ctrl_of_match
, &pdev
->dev
);
297 /* Grab the register range from the sdr controller in device tree */
298 mc_vbase
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
300 if (IS_ERR(mc_vbase
)) {
301 edac_printk(KERN_ERR
, EDAC_MC
,
302 "regmap for altr,sdr-syscon lookup failed.\n");
306 /* Check specific dependencies for the module */
307 priv
= of_match_node(altr_sdram_ctrl_of_match
,
308 pdev
->dev
.of_node
)->data
;
310 /* Validate the SDRAM controller has ECC enabled */
311 if (regmap_read(mc_vbase
, priv
->ecc_ctrl_offset
, &read_reg
) ||
312 ((read_reg
& priv
->ecc_ctl_en_mask
) != priv
->ecc_ctl_en_mask
)) {
313 edac_printk(KERN_ERR
, EDAC_MC
,
314 "No ECC/ECC disabled [0x%08X]\n", read_reg
);
318 /* Grab memory size from device tree. */
319 mem_size
= get_total_mem();
321 edac_printk(KERN_ERR
, EDAC_MC
, "Unable to calculate memory size\n");
325 /* Ensure the SDRAM Interrupt is disabled */
326 if (regmap_update_bits(mc_vbase
, priv
->ecc_irq_en_offset
,
327 priv
->ecc_irq_en_mask
, 0)) {
328 edac_printk(KERN_ERR
, EDAC_MC
,
329 "Error disabling SDRAM ECC IRQ\n");
333 /* Toggle to clear the SDRAM Error count */
334 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
335 priv
->ecc_cnt_rst_mask
,
336 priv
->ecc_cnt_rst_mask
)) {
337 edac_printk(KERN_ERR
, EDAC_MC
,
338 "Error clearing SDRAM ECC count\n");
342 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
343 priv
->ecc_cnt_rst_mask
, 0)) {
344 edac_printk(KERN_ERR
, EDAC_MC
,
345 "Error clearing SDRAM ECC count\n");
349 irq
= platform_get_irq(pdev
, 0);
351 edac_printk(KERN_ERR
, EDAC_MC
,
352 "No irq %d in DT\n", irq
);
356 /* Arria10 has a 2nd IRQ */
357 irq2
= platform_get_irq(pdev
, 1);
359 layers
[0].type
= EDAC_MC_LAYER_CHIP_SELECT
;
361 layers
[0].is_virt_csrow
= true;
362 layers
[1].type
= EDAC_MC_LAYER_CHANNEL
;
364 layers
[1].is_virt_csrow
= false;
365 mci
= edac_mc_alloc(0, ARRAY_SIZE(layers
), layers
,
366 sizeof(struct altr_sdram_mc_data
));
370 mci
->pdev
= &pdev
->dev
;
371 drvdata
= mci
->pvt_info
;
372 drvdata
->mc_vbase
= mc_vbase
;
373 drvdata
->data
= priv
;
374 platform_set_drvdata(pdev
, mci
);
376 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
377 edac_printk(KERN_ERR
, EDAC_MC
,
378 "Unable to get managed device resource\n");
383 mci
->mtype_cap
= MEM_FLAG_DDR3
;
384 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
385 mci
->edac_cap
= EDAC_FLAG_SECDED
;
386 mci
->mod_name
= EDAC_MOD_STR
;
387 mci
->ctl_name
= dev_name(&pdev
->dev
);
388 mci
->scrub_mode
= SCRUB_SW_SRC
;
389 mci
->dev_name
= dev_name(&pdev
->dev
);
392 dimm
->nr_pages
= ((mem_size
- 1) >> PAGE_SHIFT
) + 1;
394 dimm
->dtype
= DEV_X8
;
395 dimm
->mtype
= MEM_DDR3
;
396 dimm
->edac_mode
= EDAC_SECDED
;
398 res
= edac_mc_add_mc(mci
);
402 /* Only the Arria10 has separate IRQs */
403 if (of_machine_is_compatible("altr,socfpga-arria10")) {
404 /* Arria10 specific initialization */
405 res
= a10_init(mc_vbase
);
409 res
= devm_request_irq(&pdev
->dev
, irq2
,
410 altr_sdram_mc_err_handler
,
411 IRQF_SHARED
, dev_name(&pdev
->dev
), mci
);
413 edac_mc_printk(mci
, KERN_ERR
,
414 "Unable to request irq %d\n", irq2
);
419 res
= a10_unmask_irq(pdev
, A10_DDR0_IRQ_MASK
);
423 irqflags
= IRQF_SHARED
;
426 res
= devm_request_irq(&pdev
->dev
, irq
, altr_sdram_mc_err_handler
,
427 irqflags
, dev_name(&pdev
->dev
), mci
);
429 edac_mc_printk(mci
, KERN_ERR
,
430 "Unable to request irq %d\n", irq
);
435 /* Infrastructure ready - enable the IRQ */
436 if (regmap_update_bits(drvdata
->mc_vbase
, priv
->ecc_irq_en_offset
,
437 priv
->ecc_irq_en_mask
, priv
->ecc_irq_en_mask
)) {
438 edac_mc_printk(mci
, KERN_ERR
,
439 "Error enabling SDRAM ECC IRQ\n");
444 altr_sdr_mc_create_debugfs_nodes(mci
);
446 devres_close_group(&pdev
->dev
, NULL
);
451 edac_mc_del_mc(&pdev
->dev
);
453 devres_release_group(&pdev
->dev
, NULL
);
456 edac_printk(KERN_ERR
, EDAC_MC
,
457 "EDAC Probe Failed; Error %d\n", res
);
462 static int altr_sdram_remove(struct platform_device
*pdev
)
464 struct mem_ctl_info
*mci
= platform_get_drvdata(pdev
);
466 edac_mc_del_mc(&pdev
->dev
);
468 platform_set_drvdata(pdev
, NULL
);
474 * If you want to suspend, need to disable EDAC by removing it
475 * from the device tree or defconfig.
478 static int altr_sdram_prepare(struct device
*dev
)
480 pr_err("Suspend not allowed when EDAC is enabled.\n");
485 static const struct dev_pm_ops altr_sdram_pm_ops
= {
486 .prepare
= altr_sdram_prepare
,
490 static struct platform_driver altr_sdram_edac_driver
= {
491 .probe
= altr_sdram_probe
,
492 .remove
= altr_sdram_remove
,
494 .name
= "altr_sdram_edac",
496 .pm
= &altr_sdram_pm_ops
,
498 .of_match_table
= altr_sdram_ctrl_of_match
,
502 module_platform_driver(altr_sdram_edac_driver
);
504 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
506 /************************* EDAC Parent Probe *************************/
508 static const struct of_device_id altr_edac_device_of_match
[];
510 static const struct of_device_id altr_edac_of_match
[] = {
511 { .compatible
= "altr,socfpga-ecc-manager" },
514 MODULE_DEVICE_TABLE(of
, altr_edac_of_match
);
516 static int altr_edac_probe(struct platform_device
*pdev
)
518 of_platform_populate(pdev
->dev
.of_node
, altr_edac_device_of_match
,
523 static struct platform_driver altr_edac_driver
= {
524 .probe
= altr_edac_probe
,
526 .name
= "socfpga_ecc_manager",
527 .of_match_table
= altr_edac_of_match
,
530 module_platform_driver(altr_edac_driver
);
532 /************************* EDAC Device Functions *************************/
535 * EDAC Device Functions (shared between various IPs).
536 * The discrete memories use the EDAC Device framework. The probe
537 * and error handling functions are very similar between memories
538 * so they are shared. The memory allocation and freeing for EDAC
539 * trigger testing are different for each memory.
542 #ifdef CONFIG_EDAC_ALTERA_OCRAM
543 static const struct edac_device_prv_data ocramecc_data
;
545 #ifdef CONFIG_EDAC_ALTERA_L2C
546 static const struct edac_device_prv_data l2ecc_data
;
548 #ifdef CONFIG_EDAC_ALTERA_OCRAM
549 static const struct edac_device_prv_data a10_ocramecc_data
;
551 #ifdef CONFIG_EDAC_ALTERA_L2C
552 static const struct edac_device_prv_data a10_l2ecc_data
;
555 static irqreturn_t
altr_edac_device_handler(int irq
, void *dev_id
)
557 irqreturn_t ret_value
= IRQ_NONE
;
558 struct edac_device_ctl_info
*dci
= dev_id
;
559 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
560 const struct edac_device_prv_data
*priv
= drvdata
->data
;
562 if (irq
== drvdata
->sb_irq
) {
563 if (priv
->ce_clear_mask
)
564 writel(priv
->ce_clear_mask
, drvdata
->base
);
565 edac_device_handle_ce(dci
, 0, 0, drvdata
->edac_dev_name
);
566 ret_value
= IRQ_HANDLED
;
567 } else if (irq
== drvdata
->db_irq
) {
568 if (priv
->ue_clear_mask
)
569 writel(priv
->ue_clear_mask
, drvdata
->base
);
570 edac_device_handle_ue(dci
, 0, 0, drvdata
->edac_dev_name
);
571 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
572 ret_value
= IRQ_HANDLED
;
580 static ssize_t __maybe_unused
581 altr_edac_device_trig(struct file
*file
, const char __user
*user_buf
,
582 size_t count
, loff_t
*ppos
)
585 u32
*ptemp
, i
, error_mask
;
589 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
590 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
591 const struct edac_device_prv_data
*priv
= drvdata
->data
;
592 void *generic_ptr
= edac_dci
->dev
;
594 if (!user_buf
|| get_user(trig_type
, user_buf
))
597 if (!priv
->alloc_mem
)
601 * Note that generic_ptr is initialized to the device * but in
602 * some alloc_functions, this is overridden and returns data.
604 ptemp
= priv
->alloc_mem(priv
->trig_alloc_sz
, &generic_ptr
);
606 edac_printk(KERN_ERR
, EDAC_DEVICE
,
607 "Inject: Buffer Allocation error\n");
611 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
612 error_mask
= priv
->ue_set_mask
;
614 error_mask
= priv
->ce_set_mask
;
616 edac_printk(KERN_ALERT
, EDAC_DEVICE
,
617 "Trigger Error Mask (0x%X)\n", error_mask
);
619 local_irq_save(flags
);
620 /* write ECC corrupted data out. */
621 for (i
= 0; i
< (priv
->trig_alloc_sz
/ sizeof(*ptemp
)); i
++) {
622 /* Read data so we're in the correct state */
624 if (READ_ONCE(ptemp
[i
]))
626 /* Toggle Error bit (it is latched), leave ECC enabled */
627 writel(error_mask
, (drvdata
->base
+ priv
->set_err_ofst
));
628 writel(priv
->ecc_enable_mask
, (drvdata
->base
+
629 priv
->set_err_ofst
));
632 /* Ensure it has been written out */
634 local_irq_restore(flags
);
637 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Mem Not Cleared\n");
639 /* Read out written data. ECC error caused here */
640 for (i
= 0; i
< ALTR_TRIGGER_READ_WRD_CNT
; i
++)
641 if (READ_ONCE(ptemp
[i
]) != i
)
642 edac_printk(KERN_ERR
, EDAC_DEVICE
,
643 "Read doesn't match written data\n");
646 priv
->free_mem(ptemp
, priv
->trig_alloc_sz
, generic_ptr
);
651 static const struct file_operations altr_edac_device_inject_fops __maybe_unused
= {
653 .write
= altr_edac_device_trig
,
654 .llseek
= generic_file_llseek
,
657 static ssize_t __maybe_unused
658 altr_edac_a10_device_trig(struct file
*file
, const char __user
*user_buf
,
659 size_t count
, loff_t
*ppos
);
661 static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused
= {
663 .write
= altr_edac_a10_device_trig
,
664 .llseek
= generic_file_llseek
,
667 static ssize_t __maybe_unused
668 altr_edac_a10_device_trig2(struct file
*file
, const char __user
*user_buf
,
669 size_t count
, loff_t
*ppos
);
671 static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused
= {
673 .write
= altr_edac_a10_device_trig2
,
674 .llseek
= generic_file_llseek
,
677 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info
*edac_dci
,
678 const struct edac_device_prv_data
*priv
)
680 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
682 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
685 drvdata
->debugfs_dir
= edac_debugfs_create_dir(drvdata
->edac_dev_name
);
686 if (!drvdata
->debugfs_dir
)
689 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR
,
690 drvdata
->debugfs_dir
, edac_dci
,
692 debugfs_remove_recursive(drvdata
->debugfs_dir
);
695 static const struct of_device_id altr_edac_device_of_match
[] = {
696 #ifdef CONFIG_EDAC_ALTERA_L2C
697 { .compatible
= "altr,socfpga-l2-ecc", .data
= &l2ecc_data
},
699 #ifdef CONFIG_EDAC_ALTERA_OCRAM
700 { .compatible
= "altr,socfpga-ocram-ecc", .data
= &ocramecc_data
},
704 MODULE_DEVICE_TABLE(of
, altr_edac_device_of_match
);
707 * altr_edac_device_probe()
708 * This is a generic EDAC device driver that will support
709 * various Altera memory devices such as the L2 cache ECC and
710 * OCRAM ECC as well as the memories for other peripherals.
711 * Module specific initialization is done by passing the
712 * function index in the device tree.
714 static int altr_edac_device_probe(struct platform_device
*pdev
)
716 struct edac_device_ctl_info
*dci
;
717 struct altr_edac_device_dev
*drvdata
;
720 struct device_node
*np
= pdev
->dev
.of_node
;
721 char *ecc_name
= (char *)np
->name
;
722 static int dev_instance
;
724 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
725 edac_printk(KERN_ERR
, EDAC_DEVICE
,
726 "Unable to open devm\n");
730 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
732 edac_printk(KERN_ERR
, EDAC_DEVICE
,
733 "Unable to get mem resource\n");
738 if (!devm_request_mem_region(&pdev
->dev
, r
->start
, resource_size(r
),
739 dev_name(&pdev
->dev
))) {
740 edac_printk(KERN_ERR
, EDAC_DEVICE
,
741 "%s:Error requesting mem region\n", ecc_name
);
746 dci
= edac_device_alloc_ctl_info(sizeof(*drvdata
), ecc_name
,
747 1, ecc_name
, 1, 0, NULL
, 0,
751 edac_printk(KERN_ERR
, EDAC_DEVICE
,
752 "%s: Unable to allocate EDAC device\n", ecc_name
);
757 drvdata
= dci
->pvt_info
;
758 dci
->dev
= &pdev
->dev
;
759 platform_set_drvdata(pdev
, dci
);
760 drvdata
->edac_dev_name
= ecc_name
;
762 drvdata
->base
= devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
763 if (!drvdata
->base
) {
768 /* Get driver specific data for this EDAC device */
769 drvdata
->data
= of_match_node(altr_edac_device_of_match
, np
)->data
;
771 /* Check specific dependencies for the module */
772 if (drvdata
->data
->setup
) {
773 res
= drvdata
->data
->setup(drvdata
);
778 drvdata
->sb_irq
= platform_get_irq(pdev
, 0);
779 res
= devm_request_irq(&pdev
->dev
, drvdata
->sb_irq
,
780 altr_edac_device_handler
,
781 0, dev_name(&pdev
->dev
), dci
);
785 drvdata
->db_irq
= platform_get_irq(pdev
, 1);
786 res
= devm_request_irq(&pdev
->dev
, drvdata
->db_irq
,
787 altr_edac_device_handler
,
788 0, dev_name(&pdev
->dev
), dci
);
792 dci
->mod_name
= "Altera ECC Manager";
793 dci
->dev_name
= drvdata
->edac_dev_name
;
795 res
= edac_device_add_device(dci
);
799 altr_create_edacdev_dbgfs(dci
, drvdata
->data
);
801 devres_close_group(&pdev
->dev
, NULL
);
806 edac_device_free_ctl_info(dci
);
808 devres_release_group(&pdev
->dev
, NULL
);
809 edac_printk(KERN_ERR
, EDAC_DEVICE
,
810 "%s:Error setting up EDAC device: %d\n", ecc_name
, res
);
815 static int altr_edac_device_remove(struct platform_device
*pdev
)
817 struct edac_device_ctl_info
*dci
= platform_get_drvdata(pdev
);
818 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
820 debugfs_remove_recursive(drvdata
->debugfs_dir
);
821 edac_device_del_device(&pdev
->dev
);
822 edac_device_free_ctl_info(dci
);
827 static struct platform_driver altr_edac_device_driver
= {
828 .probe
= altr_edac_device_probe
,
829 .remove
= altr_edac_device_remove
,
831 .name
= "altr_edac_device",
832 .of_match_table
= altr_edac_device_of_match
,
835 module_platform_driver(altr_edac_device_driver
);
837 /******************* Arria10 Device ECC Shared Functions *****************/
840 * Test for memory's ECC dependencies upon entry because platform specific
841 * startup should have initialized the memory and enabled the ECC.
842 * Can't turn on ECC here because accessing un-initialized memory will
843 * cause CE/UE errors possibly causing an ABORT.
845 static int __maybe_unused
846 altr_check_ecc_deps(struct altr_edac_device_dev
*device
)
848 void __iomem
*base
= device
->base
;
849 const struct edac_device_prv_data
*prv
= device
->data
;
851 if (readl(base
+ prv
->ecc_en_ofst
) & prv
->ecc_enable_mask
)
854 edac_printk(KERN_ERR
, EDAC_DEVICE
,
855 "%s: No ECC present or ECC disabled.\n",
856 device
->edac_dev_name
);
860 static irqreturn_t __maybe_unused
altr_edac_a10_ecc_irq(int irq
, void *dev_id
)
862 struct altr_edac_device_dev
*dci
= dev_id
;
863 void __iomem
*base
= dci
->base
;
865 if (irq
== dci
->sb_irq
) {
866 writel(ALTR_A10_ECC_SERRPENA
,
867 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
868 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
871 } else if (irq
== dci
->db_irq
) {
872 writel(ALTR_A10_ECC_DERRPENA
,
873 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
874 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
875 if (dci
->data
->panic
)
876 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
886 /******************* Arria10 Memory Buffer Functions *********************/
888 static inline int a10_get_irq_mask(struct device_node
*np
)
891 const u32
*handle
= of_get_property(np
, "interrupts", NULL
);
895 irq
= be32_to_cpup(handle
);
899 static inline void ecc_set_bits(u32 bit_mask
, void __iomem
*ioaddr
)
901 u32 value
= readl(ioaddr
);
904 writel(value
, ioaddr
);
907 static inline void ecc_clear_bits(u32 bit_mask
, void __iomem
*ioaddr
)
909 u32 value
= readl(ioaddr
);
912 writel(value
, ioaddr
);
915 static inline int ecc_test_bits(u32 bit_mask
, void __iomem
*ioaddr
)
917 u32 value
= readl(ioaddr
);
919 return (value
& bit_mask
) ? 1 : 0;
923 * This function uses the memory initialization block in the Arria10 ECC
924 * controller to initialize/clear the entire memory data and ECC data.
926 static int __maybe_unused
altr_init_memory_port(void __iomem
*ioaddr
, int port
)
928 int limit
= ALTR_A10_ECC_INIT_WATCHDOG_10US
;
929 u32 init_mask
, stat_mask
, clear_mask
;
933 init_mask
= ALTR_A10_ECC_INITB
;
934 stat_mask
= ALTR_A10_ECC_INITCOMPLETEB
;
935 clear_mask
= ALTR_A10_ECC_ERRPENB_MASK
;
937 init_mask
= ALTR_A10_ECC_INITA
;
938 stat_mask
= ALTR_A10_ECC_INITCOMPLETEA
;
939 clear_mask
= ALTR_A10_ECC_ERRPENA_MASK
;
942 ecc_set_bits(init_mask
, (ioaddr
+ ALTR_A10_ECC_CTRL_OFST
));
944 if (ecc_test_bits(stat_mask
,
945 (ioaddr
+ ALTR_A10_ECC_INITSTAT_OFST
)))
952 /* Clear any pending ECC interrupts */
953 writel(clear_mask
, (ioaddr
+ ALTR_A10_ECC_INTSTAT_OFST
));
958 static __init
int __maybe_unused
959 altr_init_a10_ecc_block(struct device_node
*np
, u32 irq_mask
,
960 u32 ecc_ctrl_en_mask
, bool dual_port
)
963 void __iomem
*ecc_block_base
;
964 struct regmap
*ecc_mgr_map
;
966 struct device_node
*np_eccmgr
;
968 ecc_name
= (char *)np
->name
;
970 /* Get the ECC Manager - parent of the device EDACs */
971 np_eccmgr
= of_get_parent(np
);
974 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr
,
975 "altr,sysmgr-syscon");
977 of_node_put(np_eccmgr
);
978 if (IS_ERR(ecc_mgr_map
)) {
979 edac_printk(KERN_ERR
, EDAC_DEVICE
,
980 "Unable to get syscon altr,sysmgr-syscon\n");
984 /* Map the ECC Block */
985 ecc_block_base
= of_iomap(np
, 0);
986 if (!ecc_block_base
) {
987 edac_printk(KERN_ERR
, EDAC_DEVICE
,
988 "Unable to map %s ECC block\n", ecc_name
);
993 regmap_write(ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_SET_OFST
, irq_mask
);
994 writel(ALTR_A10_ECC_SERRINTEN
,
995 (ecc_block_base
+ ALTR_A10_ECC_ERRINTENR_OFST
));
996 ecc_clear_bits(ecc_ctrl_en_mask
,
997 (ecc_block_base
+ ALTR_A10_ECC_CTRL_OFST
));
998 /* Ensure all writes complete */
1000 /* Use HW initialization block to initialize memory for ECC */
1001 ret
= altr_init_memory_port(ecc_block_base
, 0);
1003 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1004 "ECC: cannot init %s PORTA memory\n", ecc_name
);
1009 ret
= altr_init_memory_port(ecc_block_base
, 1);
1011 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1012 "ECC: cannot init %s PORTB memory\n",
1018 /* Interrupt mode set to every SBERR */
1019 regmap_write(ecc_mgr_map
, ALTR_A10_ECC_INTMODE_OFST
,
1020 ALTR_A10_ECC_INTMODE
);
1022 ecc_set_bits(ecc_ctrl_en_mask
, (ecc_block_base
+
1023 ALTR_A10_ECC_CTRL_OFST
));
1024 writel(ALTR_A10_ECC_SERRINTEN
,
1025 (ecc_block_base
+ ALTR_A10_ECC_ERRINTENS_OFST
));
1026 regmap_write(ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_CLR_OFST
, irq_mask
);
1027 /* Ensure all writes complete */
1030 iounmap(ecc_block_base
);
1034 static int validate_parent_available(struct device_node
*np
);
1035 static const struct of_device_id altr_edac_a10_device_of_match
[];
1036 static int __init __maybe_unused
altr_init_a10_ecc_device_type(char *compat
)
1039 struct device_node
*child
, *np
;
1041 np
= of_find_compatible_node(NULL
, NULL
,
1042 "altr,socfpga-a10-ecc-manager");
1044 edac_printk(KERN_ERR
, EDAC_DEVICE
, "ECC Manager not found\n");
1048 for_each_child_of_node(np
, child
) {
1049 const struct of_device_id
*pdev_id
;
1050 const struct edac_device_prv_data
*prv
;
1052 if (!of_device_is_available(child
))
1054 if (!of_device_is_compatible(child
, compat
))
1057 if (validate_parent_available(child
))
1060 irq
= a10_get_irq_mask(child
);
1064 /* Get matching node and check for valid result */
1065 pdev_id
= of_match_node(altr_edac_a10_device_of_match
, child
);
1066 if (IS_ERR_OR_NULL(pdev_id
))
1069 /* Validate private data pointer before dereferencing */
1070 prv
= pdev_id
->data
;
1074 altr_init_a10_ecc_block(child
, BIT(irq
),
1075 prv
->ecc_enable_mask
, 0);
1082 /*********************** SDRAM EDAC Device Functions *********************/
1084 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1086 static const struct edac_device_prv_data s10_sdramecc_data
= {
1087 .setup
= altr_check_ecc_deps
,
1088 .ce_clear_mask
= ALTR_S10_ECC_SERRPENA
,
1089 .ue_clear_mask
= ALTR_S10_ECC_DERRPENA
,
1090 .ecc_enable_mask
= ALTR_S10_ECC_EN
,
1091 .ecc_en_ofst
= ALTR_S10_ECC_CTRL_SDRAM_OFST
,
1092 .ce_set_mask
= ALTR_S10_ECC_TSERRA
,
1093 .ue_set_mask
= ALTR_S10_ECC_TDERRA
,
1094 .set_err_ofst
= ALTR_S10_ECC_INTTEST_OFST
,
1095 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1096 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1098 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
1100 /*********************** OCRAM EDAC Device Functions *********************/
1102 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1104 static void *ocram_alloc_mem(size_t size
, void **other
)
1106 struct device_node
*np
;
1107 struct gen_pool
*gp
;
1110 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-ocram-ecc");
1114 gp
= of_gen_pool_get(np
, "iram", 0);
1119 sram_addr
= (void *)gen_pool_alloc(gp
, size
);
1123 memset(sram_addr
, 0, size
);
1124 /* Ensure data is written out */
1127 /* Remember this handle for freeing later */
1133 static void ocram_free_mem(void *p
, size_t size
, void *other
)
1135 gen_pool_free((struct gen_pool
*)other
, (unsigned long)p
, size
);
1138 static const struct edac_device_prv_data ocramecc_data
= {
1139 .setup
= altr_check_ecc_deps
,
1140 .ce_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_SERR
),
1141 .ue_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_DERR
),
1142 .alloc_mem
= ocram_alloc_mem
,
1143 .free_mem
= ocram_free_mem
,
1144 .ecc_enable_mask
= ALTR_OCR_ECC_EN
,
1145 .ecc_en_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
1146 .ce_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJS
),
1147 .ue_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJD
),
1148 .set_err_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
1149 .trig_alloc_sz
= ALTR_TRIG_OCRAM_BYTE_SIZE
,
1150 .inject_fops
= &altr_edac_device_inject_fops
,
1153 static int __maybe_unused
1154 altr_check_ocram_deps_init(struct altr_edac_device_dev
*device
)
1156 void __iomem
*base
= device
->base
;
1159 ret
= altr_check_ecc_deps(device
);
1163 /* Verify OCRAM has been initialized */
1164 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA
,
1165 (base
+ ALTR_A10_ECC_INITSTAT_OFST
)))
1168 /* Enable IRQ on Single Bit Error */
1169 writel(ALTR_A10_ECC_SERRINTEN
, (base
+ ALTR_A10_ECC_ERRINTENS_OFST
));
1170 /* Ensure all writes complete */
1176 static const struct edac_device_prv_data a10_ocramecc_data
= {
1177 .setup
= altr_check_ocram_deps_init
,
1178 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1179 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1180 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_OCRAM
,
1181 .ecc_enable_mask
= ALTR_A10_OCRAM_ECC_EN_CTL
,
1182 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1183 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1184 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1185 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1186 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1187 .inject_fops
= &altr_edac_a10_device_inject2_fops
,
1189 * OCRAM panic on uncorrectable error because sleep/resume
1190 * functions and FPGA contents are stored in OCRAM. Prefer
1191 * a kernel panic over executing/loading corrupted data.
1196 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1198 /********************* L2 Cache EDAC Device Functions ********************/
1200 #ifdef CONFIG_EDAC_ALTERA_L2C
1202 static void *l2_alloc_mem(size_t size
, void **other
)
1204 struct device
*dev
= *other
;
1205 void *ptemp
= devm_kzalloc(dev
, size
, GFP_KERNEL
);
1210 /* Make sure everything is written out */
1214 * Clean all cache levels up to LoC (includes L2)
1215 * This ensures the corrupted data is written into
1216 * L2 cache for readback test (which causes ECC error).
1223 static void l2_free_mem(void *p
, size_t size
, void *other
)
1225 struct device
*dev
= other
;
1232 * altr_l2_check_deps()
1233 * Test for L2 cache ECC dependencies upon entry because
1234 * platform specific startup should have initialized the L2
1235 * memory and enabled the ECC.
1236 * Bail if ECC is not enabled.
1237 * Note that L2 Cache Enable is forced at build time.
1239 static int altr_l2_check_deps(struct altr_edac_device_dev
*device
)
1241 void __iomem
*base
= device
->base
;
1242 const struct edac_device_prv_data
*prv
= device
->data
;
1244 if ((readl(base
) & prv
->ecc_enable_mask
) ==
1245 prv
->ecc_enable_mask
)
1248 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1249 "L2: No ECC present, or ECC disabled\n");
1253 static irqreturn_t
altr_edac_a10_l2_irq(int irq
, void *dev_id
)
1255 struct altr_edac_device_dev
*dci
= dev_id
;
1257 if (irq
== dci
->sb_irq
) {
1258 regmap_write(dci
->edac
->ecc_mgr_map
,
1259 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
1260 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB
);
1261 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
1264 } else if (irq
== dci
->db_irq
) {
1265 regmap_write(dci
->edac
->ecc_mgr_map
,
1266 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
1267 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB
);
1268 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
1269 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1279 static const struct edac_device_prv_data l2ecc_data
= {
1280 .setup
= altr_l2_check_deps
,
1283 .alloc_mem
= l2_alloc_mem
,
1284 .free_mem
= l2_free_mem
,
1285 .ecc_enable_mask
= ALTR_L2_ECC_EN
,
1286 .ce_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJS
),
1287 .ue_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJD
),
1288 .set_err_ofst
= ALTR_L2_ECC_REG_OFFSET
,
1289 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
1290 .inject_fops
= &altr_edac_device_inject_fops
,
1293 static const struct edac_device_prv_data a10_l2ecc_data
= {
1294 .setup
= altr_l2_check_deps
,
1295 .ce_clear_mask
= ALTR_A10_L2_ECC_SERR_CLR
,
1296 .ue_clear_mask
= ALTR_A10_L2_ECC_MERR_CLR
,
1297 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_L2
,
1298 .alloc_mem
= l2_alloc_mem
,
1299 .free_mem
= l2_free_mem
,
1300 .ecc_enable_mask
= ALTR_A10_L2_ECC_EN_CTL
,
1301 .ce_set_mask
= ALTR_A10_L2_ECC_CE_INJ_MASK
,
1302 .ue_set_mask
= ALTR_A10_L2_ECC_UE_INJ_MASK
,
1303 .set_err_ofst
= ALTR_A10_L2_ECC_INJ_OFST
,
1304 .ecc_irq_handler
= altr_edac_a10_l2_irq
,
1305 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
1306 .inject_fops
= &altr_edac_device_inject_fops
,
1309 #endif /* CONFIG_EDAC_ALTERA_L2C */
1311 /********************* Ethernet Device Functions ********************/
1313 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1315 static int __init
socfpga_init_ethernet_ecc(struct altr_edac_device_dev
*dev
)
1319 ret
= altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1323 return altr_check_ecc_deps(dev
);
1326 static const struct edac_device_prv_data a10_enetecc_data
= {
1327 .setup
= socfpga_init_ethernet_ecc
,
1328 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1329 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1330 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1331 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1332 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1333 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1334 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1335 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1336 .inject_fops
= &altr_edac_a10_device_inject2_fops
,
1339 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1341 /********************** NAND Device Functions **********************/
1343 #ifdef CONFIG_EDAC_ALTERA_NAND
1345 static int __init
socfpga_init_nand_ecc(struct altr_edac_device_dev
*device
)
1349 ret
= altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1353 return altr_check_ecc_deps(device
);
1356 static const struct edac_device_prv_data a10_nandecc_data
= {
1357 .setup
= socfpga_init_nand_ecc
,
1358 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1359 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1360 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1361 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1362 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1363 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1364 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1365 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1366 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1369 #endif /* CONFIG_EDAC_ALTERA_NAND */
1371 /********************** DMA Device Functions **********************/
1373 #ifdef CONFIG_EDAC_ALTERA_DMA
1375 static int __init
socfpga_init_dma_ecc(struct altr_edac_device_dev
*device
)
1379 ret
= altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1383 return altr_check_ecc_deps(device
);
1386 static const struct edac_device_prv_data a10_dmaecc_data
= {
1387 .setup
= socfpga_init_dma_ecc
,
1388 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1389 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1390 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1391 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1392 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1393 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1394 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1395 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1396 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1399 #endif /* CONFIG_EDAC_ALTERA_DMA */
1401 /********************** USB Device Functions **********************/
1403 #ifdef CONFIG_EDAC_ALTERA_USB
1405 static int __init
socfpga_init_usb_ecc(struct altr_edac_device_dev
*device
)
1409 ret
= altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1413 return altr_check_ecc_deps(device
);
1416 static const struct edac_device_prv_data a10_usbecc_data
= {
1417 .setup
= socfpga_init_usb_ecc
,
1418 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1419 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1420 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1421 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1422 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1423 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1424 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1425 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1426 .inject_fops
= &altr_edac_a10_device_inject2_fops
,
1429 #endif /* CONFIG_EDAC_ALTERA_USB */
1431 /********************** QSPI Device Functions **********************/
1433 #ifdef CONFIG_EDAC_ALTERA_QSPI
1435 static int __init
socfpga_init_qspi_ecc(struct altr_edac_device_dev
*device
)
1439 ret
= altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1443 return altr_check_ecc_deps(device
);
1446 static const struct edac_device_prv_data a10_qspiecc_data
= {
1447 .setup
= socfpga_init_qspi_ecc
,
1448 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1449 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1450 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1451 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1452 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1453 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1454 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1455 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1456 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1459 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1461 /********************* SDMMC Device Functions **********************/
1463 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1465 static const struct edac_device_prv_data a10_sdmmceccb_data
;
1466 static int altr_portb_setup(struct altr_edac_device_dev
*device
)
1468 struct edac_device_ctl_info
*dci
;
1469 struct altr_edac_device_dev
*altdev
;
1470 char *ecc_name
= "sdmmcb-ecc";
1472 struct device_node
*np
;
1473 const struct edac_device_prv_data
*prv
= &a10_sdmmceccb_data
;
1475 rc
= altr_check_ecc_deps(device
);
1479 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-sdmmc-ecc");
1481 edac_printk(KERN_WARNING
, EDAC_DEVICE
, "SDMMC node not found\n");
1485 /* Create the PortB EDAC device */
1486 edac_idx
= edac_device_alloc_index();
1487 dci
= edac_device_alloc_ctl_info(sizeof(*altdev
), ecc_name
, 1,
1488 ecc_name
, 1, 0, NULL
, 0, edac_idx
);
1490 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1491 "%s: Unable to allocate PortB EDAC device\n",
1496 /* Initialize the PortB EDAC device structure from PortA structure */
1497 altdev
= dci
->pvt_info
;
1500 if (!devres_open_group(&altdev
->ddev
, altr_portb_setup
, GFP_KERNEL
))
1503 /* Update PortB specific values */
1504 altdev
->edac_dev_name
= ecc_name
;
1505 altdev
->edac_idx
= edac_idx
;
1506 altdev
->edac_dev
= dci
;
1508 dci
->dev
= &altdev
->ddev
;
1509 dci
->ctl_name
= "Altera ECC Manager";
1510 dci
->mod_name
= ecc_name
;
1511 dci
->dev_name
= ecc_name
;
1514 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly
1516 * FIXME: Instead of ifdefs with different architectures the driver
1517 * should properly use compatibles.
1520 altdev
->sb_irq
= irq_of_parse_and_map(np
, 1);
1522 altdev
->sb_irq
= irq_of_parse_and_map(np
, 2);
1524 if (!altdev
->sb_irq
) {
1525 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error PortB SBIRQ alloc\n");
1527 goto err_release_group_1
;
1529 rc
= devm_request_irq(&altdev
->ddev
, altdev
->sb_irq
,
1530 prv
->ecc_irq_handler
,
1531 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1534 edac_printk(KERN_ERR
, EDAC_DEVICE
, "PortB SBERR IRQ error\n");
1535 goto err_release_group_1
;
1539 /* Use IRQ to determine SError origin instead of assigning IRQ */
1540 rc
= of_property_read_u32_index(np
, "interrupts", 1, &altdev
->db_irq
);
1542 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1543 "Error PortB DBIRQ alloc\n");
1544 goto err_release_group_1
;
1547 altdev
->db_irq
= irq_of_parse_and_map(np
, 3);
1548 if (!altdev
->db_irq
) {
1549 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error PortB DBIRQ alloc\n");
1551 goto err_release_group_1
;
1553 rc
= devm_request_irq(&altdev
->ddev
, altdev
->db_irq
,
1554 prv
->ecc_irq_handler
,
1555 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1558 edac_printk(KERN_ERR
, EDAC_DEVICE
, "PortB DBERR IRQ error\n");
1559 goto err_release_group_1
;
1563 rc
= edac_device_add_device(dci
);
1565 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1566 "edac_device_add_device portB failed\n");
1568 goto err_release_group_1
;
1570 altr_create_edacdev_dbgfs(dci
, prv
);
1572 list_add(&altdev
->next
, &altdev
->edac
->a10_ecc_devices
);
1574 devres_remove_group(&altdev
->ddev
, altr_portb_setup
);
1578 err_release_group_1
:
1579 edac_device_free_ctl_info(dci
);
1580 devres_release_group(&altdev
->ddev
, altr_portb_setup
);
1581 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1582 "%s:Error setting up EDAC device: %d\n", ecc_name
, rc
);
1586 static int __init
socfpga_init_sdmmc_ecc(struct altr_edac_device_dev
*device
)
1589 struct device_node
*child
;
1591 child
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-sdmmc-ecc");
1595 if (!of_device_is_available(child
))
1598 if (validate_parent_available(child
))
1602 rc
= altr_init_a10_ecc_block(child
, ALTR_A10_SDMMC_IRQ_MASK
,
1603 a10_sdmmceccb_data
.ecc_enable_mask
, 1);
1608 return altr_portb_setup(device
);
1615 static irqreturn_t
altr_edac_a10_ecc_irq_portb(int irq
, void *dev_id
)
1617 struct altr_edac_device_dev
*ad
= dev_id
;
1618 void __iomem
*base
= ad
->base
;
1619 const struct edac_device_prv_data
*priv
= ad
->data
;
1621 if (irq
== ad
->sb_irq
) {
1622 writel(priv
->ce_clear_mask
,
1623 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
1624 edac_device_handle_ce(ad
->edac_dev
, 0, 0, ad
->edac_dev_name
);
1626 } else if (irq
== ad
->db_irq
) {
1627 writel(priv
->ue_clear_mask
,
1628 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
1629 edac_device_handle_ue(ad
->edac_dev
, 0, 0, ad
->edac_dev_name
);
1633 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq
);
1638 static const struct edac_device_prv_data a10_sdmmcecca_data
= {
1639 .setup
= socfpga_init_sdmmc_ecc
,
1640 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1641 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1642 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1643 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1644 .ce_set_mask
= ALTR_A10_ECC_SERRPENA
,
1645 .ue_set_mask
= ALTR_A10_ECC_DERRPENA
,
1646 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1647 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1648 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1651 static const struct edac_device_prv_data a10_sdmmceccb_data
= {
1652 .setup
= socfpga_init_sdmmc_ecc
,
1653 .ce_clear_mask
= ALTR_A10_ECC_SERRPENB
,
1654 .ue_clear_mask
= ALTR_A10_ECC_DERRPENB
,
1655 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1656 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1657 .ce_set_mask
= ALTR_A10_ECC_TSERRB
,
1658 .ue_set_mask
= ALTR_A10_ECC_TDERRB
,
1659 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1660 .ecc_irq_handler
= altr_edac_a10_ecc_irq_portb
,
1661 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1664 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1666 /********************* Arria10 EDAC Device Functions *************************/
1667 static const struct of_device_id altr_edac_a10_device_of_match
[] = {
1668 #ifdef CONFIG_EDAC_ALTERA_L2C
1669 { .compatible
= "altr,socfpga-a10-l2-ecc", .data
= &a10_l2ecc_data
},
1671 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1672 { .compatible
= "altr,socfpga-a10-ocram-ecc",
1673 .data
= &a10_ocramecc_data
},
1675 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1676 { .compatible
= "altr,socfpga-eth-mac-ecc",
1677 .data
= &a10_enetecc_data
},
1679 #ifdef CONFIG_EDAC_ALTERA_NAND
1680 { .compatible
= "altr,socfpga-nand-ecc", .data
= &a10_nandecc_data
},
1682 #ifdef CONFIG_EDAC_ALTERA_DMA
1683 { .compatible
= "altr,socfpga-dma-ecc", .data
= &a10_dmaecc_data
},
1685 #ifdef CONFIG_EDAC_ALTERA_USB
1686 { .compatible
= "altr,socfpga-usb-ecc", .data
= &a10_usbecc_data
},
1688 #ifdef CONFIG_EDAC_ALTERA_QSPI
1689 { .compatible
= "altr,socfpga-qspi-ecc", .data
= &a10_qspiecc_data
},
1691 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1692 { .compatible
= "altr,socfpga-sdmmc-ecc", .data
= &a10_sdmmcecca_data
},
1694 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1695 { .compatible
= "altr,sdram-edac-s10", .data
= &s10_sdramecc_data
},
1699 MODULE_DEVICE_TABLE(of
, altr_edac_a10_device_of_match
);
1702 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1703 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1704 * manager manages the IRQs and the children.
1705 * Based on xgene_edac.c peripheral code.
1708 static ssize_t __maybe_unused
1709 altr_edac_a10_device_trig(struct file
*file
, const char __user
*user_buf
,
1710 size_t count
, loff_t
*ppos
)
1712 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
1713 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
1714 const struct edac_device_prv_data
*priv
= drvdata
->data
;
1715 void __iomem
*set_addr
= (drvdata
->base
+ priv
->set_err_ofst
);
1716 unsigned long flags
;
1719 if (!user_buf
|| get_user(trig_type
, user_buf
))
1722 local_irq_save(flags
);
1723 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
1724 writel(priv
->ue_set_mask
, set_addr
);
1726 writel(priv
->ce_set_mask
, set_addr
);
1728 /* Ensure the interrupt test bits are set */
1730 local_irq_restore(flags
);
1736 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1737 * slightly. A few Arria10 peripherals can use this injection function.
1738 * Inject the error into the memory and then readback to trigger the IRQ.
1740 static ssize_t __maybe_unused
1741 altr_edac_a10_device_trig2(struct file
*file
, const char __user
*user_buf
,
1742 size_t count
, loff_t
*ppos
)
1744 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
1745 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
1746 const struct edac_device_prv_data
*priv
= drvdata
->data
;
1747 void __iomem
*set_addr
= (drvdata
->base
+ priv
->set_err_ofst
);
1748 unsigned long flags
;
1751 if (!user_buf
|| get_user(trig_type
, user_buf
))
1754 local_irq_save(flags
);
1755 if (trig_type
== ALTR_UE_TRIGGER_CHAR
) {
1756 writel(priv
->ue_set_mask
, set_addr
);
1758 /* Setup read/write of 4 bytes */
1759 writel(ECC_WORD_WRITE
, drvdata
->base
+ ECC_BLK_DBYTECTRL_OFST
);
1760 /* Setup Address to 0 */
1761 writel(0, drvdata
->base
+ ECC_BLK_ADDRESS_OFST
);
1762 /* Setup accctrl to read & ecc & data override */
1763 writel(ECC_READ_EDOVR
, drvdata
->base
+ ECC_BLK_ACCCTRL_OFST
);
1765 writel(ECC_XACT_KICK
, drvdata
->base
+ ECC_BLK_STARTACC_OFST
);
1766 /* Setup write for single bit change */
1767 writel(readl(drvdata
->base
+ ECC_BLK_RDATA0_OFST
) ^ 0x1,
1768 drvdata
->base
+ ECC_BLK_WDATA0_OFST
);
1769 writel(readl(drvdata
->base
+ ECC_BLK_RDATA1_OFST
),
1770 drvdata
->base
+ ECC_BLK_WDATA1_OFST
);
1771 writel(readl(drvdata
->base
+ ECC_BLK_RDATA2_OFST
),
1772 drvdata
->base
+ ECC_BLK_WDATA2_OFST
);
1773 writel(readl(drvdata
->base
+ ECC_BLK_RDATA3_OFST
),
1774 drvdata
->base
+ ECC_BLK_WDATA3_OFST
);
1776 /* Copy Read ECC to Write ECC */
1777 writel(readl(drvdata
->base
+ ECC_BLK_RECC0_OFST
),
1778 drvdata
->base
+ ECC_BLK_WECC0_OFST
);
1779 writel(readl(drvdata
->base
+ ECC_BLK_RECC1_OFST
),
1780 drvdata
->base
+ ECC_BLK_WECC1_OFST
);
1781 /* Setup accctrl to write & ecc override & data override */
1782 writel(ECC_WRITE_EDOVR
, drvdata
->base
+ ECC_BLK_ACCCTRL_OFST
);
1784 writel(ECC_XACT_KICK
, drvdata
->base
+ ECC_BLK_STARTACC_OFST
);
1785 /* Setup accctrl to read & ecc overwrite & data overwrite */
1786 writel(ECC_READ_EDOVR
, drvdata
->base
+ ECC_BLK_ACCCTRL_OFST
);
1788 writel(ECC_XACT_KICK
, drvdata
->base
+ ECC_BLK_STARTACC_OFST
);
1791 /* Ensure the interrupt test bits are set */
1793 local_irq_restore(flags
);
1798 static void altr_edac_a10_irq_handler(struct irq_desc
*desc
)
1800 int dberr
, bit
, sm_offset
, irq_status
;
1801 struct altr_arria10_edac
*edac
= irq_desc_get_handler_data(desc
);
1802 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1803 int irq
= irq_desc_get_irq(desc
);
1806 dberr
= (irq
== edac
->db_irq
) ? 1 : 0;
1807 sm_offset
= dberr
? A10_SYSMGR_ECC_INTSTAT_DERR_OFST
:
1808 A10_SYSMGR_ECC_INTSTAT_SERR_OFST
;
1810 chained_irq_enter(chip
, desc
);
1812 regmap_read(edac
->ecc_mgr_map
, sm_offset
, &irq_status
);
1815 for_each_set_bit(bit
, &bits
, 32)
1816 generic_handle_domain_irq(edac
->domain
, dberr
* 32 + bit
);
1818 chained_irq_exit(chip
, desc
);
1821 static int validate_parent_available(struct device_node
*np
)
1823 struct device_node
*parent
;
1826 /* SDRAM must be present for Linux (implied parent) */
1827 if (of_device_is_compatible(np
, "altr,sdram-edac-s10"))
1830 /* Ensure parent device is enabled if parent node exists */
1831 parent
= of_parse_phandle(np
, "altr,ecc-parent", 0);
1832 if (parent
&& !of_device_is_available(parent
))
1835 of_node_put(parent
);
1839 static int get_s10_sdram_edac_resource(struct device_node
*np
,
1840 struct resource
*res
)
1842 struct device_node
*parent
;
1845 parent
= of_parse_phandle(np
, "altr,sdr-syscon", 0);
1849 ret
= of_address_to_resource(parent
, 0, res
);
1850 of_node_put(parent
);
1855 static int altr_edac_a10_device_add(struct altr_arria10_edac
*edac
,
1856 struct device_node
*np
)
1858 struct edac_device_ctl_info
*dci
;
1859 struct altr_edac_device_dev
*altdev
;
1860 char *ecc_name
= (char *)np
->name
;
1861 struct resource res
;
1864 const struct edac_device_prv_data
*prv
;
1865 /* Get matching node and check for valid result */
1866 const struct of_device_id
*pdev_id
=
1867 of_match_node(altr_edac_a10_device_of_match
, np
);
1868 if (IS_ERR_OR_NULL(pdev_id
))
1871 /* Get driver specific data for this EDAC device */
1872 prv
= pdev_id
->data
;
1873 if (IS_ERR_OR_NULL(prv
))
1876 if (validate_parent_available(np
))
1879 if (!devres_open_group(edac
->dev
, altr_edac_a10_device_add
, GFP_KERNEL
))
1882 if (of_device_is_compatible(np
, "altr,sdram-edac-s10"))
1883 rc
= get_s10_sdram_edac_resource(np
, &res
);
1885 rc
= of_address_to_resource(np
, 0, &res
);
1888 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1889 "%s: no resource address\n", ecc_name
);
1890 goto err_release_group
;
1893 edac_idx
= edac_device_alloc_index();
1894 dci
= edac_device_alloc_ctl_info(sizeof(*altdev
), ecc_name
,
1895 1, ecc_name
, 1, 0, NULL
, 0,
1899 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1900 "%s: Unable to allocate EDAC device\n", ecc_name
);
1902 goto err_release_group
;
1905 altdev
= dci
->pvt_info
;
1906 dci
->dev
= edac
->dev
;
1907 altdev
->edac_dev_name
= ecc_name
;
1908 altdev
->edac_idx
= edac_idx
;
1909 altdev
->edac
= edac
;
1910 altdev
->edac_dev
= dci
;
1912 altdev
->ddev
= *edac
->dev
;
1913 dci
->dev
= &altdev
->ddev
;
1914 dci
->ctl_name
= "Altera ECC Manager";
1915 dci
->mod_name
= ecc_name
;
1916 dci
->dev_name
= ecc_name
;
1918 altdev
->base
= devm_ioremap_resource(edac
->dev
, &res
);
1919 if (IS_ERR(altdev
->base
)) {
1920 rc
= PTR_ERR(altdev
->base
);
1921 goto err_release_group1
;
1924 /* Check specific dependencies for the module */
1925 if (altdev
->data
->setup
) {
1926 rc
= altdev
->data
->setup(altdev
);
1928 goto err_release_group1
;
1931 altdev
->sb_irq
= irq_of_parse_and_map(np
, 0);
1932 if (!altdev
->sb_irq
) {
1933 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error allocating SBIRQ\n");
1935 goto err_release_group1
;
1937 rc
= devm_request_irq(edac
->dev
, altdev
->sb_irq
, prv
->ecc_irq_handler
,
1938 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1941 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No SBERR IRQ resource\n");
1942 goto err_release_group1
;
1946 /* Use IRQ to determine SError origin instead of assigning IRQ */
1947 rc
= of_property_read_u32_index(np
, "interrupts", 0, &altdev
->db_irq
);
1949 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1950 "Unable to parse DB IRQ index\n");
1951 goto err_release_group1
;
1954 altdev
->db_irq
= irq_of_parse_and_map(np
, 1);
1955 if (!altdev
->db_irq
) {
1956 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error allocating DBIRQ\n");
1958 goto err_release_group1
;
1960 rc
= devm_request_irq(edac
->dev
, altdev
->db_irq
, prv
->ecc_irq_handler
,
1961 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1964 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No DBERR IRQ resource\n");
1965 goto err_release_group1
;
1969 rc
= edac_device_add_device(dci
);
1971 dev_err(edac
->dev
, "edac_device_add_device failed\n");
1973 goto err_release_group1
;
1976 altr_create_edacdev_dbgfs(dci
, prv
);
1978 list_add(&altdev
->next
, &edac
->a10_ecc_devices
);
1980 devres_remove_group(edac
->dev
, altr_edac_a10_device_add
);
1985 edac_device_free_ctl_info(dci
);
1987 devres_release_group(edac
->dev
, NULL
);
1988 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1989 "%s:Error setting up EDAC device: %d\n", ecc_name
, rc
);
1994 static void a10_eccmgr_irq_mask(struct irq_data
*d
)
1996 struct altr_arria10_edac
*edac
= irq_data_get_irq_chip_data(d
);
1998 regmap_write(edac
->ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_SET_OFST
,
2002 static void a10_eccmgr_irq_unmask(struct irq_data
*d
)
2004 struct altr_arria10_edac
*edac
= irq_data_get_irq_chip_data(d
);
2006 regmap_write(edac
->ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_CLR_OFST
,
2010 static int a10_eccmgr_irqdomain_map(struct irq_domain
*d
, unsigned int irq
,
2011 irq_hw_number_t hwirq
)
2013 struct altr_arria10_edac
*edac
= d
->host_data
;
2015 irq_set_chip_and_handler(irq
, &edac
->irq_chip
, handle_simple_irq
);
2016 irq_set_chip_data(irq
, edac
);
2017 irq_set_noprobe(irq
);
2022 static const struct irq_domain_ops a10_eccmgr_ic_ops
= {
2023 .map
= a10_eccmgr_irqdomain_map
,
2024 .xlate
= irq_domain_xlate_twocell
,
2027 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2028 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2031 /* panic routine issues reboot on non-zero panic_timeout */
2032 extern int panic_timeout
;
2035 * The double bit error is handled through SError which is fatal. This is
2036 * called as a panic notifier to printout ECC error info as part of the panic.
2038 static int s10_edac_dberr_handler(struct notifier_block
*this,
2039 unsigned long event
, void *ptr
)
2041 struct altr_arria10_edac
*edac
= to_a10edac(this, panic_notifier
);
2042 int err_addr
, dberror
;
2044 regmap_read(edac
->ecc_mgr_map
, S10_SYSMGR_ECC_INTSTAT_DERR_OFST
,
2046 regmap_write(edac
->ecc_mgr_map
, S10_SYSMGR_UE_VAL_OFST
, dberror
);
2047 if (dberror
& S10_DBE_IRQ_MASK
) {
2048 struct list_head
*position
;
2049 struct altr_edac_device_dev
*ed
;
2050 struct arm_smccc_res result
;
2052 /* Find the matching DBE in the list of devices */
2053 list_for_each(position
, &edac
->a10_ecc_devices
) {
2054 ed
= list_entry(position
, struct altr_edac_device_dev
,
2056 if (!(BIT(ed
->db_irq
) & dberror
))
2059 writel(ALTR_A10_ECC_DERRPENA
,
2060 ed
->base
+ ALTR_A10_ECC_INTSTAT_OFST
);
2061 err_addr
= readl(ed
->base
+ ALTR_S10_DERR_ADDRA_OFST
);
2062 regmap_write(edac
->ecc_mgr_map
,
2063 S10_SYSMGR_UE_ADDR_OFST
, err_addr
);
2064 edac_printk(KERN_ERR
, EDAC_DEVICE
,
2065 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2066 ed
->edac_dev_name
, err_addr
);
2069 /* Notify the System through SMC. Reboot delay = 1 second */
2071 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE
, dberror
, 0, 0, 0, 0,
2079 /****************** Arria 10 EDAC Probe Function *********************/
2080 static int altr_edac_a10_probe(struct platform_device
*pdev
)
2082 struct altr_arria10_edac
*edac
;
2083 struct device_node
*child
;
2085 edac
= devm_kzalloc(&pdev
->dev
, sizeof(*edac
), GFP_KERNEL
);
2089 edac
->dev
= &pdev
->dev
;
2090 platform_set_drvdata(pdev
, edac
);
2091 INIT_LIST_HEAD(&edac
->a10_ecc_devices
);
2094 altr_sysmgr_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
2095 "altr,sysmgr-syscon");
2097 if (IS_ERR(edac
->ecc_mgr_map
)) {
2098 edac_printk(KERN_ERR
, EDAC_DEVICE
,
2099 "Unable to get syscon altr,sysmgr-syscon\n");
2100 return PTR_ERR(edac
->ecc_mgr_map
);
2103 edac
->irq_chip
.name
= pdev
->dev
.of_node
->name
;
2104 edac
->irq_chip
.irq_mask
= a10_eccmgr_irq_mask
;
2105 edac
->irq_chip
.irq_unmask
= a10_eccmgr_irq_unmask
;
2106 edac
->domain
= irq_domain_add_linear(pdev
->dev
.of_node
, 64,
2107 &a10_eccmgr_ic_ops
, edac
);
2108 if (!edac
->domain
) {
2109 dev_err(&pdev
->dev
, "Error adding IRQ domain\n");
2113 edac
->sb_irq
= platform_get_irq(pdev
, 0);
2114 if (edac
->sb_irq
< 0) {
2115 dev_err(&pdev
->dev
, "No SBERR IRQ resource\n");
2116 return edac
->sb_irq
;
2119 irq_set_chained_handler_and_data(edac
->sb_irq
,
2120 altr_edac_a10_irq_handler
,
2125 int dberror
, err_addr
;
2127 edac
->panic_notifier
.notifier_call
= s10_edac_dberr_handler
;
2128 atomic_notifier_chain_register(&panic_notifier_list
,
2129 &edac
->panic_notifier
);
2131 /* Printout a message if uncorrectable error previously. */
2132 regmap_read(edac
->ecc_mgr_map
, S10_SYSMGR_UE_VAL_OFST
,
2135 regmap_read(edac
->ecc_mgr_map
, S10_SYSMGR_UE_ADDR_OFST
,
2137 edac_printk(KERN_ERR
, EDAC_DEVICE
,
2138 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2140 /* Reset the sticky registers */
2141 regmap_write(edac
->ecc_mgr_map
,
2142 S10_SYSMGR_UE_VAL_OFST
, 0);
2143 regmap_write(edac
->ecc_mgr_map
,
2144 S10_SYSMGR_UE_ADDR_OFST
, 0);
2148 edac
->db_irq
= platform_get_irq(pdev
, 1);
2149 if (edac
->db_irq
< 0) {
2150 dev_err(&pdev
->dev
, "No DBERR IRQ resource\n");
2151 return edac
->db_irq
;
2153 irq_set_chained_handler_and_data(edac
->db_irq
,
2154 altr_edac_a10_irq_handler
, edac
);
2157 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
2158 if (!of_device_is_available(child
))
2161 if (of_match_node(altr_edac_a10_device_of_match
, child
))
2162 altr_edac_a10_device_add(edac
, child
);
2164 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2165 else if (of_device_is_compatible(child
, "altr,sdram-edac-a10"))
2166 of_platform_populate(pdev
->dev
.of_node
,
2167 altr_sdram_ctrl_of_match
,
2175 static const struct of_device_id altr_edac_a10_of_match
[] = {
2176 { .compatible
= "altr,socfpga-a10-ecc-manager" },
2177 { .compatible
= "altr,socfpga-s10-ecc-manager" },
2180 MODULE_DEVICE_TABLE(of
, altr_edac_a10_of_match
);
2182 static struct platform_driver altr_edac_a10_driver
= {
2183 .probe
= altr_edac_a10_probe
,
2185 .name
= "socfpga_a10_ecc_manager",
2186 .of_match_table
= altr_edac_a10_of_match
,
2189 module_platform_driver(altr_edac_a10_driver
);
2191 MODULE_LICENSE("GPL v2");
2192 MODULE_AUTHOR("Thor Thayer");
2193 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");