2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
3 * Copyright 2011-2012 Calxeda, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
17 * Adapted from the highbank_mc_edac driver.
20 #include <asm/cacheflush.h>
21 #include <linux/ctype.h>
22 #include <linux/delay.h>
23 #include <linux/edac.h>
24 #include <linux/genalloc.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/kernel.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/regmap.h>
34 #include <linux/types.h>
35 #include <linux/uaccess.h>
37 #include "altera_edac.h"
38 #include "edac_module.h"
40 #define EDAC_MOD_STR "altera_edac"
41 #define EDAC_VERSION "1"
42 #define EDAC_DEVICE "Altera"
44 static const struct altr_sdram_prv_data c5_data
= {
45 .ecc_ctrl_offset
= CV_CTLCFG_OFST
,
46 .ecc_ctl_en_mask
= CV_CTLCFG_ECC_AUTO_EN
,
47 .ecc_stat_offset
= CV_DRAMSTS_OFST
,
48 .ecc_stat_ce_mask
= CV_DRAMSTS_SBEERR
,
49 .ecc_stat_ue_mask
= CV_DRAMSTS_DBEERR
,
50 .ecc_saddr_offset
= CV_ERRADDR_OFST
,
51 .ecc_daddr_offset
= CV_ERRADDR_OFST
,
52 .ecc_cecnt_offset
= CV_SBECOUNT_OFST
,
53 .ecc_uecnt_offset
= CV_DBECOUNT_OFST
,
54 .ecc_irq_en_offset
= CV_DRAMINTR_OFST
,
55 .ecc_irq_en_mask
= CV_DRAMINTR_INTREN
,
56 .ecc_irq_clr_offset
= CV_DRAMINTR_OFST
,
57 .ecc_irq_clr_mask
= (CV_DRAMINTR_INTRCLR
| CV_DRAMINTR_INTREN
),
58 .ecc_cnt_rst_offset
= CV_DRAMINTR_OFST
,
59 .ecc_cnt_rst_mask
= CV_DRAMINTR_INTRCLR
,
60 .ce_ue_trgr_offset
= CV_CTLCFG_OFST
,
61 .ce_set_mask
= CV_CTLCFG_GEN_SB_ERR
,
62 .ue_set_mask
= CV_CTLCFG_GEN_DB_ERR
,
65 static const struct altr_sdram_prv_data a10_data
= {
66 .ecc_ctrl_offset
= A10_ECCCTRL1_OFST
,
67 .ecc_ctl_en_mask
= A10_ECCCTRL1_ECC_EN
,
68 .ecc_stat_offset
= A10_INTSTAT_OFST
,
69 .ecc_stat_ce_mask
= A10_INTSTAT_SBEERR
,
70 .ecc_stat_ue_mask
= A10_INTSTAT_DBEERR
,
71 .ecc_saddr_offset
= A10_SERRADDR_OFST
,
72 .ecc_daddr_offset
= A10_DERRADDR_OFST
,
73 .ecc_irq_en_offset
= A10_ERRINTEN_OFST
,
74 .ecc_irq_en_mask
= A10_ECC_IRQ_EN_MASK
,
75 .ecc_irq_clr_offset
= A10_INTSTAT_OFST
,
76 .ecc_irq_clr_mask
= (A10_INTSTAT_SBEERR
| A10_INTSTAT_DBEERR
),
77 .ecc_cnt_rst_offset
= A10_ECCCTRL1_OFST
,
78 .ecc_cnt_rst_mask
= A10_ECC_CNT_RESET_MASK
,
79 .ce_ue_trgr_offset
= A10_DIAGINTTEST_OFST
,
80 .ce_set_mask
= A10_DIAGINT_TSERRA_MASK
,
81 .ue_set_mask
= A10_DIAGINT_TDERRA_MASK
,
84 /*********************** EDAC Memory Controller Functions ****************/
86 /* The SDRAM controller uses the EDAC Memory Controller framework. */
88 static irqreturn_t
altr_sdram_mc_err_handler(int irq
, void *dev_id
)
90 struct mem_ctl_info
*mci
= dev_id
;
91 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
92 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
93 u32 status
, err_count
= 1, err_addr
;
95 regmap_read(drvdata
->mc_vbase
, priv
->ecc_stat_offset
, &status
);
97 if (status
& priv
->ecc_stat_ue_mask
) {
98 regmap_read(drvdata
->mc_vbase
, priv
->ecc_daddr_offset
,
100 if (priv
->ecc_uecnt_offset
)
101 regmap_read(drvdata
->mc_vbase
, priv
->ecc_uecnt_offset
,
103 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
104 err_count
, err_addr
);
106 if (status
& priv
->ecc_stat_ce_mask
) {
107 regmap_read(drvdata
->mc_vbase
, priv
->ecc_saddr_offset
,
109 if (priv
->ecc_uecnt_offset
)
110 regmap_read(drvdata
->mc_vbase
, priv
->ecc_cecnt_offset
,
112 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, err_count
,
113 err_addr
>> PAGE_SHIFT
,
114 err_addr
& ~PAGE_MASK
, 0,
115 0, 0, -1, mci
->ctl_name
, "");
116 /* Clear IRQ to resume */
117 regmap_write(drvdata
->mc_vbase
, priv
->ecc_irq_clr_offset
,
118 priv
->ecc_irq_clr_mask
);
125 static ssize_t
altr_sdr_mc_err_inject_write(struct file
*file
,
126 const char __user
*data
,
127 size_t count
, loff_t
*ppos
)
129 struct mem_ctl_info
*mci
= file
->private_data
;
130 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
131 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
133 dma_addr_t dma_handle
;
136 ptemp
= dma_alloc_coherent(mci
->pdev
, 16, &dma_handle
, GFP_KERNEL
);
138 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
139 edac_printk(KERN_ERR
, EDAC_MC
,
140 "Inject: Buffer Allocation error\n");
144 regmap_read(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
146 read_reg
&= ~(priv
->ce_set_mask
| priv
->ue_set_mask
);
148 /* Error are injected by writing a word while the SBE or DBE
149 * bit in the CTLCFG register is set. Reading the word will
150 * trigger the SBE or DBE error and the corresponding IRQ.
153 edac_printk(KERN_ALERT
, EDAC_MC
,
154 "Inject Double bit error\n");
156 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
157 (read_reg
| priv
->ue_set_mask
));
160 edac_printk(KERN_ALERT
, EDAC_MC
,
161 "Inject Single bit error\n");
163 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
164 (read_reg
| priv
->ce_set_mask
));
168 ptemp
[0] = 0x5A5A5A5A;
169 ptemp
[1] = 0xA5A5A5A5;
171 /* Clear the error injection bits */
172 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
, read_reg
);
173 /* Ensure it has been written out */
177 * To trigger the error, we need to read the data back
178 * (the data was written with errors above).
179 * The ACCESS_ONCE macros and printk are used to prevent the
180 * the compiler optimizing these reads out.
182 reg
= ACCESS_ONCE(ptemp
[0]);
183 read_reg
= ACCESS_ONCE(ptemp
[1]);
187 edac_printk(KERN_ALERT
, EDAC_MC
, "Read Data [0x%X, 0x%X]\n",
190 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
195 static const struct file_operations altr_sdr_mc_debug_inject_fops
= {
197 .write
= altr_sdr_mc_err_inject_write
,
198 .llseek
= generic_file_llseek
,
201 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info
*mci
)
203 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
209 edac_debugfs_create_file("altr_trigger", S_IWUSR
, mci
->debugfs
, mci
,
210 &altr_sdr_mc_debug_inject_fops
);
213 /* Get total memory size from Open Firmware DTB */
214 static unsigned long get_total_mem(void)
216 struct device_node
*np
= NULL
;
219 unsigned long total_mem
= 0;
221 for_each_node_by_type(np
, "memory") {
222 ret
= of_address_to_resource(np
, 0, &res
);
226 total_mem
+= resource_size(&res
);
228 edac_dbg(0, "total_mem 0x%lx\n", total_mem
);
232 static const struct of_device_id altr_sdram_ctrl_of_match
[] = {
233 { .compatible
= "altr,sdram-edac", .data
= &c5_data
},
234 { .compatible
= "altr,sdram-edac-a10", .data
= &a10_data
},
237 MODULE_DEVICE_TABLE(of
, altr_sdram_ctrl_of_match
);
239 static int a10_init(struct regmap
*mc_vbase
)
241 if (regmap_update_bits(mc_vbase
, A10_INTMODE_OFST
,
242 A10_INTMODE_SB_INT
, A10_INTMODE_SB_INT
)) {
243 edac_printk(KERN_ERR
, EDAC_MC
,
244 "Error setting SB IRQ mode\n");
248 if (regmap_write(mc_vbase
, A10_SERRCNTREG_OFST
, 1)) {
249 edac_printk(KERN_ERR
, EDAC_MC
,
250 "Error setting trigger count\n");
257 static int a10_unmask_irq(struct platform_device
*pdev
, u32 mask
)
259 void __iomem
*sm_base
;
262 if (!request_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
),
263 dev_name(&pdev
->dev
))) {
264 edac_printk(KERN_ERR
, EDAC_MC
,
265 "Unable to request mem region\n");
269 sm_base
= ioremap(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
271 edac_printk(KERN_ERR
, EDAC_MC
,
272 "Unable to ioremap device\n");
278 iowrite32(mask
, sm_base
);
283 release_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
288 static int altr_sdram_probe(struct platform_device
*pdev
)
290 const struct of_device_id
*id
;
291 struct edac_mc_layer layers
[2];
292 struct mem_ctl_info
*mci
;
293 struct altr_sdram_mc_data
*drvdata
;
294 const struct altr_sdram_prv_data
*priv
;
295 struct regmap
*mc_vbase
;
296 struct dimm_info
*dimm
;
298 int irq
, irq2
, res
= 0;
299 unsigned long mem_size
, irqflags
= 0;
301 id
= of_match_device(altr_sdram_ctrl_of_match
, &pdev
->dev
);
305 /* Grab the register range from the sdr controller in device tree */
306 mc_vbase
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
308 if (IS_ERR(mc_vbase
)) {
309 edac_printk(KERN_ERR
, EDAC_MC
,
310 "regmap for altr,sdr-syscon lookup failed.\n");
314 /* Check specific dependencies for the module */
315 priv
= of_match_node(altr_sdram_ctrl_of_match
,
316 pdev
->dev
.of_node
)->data
;
318 /* Validate the SDRAM controller has ECC enabled */
319 if (regmap_read(mc_vbase
, priv
->ecc_ctrl_offset
, &read_reg
) ||
320 ((read_reg
& priv
->ecc_ctl_en_mask
) != priv
->ecc_ctl_en_mask
)) {
321 edac_printk(KERN_ERR
, EDAC_MC
,
322 "No ECC/ECC disabled [0x%08X]\n", read_reg
);
326 /* Grab memory size from device tree. */
327 mem_size
= get_total_mem();
329 edac_printk(KERN_ERR
, EDAC_MC
, "Unable to calculate memory size\n");
333 /* Ensure the SDRAM Interrupt is disabled */
334 if (regmap_update_bits(mc_vbase
, priv
->ecc_irq_en_offset
,
335 priv
->ecc_irq_en_mask
, 0)) {
336 edac_printk(KERN_ERR
, EDAC_MC
,
337 "Error disabling SDRAM ECC IRQ\n");
341 /* Toggle to clear the SDRAM Error count */
342 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
343 priv
->ecc_cnt_rst_mask
,
344 priv
->ecc_cnt_rst_mask
)) {
345 edac_printk(KERN_ERR
, EDAC_MC
,
346 "Error clearing SDRAM ECC count\n");
350 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
351 priv
->ecc_cnt_rst_mask
, 0)) {
352 edac_printk(KERN_ERR
, EDAC_MC
,
353 "Error clearing SDRAM ECC count\n");
357 irq
= platform_get_irq(pdev
, 0);
359 edac_printk(KERN_ERR
, EDAC_MC
,
360 "No irq %d in DT\n", irq
);
364 /* Arria10 has a 2nd IRQ */
365 irq2
= platform_get_irq(pdev
, 1);
367 layers
[0].type
= EDAC_MC_LAYER_CHIP_SELECT
;
369 layers
[0].is_virt_csrow
= true;
370 layers
[1].type
= EDAC_MC_LAYER_CHANNEL
;
372 layers
[1].is_virt_csrow
= false;
373 mci
= edac_mc_alloc(0, ARRAY_SIZE(layers
), layers
,
374 sizeof(struct altr_sdram_mc_data
));
378 mci
->pdev
= &pdev
->dev
;
379 drvdata
= mci
->pvt_info
;
380 drvdata
->mc_vbase
= mc_vbase
;
381 drvdata
->data
= priv
;
382 platform_set_drvdata(pdev
, mci
);
384 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
385 edac_printk(KERN_ERR
, EDAC_MC
,
386 "Unable to get managed device resource\n");
391 mci
->mtype_cap
= MEM_FLAG_DDR3
;
392 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
393 mci
->edac_cap
= EDAC_FLAG_SECDED
;
394 mci
->mod_name
= EDAC_MOD_STR
;
395 mci
->mod_ver
= EDAC_VERSION
;
396 mci
->ctl_name
= dev_name(&pdev
->dev
);
397 mci
->scrub_mode
= SCRUB_SW_SRC
;
398 mci
->dev_name
= dev_name(&pdev
->dev
);
401 dimm
->nr_pages
= ((mem_size
- 1) >> PAGE_SHIFT
) + 1;
403 dimm
->dtype
= DEV_X8
;
404 dimm
->mtype
= MEM_DDR3
;
405 dimm
->edac_mode
= EDAC_SECDED
;
407 res
= edac_mc_add_mc(mci
);
411 /* Only the Arria10 has separate IRQs */
413 /* Arria10 specific initialization */
414 res
= a10_init(mc_vbase
);
418 res
= devm_request_irq(&pdev
->dev
, irq2
,
419 altr_sdram_mc_err_handler
,
420 IRQF_SHARED
, dev_name(&pdev
->dev
), mci
);
422 edac_mc_printk(mci
, KERN_ERR
,
423 "Unable to request irq %d\n", irq2
);
428 res
= a10_unmask_irq(pdev
, A10_DDR0_IRQ_MASK
);
432 irqflags
= IRQF_SHARED
;
435 res
= devm_request_irq(&pdev
->dev
, irq
, altr_sdram_mc_err_handler
,
436 irqflags
, dev_name(&pdev
->dev
), mci
);
438 edac_mc_printk(mci
, KERN_ERR
,
439 "Unable to request irq %d\n", irq
);
444 /* Infrastructure ready - enable the IRQ */
445 if (regmap_update_bits(drvdata
->mc_vbase
, priv
->ecc_irq_en_offset
,
446 priv
->ecc_irq_en_mask
, priv
->ecc_irq_en_mask
)) {
447 edac_mc_printk(mci
, KERN_ERR
,
448 "Error enabling SDRAM ECC IRQ\n");
453 altr_sdr_mc_create_debugfs_nodes(mci
);
455 devres_close_group(&pdev
->dev
, NULL
);
460 edac_mc_del_mc(&pdev
->dev
);
462 devres_release_group(&pdev
->dev
, NULL
);
465 edac_printk(KERN_ERR
, EDAC_MC
,
466 "EDAC Probe Failed; Error %d\n", res
);
471 static int altr_sdram_remove(struct platform_device
*pdev
)
473 struct mem_ctl_info
*mci
= platform_get_drvdata(pdev
);
475 edac_mc_del_mc(&pdev
->dev
);
477 platform_set_drvdata(pdev
, NULL
);
483 * If you want to suspend, need to disable EDAC by removing it
484 * from the device tree or defconfig.
487 static int altr_sdram_prepare(struct device
*dev
)
489 pr_err("Suspend not allowed when EDAC is enabled.\n");
494 static const struct dev_pm_ops altr_sdram_pm_ops
= {
495 .prepare
= altr_sdram_prepare
,
499 static struct platform_driver altr_sdram_edac_driver
= {
500 .probe
= altr_sdram_probe
,
501 .remove
= altr_sdram_remove
,
503 .name
= "altr_sdram_edac",
505 .pm
= &altr_sdram_pm_ops
,
507 .of_match_table
= altr_sdram_ctrl_of_match
,
511 module_platform_driver(altr_sdram_edac_driver
);
513 /************************* EDAC Parent Probe *************************/
515 static const struct of_device_id altr_edac_device_of_match
[];
517 static const struct of_device_id altr_edac_of_match
[] = {
518 { .compatible
= "altr,socfpga-ecc-manager" },
521 MODULE_DEVICE_TABLE(of
, altr_edac_of_match
);
523 static int altr_edac_probe(struct platform_device
*pdev
)
525 of_platform_populate(pdev
->dev
.of_node
, altr_edac_device_of_match
,
530 static struct platform_driver altr_edac_driver
= {
531 .probe
= altr_edac_probe
,
533 .name
= "socfpga_ecc_manager",
534 .of_match_table
= altr_edac_of_match
,
537 module_platform_driver(altr_edac_driver
);
539 /************************* EDAC Device Functions *************************/
542 * EDAC Device Functions (shared between various IPs).
543 * The discrete memories use the EDAC Device framework. The probe
544 * and error handling functions are very similar between memories
545 * so they are shared. The memory allocation and freeing for EDAC
546 * trigger testing are different for each memory.
549 static const struct edac_device_prv_data ocramecc_data
;
550 static const struct edac_device_prv_data l2ecc_data
;
551 static const struct edac_device_prv_data a10_ocramecc_data
;
552 static const struct edac_device_prv_data a10_l2ecc_data
;
554 static irqreturn_t
altr_edac_device_handler(int irq
, void *dev_id
)
556 irqreturn_t ret_value
= IRQ_NONE
;
557 struct edac_device_ctl_info
*dci
= dev_id
;
558 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
559 const struct edac_device_prv_data
*priv
= drvdata
->data
;
561 if (irq
== drvdata
->sb_irq
) {
562 if (priv
->ce_clear_mask
)
563 writel(priv
->ce_clear_mask
, drvdata
->base
);
564 edac_device_handle_ce(dci
, 0, 0, drvdata
->edac_dev_name
);
565 ret_value
= IRQ_HANDLED
;
566 } else if (irq
== drvdata
->db_irq
) {
567 if (priv
->ue_clear_mask
)
568 writel(priv
->ue_clear_mask
, drvdata
->base
);
569 edac_device_handle_ue(dci
, 0, 0, drvdata
->edac_dev_name
);
570 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
571 ret_value
= IRQ_HANDLED
;
579 static ssize_t
altr_edac_device_trig(struct file
*file
,
580 const char __user
*user_buf
,
581 size_t count
, loff_t
*ppos
)
584 u32
*ptemp
, i
, error_mask
;
588 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
589 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
590 const struct edac_device_prv_data
*priv
= drvdata
->data
;
591 void *generic_ptr
= edac_dci
->dev
;
593 if (!user_buf
|| get_user(trig_type
, user_buf
))
596 if (!priv
->alloc_mem
)
600 * Note that generic_ptr is initialized to the device * but in
601 * some alloc_functions, this is overridden and returns data.
603 ptemp
= priv
->alloc_mem(priv
->trig_alloc_sz
, &generic_ptr
);
605 edac_printk(KERN_ERR
, EDAC_DEVICE
,
606 "Inject: Buffer Allocation error\n");
610 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
611 error_mask
= priv
->ue_set_mask
;
613 error_mask
= priv
->ce_set_mask
;
615 edac_printk(KERN_ALERT
, EDAC_DEVICE
,
616 "Trigger Error Mask (0x%X)\n", error_mask
);
618 local_irq_save(flags
);
619 /* write ECC corrupted data out. */
620 for (i
= 0; i
< (priv
->trig_alloc_sz
/ sizeof(*ptemp
)); i
++) {
621 /* Read data so we're in the correct state */
623 if (ACCESS_ONCE(ptemp
[i
]))
625 /* Toggle Error bit (it is latched), leave ECC enabled */
626 writel(error_mask
, (drvdata
->base
+ priv
->set_err_ofst
));
627 writel(priv
->ecc_enable_mask
, (drvdata
->base
+
628 priv
->set_err_ofst
));
631 /* Ensure it has been written out */
633 local_irq_restore(flags
);
636 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Mem Not Cleared\n");
638 /* Read out written data. ECC error caused here */
639 for (i
= 0; i
< ALTR_TRIGGER_READ_WRD_CNT
; i
++)
640 if (ACCESS_ONCE(ptemp
[i
]) != i
)
641 edac_printk(KERN_ERR
, EDAC_DEVICE
,
642 "Read doesn't match written data\n");
645 priv
->free_mem(ptemp
, priv
->trig_alloc_sz
, generic_ptr
);
650 static const struct file_operations altr_edac_device_inject_fops
= {
652 .write
= altr_edac_device_trig
,
653 .llseek
= generic_file_llseek
,
656 static ssize_t
altr_edac_a10_device_trig(struct file
*file
,
657 const char __user
*user_buf
,
658 size_t count
, loff_t
*ppos
);
660 static const struct file_operations altr_edac_a10_device_inject_fops
= {
662 .write
= altr_edac_a10_device_trig
,
663 .llseek
= generic_file_llseek
,
666 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info
*edac_dci
,
667 const struct edac_device_prv_data
*priv
)
669 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
671 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
674 drvdata
->debugfs_dir
= edac_debugfs_create_dir(drvdata
->edac_dev_name
);
675 if (!drvdata
->debugfs_dir
)
678 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR
,
679 drvdata
->debugfs_dir
, edac_dci
,
681 debugfs_remove_recursive(drvdata
->debugfs_dir
);
684 static const struct of_device_id altr_edac_device_of_match
[] = {
685 #ifdef CONFIG_EDAC_ALTERA_L2C
686 { .compatible
= "altr,socfpga-l2-ecc", .data
= &l2ecc_data
},
688 #ifdef CONFIG_EDAC_ALTERA_OCRAM
689 { .compatible
= "altr,socfpga-ocram-ecc", .data
= &ocramecc_data
},
693 MODULE_DEVICE_TABLE(of
, altr_edac_device_of_match
);
696 * altr_edac_device_probe()
697 * This is a generic EDAC device driver that will support
698 * various Altera memory devices such as the L2 cache ECC and
699 * OCRAM ECC as well as the memories for other peripherals.
700 * Module specific initialization is done by passing the
701 * function index in the device tree.
703 static int altr_edac_device_probe(struct platform_device
*pdev
)
705 struct edac_device_ctl_info
*dci
;
706 struct altr_edac_device_dev
*drvdata
;
709 struct device_node
*np
= pdev
->dev
.of_node
;
710 char *ecc_name
= (char *)np
->name
;
711 static int dev_instance
;
713 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
714 edac_printk(KERN_ERR
, EDAC_DEVICE
,
715 "Unable to open devm\n");
719 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
721 edac_printk(KERN_ERR
, EDAC_DEVICE
,
722 "Unable to get mem resource\n");
727 if (!devm_request_mem_region(&pdev
->dev
, r
->start
, resource_size(r
),
728 dev_name(&pdev
->dev
))) {
729 edac_printk(KERN_ERR
, EDAC_DEVICE
,
730 "%s:Error requesting mem region\n", ecc_name
);
735 dci
= edac_device_alloc_ctl_info(sizeof(*drvdata
), ecc_name
,
736 1, ecc_name
, 1, 0, NULL
, 0,
740 edac_printk(KERN_ERR
, EDAC_DEVICE
,
741 "%s: Unable to allocate EDAC device\n", ecc_name
);
746 drvdata
= dci
->pvt_info
;
747 dci
->dev
= &pdev
->dev
;
748 platform_set_drvdata(pdev
, dci
);
749 drvdata
->edac_dev_name
= ecc_name
;
751 drvdata
->base
= devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
755 /* Get driver specific data for this EDAC device */
756 drvdata
->data
= of_match_node(altr_edac_device_of_match
, np
)->data
;
758 /* Check specific dependencies for the module */
759 if (drvdata
->data
->setup
) {
760 res
= drvdata
->data
->setup(drvdata
);
765 drvdata
->sb_irq
= platform_get_irq(pdev
, 0);
766 res
= devm_request_irq(&pdev
->dev
, drvdata
->sb_irq
,
767 altr_edac_device_handler
,
768 0, dev_name(&pdev
->dev
), dci
);
772 drvdata
->db_irq
= platform_get_irq(pdev
, 1);
773 res
= devm_request_irq(&pdev
->dev
, drvdata
->db_irq
,
774 altr_edac_device_handler
,
775 0, dev_name(&pdev
->dev
), dci
);
779 dci
->mod_name
= "Altera ECC Manager";
780 dci
->dev_name
= drvdata
->edac_dev_name
;
782 res
= edac_device_add_device(dci
);
786 altr_create_edacdev_dbgfs(dci
, drvdata
->data
);
788 devres_close_group(&pdev
->dev
, NULL
);
793 edac_device_free_ctl_info(dci
);
795 devres_release_group(&pdev
->dev
, NULL
);
796 edac_printk(KERN_ERR
, EDAC_DEVICE
,
797 "%s:Error setting up EDAC device: %d\n", ecc_name
, res
);
802 static int altr_edac_device_remove(struct platform_device
*pdev
)
804 struct edac_device_ctl_info
*dci
= platform_get_drvdata(pdev
);
805 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
807 debugfs_remove_recursive(drvdata
->debugfs_dir
);
808 edac_device_del_device(&pdev
->dev
);
809 edac_device_free_ctl_info(dci
);
814 static struct platform_driver altr_edac_device_driver
= {
815 .probe
= altr_edac_device_probe
,
816 .remove
= altr_edac_device_remove
,
818 .name
= "altr_edac_device",
819 .of_match_table
= altr_edac_device_of_match
,
822 module_platform_driver(altr_edac_device_driver
);
824 /******************* Arria10 Device ECC Shared Functions *****************/
827 * Test for memory's ECC dependencies upon entry because platform specific
828 * startup should have initialized the memory and enabled the ECC.
829 * Can't turn on ECC here because accessing un-initialized memory will
830 * cause CE/UE errors possibly causing an ABORT.
832 static int __maybe_unused
833 altr_check_ecc_deps(struct altr_edac_device_dev
*device
)
835 void __iomem
*base
= device
->base
;
836 const struct edac_device_prv_data
*prv
= device
->data
;
838 if (readl(base
+ prv
->ecc_en_ofst
) & prv
->ecc_enable_mask
)
841 edac_printk(KERN_ERR
, EDAC_DEVICE
,
842 "%s: No ECC present or ECC disabled.\n",
843 device
->edac_dev_name
);
847 static irqreturn_t __maybe_unused
altr_edac_a10_ecc_irq(int irq
, void *dev_id
)
849 struct altr_edac_device_dev
*dci
= dev_id
;
850 void __iomem
*base
= dci
->base
;
852 if (irq
== dci
->sb_irq
) {
853 writel(ALTR_A10_ECC_SERRPENA
,
854 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
855 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
858 } else if (irq
== dci
->db_irq
) {
859 writel(ALTR_A10_ECC_DERRPENA
,
860 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
861 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
862 if (dci
->data
->panic
)
863 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
873 /******************* Arria10 Memory Buffer Functions *********************/
875 static inline int a10_get_irq_mask(struct device_node
*np
)
878 const u32
*handle
= of_get_property(np
, "interrupts", NULL
);
882 irq
= be32_to_cpup(handle
);
886 static inline void ecc_set_bits(u32 bit_mask
, void __iomem
*ioaddr
)
888 u32 value
= readl(ioaddr
);
891 writel(value
, ioaddr
);
894 static inline void ecc_clear_bits(u32 bit_mask
, void __iomem
*ioaddr
)
896 u32 value
= readl(ioaddr
);
899 writel(value
, ioaddr
);
902 static inline int ecc_test_bits(u32 bit_mask
, void __iomem
*ioaddr
)
904 u32 value
= readl(ioaddr
);
906 return (value
& bit_mask
) ? 1 : 0;
910 * This function uses the memory initialization block in the Arria10 ECC
911 * controller to initialize/clear the entire memory data and ECC data.
913 static int __maybe_unused
altr_init_memory_port(void __iomem
*ioaddr
, int port
)
915 int limit
= ALTR_A10_ECC_INIT_WATCHDOG_10US
;
916 u32 init_mask
, stat_mask
, clear_mask
;
920 init_mask
= ALTR_A10_ECC_INITB
;
921 stat_mask
= ALTR_A10_ECC_INITCOMPLETEB
;
922 clear_mask
= ALTR_A10_ECC_ERRPENB_MASK
;
924 init_mask
= ALTR_A10_ECC_INITA
;
925 stat_mask
= ALTR_A10_ECC_INITCOMPLETEA
;
926 clear_mask
= ALTR_A10_ECC_ERRPENA_MASK
;
929 ecc_set_bits(init_mask
, (ioaddr
+ ALTR_A10_ECC_CTRL_OFST
));
931 if (ecc_test_bits(stat_mask
,
932 (ioaddr
+ ALTR_A10_ECC_INITSTAT_OFST
)))
939 /* Clear any pending ECC interrupts */
940 writel(clear_mask
, (ioaddr
+ ALTR_A10_ECC_INTSTAT_OFST
));
945 static __init
int __maybe_unused
946 altr_init_a10_ecc_block(struct device_node
*np
, u32 irq_mask
,
947 u32 ecc_ctrl_en_mask
, bool dual_port
)
950 void __iomem
*ecc_block_base
;
951 struct regmap
*ecc_mgr_map
;
953 struct device_node
*np_eccmgr
;
955 ecc_name
= (char *)np
->name
;
957 /* Get the ECC Manager - parent of the device EDACs */
958 np_eccmgr
= of_get_parent(np
);
959 ecc_mgr_map
= syscon_regmap_lookup_by_phandle(np_eccmgr
,
960 "altr,sysmgr-syscon");
961 of_node_put(np_eccmgr
);
962 if (IS_ERR(ecc_mgr_map
)) {
963 edac_printk(KERN_ERR
, EDAC_DEVICE
,
964 "Unable to get syscon altr,sysmgr-syscon\n");
968 /* Map the ECC Block */
969 ecc_block_base
= of_iomap(np
, 0);
970 if (!ecc_block_base
) {
971 edac_printk(KERN_ERR
, EDAC_DEVICE
,
972 "Unable to map %s ECC block\n", ecc_name
);
977 regmap_write(ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_SET_OFST
, irq_mask
);
978 writel(ALTR_A10_ECC_SERRINTEN
,
979 (ecc_block_base
+ ALTR_A10_ECC_ERRINTENR_OFST
));
980 ecc_clear_bits(ecc_ctrl_en_mask
,
981 (ecc_block_base
+ ALTR_A10_ECC_CTRL_OFST
));
982 /* Ensure all writes complete */
984 /* Use HW initialization block to initialize memory for ECC */
985 ret
= altr_init_memory_port(ecc_block_base
, 0);
987 edac_printk(KERN_ERR
, EDAC_DEVICE
,
988 "ECC: cannot init %s PORTA memory\n", ecc_name
);
993 ret
= altr_init_memory_port(ecc_block_base
, 1);
995 edac_printk(KERN_ERR
, EDAC_DEVICE
,
996 "ECC: cannot init %s PORTB memory\n",
1002 /* Interrupt mode set to every SBERR */
1003 regmap_write(ecc_mgr_map
, ALTR_A10_ECC_INTMODE_OFST
,
1004 ALTR_A10_ECC_INTMODE
);
1006 ecc_set_bits(ecc_ctrl_en_mask
, (ecc_block_base
+
1007 ALTR_A10_ECC_CTRL_OFST
));
1008 writel(ALTR_A10_ECC_SERRINTEN
,
1009 (ecc_block_base
+ ALTR_A10_ECC_ERRINTENS_OFST
));
1010 regmap_write(ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_CLR_OFST
, irq_mask
);
1011 /* Ensure all writes complete */
1014 iounmap(ecc_block_base
);
1018 static int socfpga_is_a10(void)
1020 return of_machine_is_compatible("altr,socfpga-arria10");
1023 static int validate_parent_available(struct device_node
*np
);
1024 static const struct of_device_id altr_edac_a10_device_of_match
[];
1025 static int __init __maybe_unused
altr_init_a10_ecc_device_type(char *compat
)
1028 struct device_node
*child
, *np
;
1030 if (!socfpga_is_a10())
1033 np
= of_find_compatible_node(NULL
, NULL
,
1034 "altr,socfpga-a10-ecc-manager");
1036 edac_printk(KERN_ERR
, EDAC_DEVICE
, "ECC Manager not found\n");
1040 for_each_child_of_node(np
, child
) {
1041 const struct of_device_id
*pdev_id
;
1042 const struct edac_device_prv_data
*prv
;
1044 if (!of_device_is_available(child
))
1046 if (!of_device_is_compatible(child
, compat
))
1049 if (validate_parent_available(child
))
1052 irq
= a10_get_irq_mask(child
);
1056 /* Get matching node and check for valid result */
1057 pdev_id
= of_match_node(altr_edac_a10_device_of_match
, child
);
1058 if (IS_ERR_OR_NULL(pdev_id
))
1061 /* Validate private data pointer before dereferencing */
1062 prv
= pdev_id
->data
;
1066 altr_init_a10_ecc_block(child
, BIT(irq
),
1067 prv
->ecc_enable_mask
, 0);
1074 /*********************** OCRAM EDAC Device Functions *********************/
1076 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1078 static void *ocram_alloc_mem(size_t size
, void **other
)
1080 struct device_node
*np
;
1081 struct gen_pool
*gp
;
1084 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-ocram-ecc");
1088 gp
= of_gen_pool_get(np
, "iram", 0);
1093 sram_addr
= (void *)gen_pool_alloc(gp
, size
);
1097 memset(sram_addr
, 0, size
);
1098 /* Ensure data is written out */
1101 /* Remember this handle for freeing later */
1107 static void ocram_free_mem(void *p
, size_t size
, void *other
)
1109 gen_pool_free((struct gen_pool
*)other
, (u32
)p
, size
);
1112 static const struct edac_device_prv_data ocramecc_data
= {
1113 .setup
= altr_check_ecc_deps
,
1114 .ce_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_SERR
),
1115 .ue_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_DERR
),
1116 .alloc_mem
= ocram_alloc_mem
,
1117 .free_mem
= ocram_free_mem
,
1118 .ecc_enable_mask
= ALTR_OCR_ECC_EN
,
1119 .ecc_en_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
1120 .ce_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJS
),
1121 .ue_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJD
),
1122 .set_err_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
1123 .trig_alloc_sz
= ALTR_TRIG_OCRAM_BYTE_SIZE
,
1124 .inject_fops
= &altr_edac_device_inject_fops
,
1127 static const struct edac_device_prv_data a10_ocramecc_data
= {
1128 .setup
= altr_check_ecc_deps
,
1129 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1130 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1131 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_OCRAM
,
1132 .ecc_enable_mask
= ALTR_A10_OCRAM_ECC_EN_CTL
,
1133 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1134 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1135 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1136 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1137 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1138 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1140 * OCRAM panic on uncorrectable error because sleep/resume
1141 * functions and FPGA contents are stored in OCRAM. Prefer
1142 * a kernel panic over executing/loading corrupted data.
1147 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1149 /********************* L2 Cache EDAC Device Functions ********************/
1151 #ifdef CONFIG_EDAC_ALTERA_L2C
1153 static void *l2_alloc_mem(size_t size
, void **other
)
1155 struct device
*dev
= *other
;
1156 void *ptemp
= devm_kzalloc(dev
, size
, GFP_KERNEL
);
1161 /* Make sure everything is written out */
1165 * Clean all cache levels up to LoC (includes L2)
1166 * This ensures the corrupted data is written into
1167 * L2 cache for readback test (which causes ECC error).
1174 static void l2_free_mem(void *p
, size_t size
, void *other
)
1176 struct device
*dev
= other
;
1183 * altr_l2_check_deps()
1184 * Test for L2 cache ECC dependencies upon entry because
1185 * platform specific startup should have initialized the L2
1186 * memory and enabled the ECC.
1187 * Bail if ECC is not enabled.
1188 * Note that L2 Cache Enable is forced at build time.
1190 static int altr_l2_check_deps(struct altr_edac_device_dev
*device
)
1192 void __iomem
*base
= device
->base
;
1193 const struct edac_device_prv_data
*prv
= device
->data
;
1195 if ((readl(base
) & prv
->ecc_enable_mask
) ==
1196 prv
->ecc_enable_mask
)
1199 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1200 "L2: No ECC present, or ECC disabled\n");
1204 static irqreturn_t
altr_edac_a10_l2_irq(int irq
, void *dev_id
)
1206 struct altr_edac_device_dev
*dci
= dev_id
;
1208 if (irq
== dci
->sb_irq
) {
1209 regmap_write(dci
->edac
->ecc_mgr_map
,
1210 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
1211 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB
);
1212 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
1215 } else if (irq
== dci
->db_irq
) {
1216 regmap_write(dci
->edac
->ecc_mgr_map
,
1217 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
1218 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB
);
1219 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
1220 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1230 static const struct edac_device_prv_data l2ecc_data
= {
1231 .setup
= altr_l2_check_deps
,
1234 .alloc_mem
= l2_alloc_mem
,
1235 .free_mem
= l2_free_mem
,
1236 .ecc_enable_mask
= ALTR_L2_ECC_EN
,
1237 .ce_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJS
),
1238 .ue_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJD
),
1239 .set_err_ofst
= ALTR_L2_ECC_REG_OFFSET
,
1240 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
1241 .inject_fops
= &altr_edac_device_inject_fops
,
1244 static const struct edac_device_prv_data a10_l2ecc_data
= {
1245 .setup
= altr_l2_check_deps
,
1246 .ce_clear_mask
= ALTR_A10_L2_ECC_SERR_CLR
,
1247 .ue_clear_mask
= ALTR_A10_L2_ECC_MERR_CLR
,
1248 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_L2
,
1249 .alloc_mem
= l2_alloc_mem
,
1250 .free_mem
= l2_free_mem
,
1251 .ecc_enable_mask
= ALTR_A10_L2_ECC_EN_CTL
,
1252 .ce_set_mask
= ALTR_A10_L2_ECC_CE_INJ_MASK
,
1253 .ue_set_mask
= ALTR_A10_L2_ECC_UE_INJ_MASK
,
1254 .set_err_ofst
= ALTR_A10_L2_ECC_INJ_OFST
,
1255 .ecc_irq_handler
= altr_edac_a10_l2_irq
,
1256 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
1257 .inject_fops
= &altr_edac_device_inject_fops
,
1260 #endif /* CONFIG_EDAC_ALTERA_L2C */
1262 /********************* Ethernet Device Functions ********************/
1264 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1266 static const struct edac_device_prv_data a10_enetecc_data
= {
1267 .setup
= altr_check_ecc_deps
,
1268 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1269 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1270 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1271 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1272 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1273 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1274 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1275 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1276 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1279 static int __init
socfpga_init_ethernet_ecc(void)
1281 return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1284 early_initcall(socfpga_init_ethernet_ecc
);
1286 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1288 /********************** NAND Device Functions **********************/
1290 #ifdef CONFIG_EDAC_ALTERA_NAND
1292 static const struct edac_device_prv_data a10_nandecc_data
= {
1293 .setup
= altr_check_ecc_deps
,
1294 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1295 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1296 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1297 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1298 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1299 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1300 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1301 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1302 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1305 static int __init
socfpga_init_nand_ecc(void)
1307 return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1310 early_initcall(socfpga_init_nand_ecc
);
1312 #endif /* CONFIG_EDAC_ALTERA_NAND */
1314 /********************** DMA Device Functions **********************/
1316 #ifdef CONFIG_EDAC_ALTERA_DMA
1318 static const struct edac_device_prv_data a10_dmaecc_data
= {
1319 .setup
= altr_check_ecc_deps
,
1320 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1321 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1322 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1323 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1324 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1325 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1326 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1327 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1328 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1331 static int __init
socfpga_init_dma_ecc(void)
1333 return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1336 early_initcall(socfpga_init_dma_ecc
);
1338 #endif /* CONFIG_EDAC_ALTERA_DMA */
1340 /********************** USB Device Functions **********************/
1342 #ifdef CONFIG_EDAC_ALTERA_USB
1344 static const struct edac_device_prv_data a10_usbecc_data
= {
1345 .setup
= altr_check_ecc_deps
,
1346 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1347 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1348 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1349 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1350 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1351 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1352 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1353 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1354 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1357 static int __init
socfpga_init_usb_ecc(void)
1359 return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1362 early_initcall(socfpga_init_usb_ecc
);
1364 #endif /* CONFIG_EDAC_ALTERA_USB */
1366 /********************** QSPI Device Functions **********************/
1368 #ifdef CONFIG_EDAC_ALTERA_QSPI
1370 static const struct edac_device_prv_data a10_qspiecc_data
= {
1371 .setup
= altr_check_ecc_deps
,
1372 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1373 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1374 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1375 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1376 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1377 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1378 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1379 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1380 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1383 static int __init
socfpga_init_qspi_ecc(void)
1385 return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1388 early_initcall(socfpga_init_qspi_ecc
);
1390 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1392 /********************* SDMMC Device Functions **********************/
1394 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1396 static const struct edac_device_prv_data a10_sdmmceccb_data
;
1397 static int altr_portb_setup(struct altr_edac_device_dev
*device
)
1399 struct edac_device_ctl_info
*dci
;
1400 struct altr_edac_device_dev
*altdev
;
1401 char *ecc_name
= "sdmmcb-ecc";
1403 struct device_node
*np
;
1404 const struct edac_device_prv_data
*prv
= &a10_sdmmceccb_data
;
1406 rc
= altr_check_ecc_deps(device
);
1410 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-sdmmc-ecc");
1412 edac_printk(KERN_WARNING
, EDAC_DEVICE
, "SDMMC node not found\n");
1416 /* Create the PortB EDAC device */
1417 edac_idx
= edac_device_alloc_index();
1418 dci
= edac_device_alloc_ctl_info(sizeof(*altdev
), ecc_name
, 1,
1419 ecc_name
, 1, 0, NULL
, 0, edac_idx
);
1421 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1422 "%s: Unable to allocate PortB EDAC device\n",
1427 /* Initialize the PortB EDAC device structure from PortA structure */
1428 altdev
= dci
->pvt_info
;
1431 if (!devres_open_group(&altdev
->ddev
, altr_portb_setup
, GFP_KERNEL
))
1434 /* Update PortB specific values */
1435 altdev
->edac_dev_name
= ecc_name
;
1436 altdev
->edac_idx
= edac_idx
;
1437 altdev
->edac_dev
= dci
;
1439 dci
->dev
= &altdev
->ddev
;
1440 dci
->ctl_name
= "Altera ECC Manager";
1441 dci
->mod_name
= ecc_name
;
1442 dci
->dev_name
= ecc_name
;
1444 /* Update the IRQs for PortB */
1445 altdev
->sb_irq
= irq_of_parse_and_map(np
, 2);
1446 if (!altdev
->sb_irq
) {
1447 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error PortB SBIRQ alloc\n");
1449 goto err_release_group_1
;
1451 rc
= devm_request_irq(&altdev
->ddev
, altdev
->sb_irq
,
1452 prv
->ecc_irq_handler
,
1453 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1456 edac_printk(KERN_ERR
, EDAC_DEVICE
, "PortB SBERR IRQ error\n");
1457 goto err_release_group_1
;
1460 altdev
->db_irq
= irq_of_parse_and_map(np
, 3);
1461 if (!altdev
->db_irq
) {
1462 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error PortB DBIRQ alloc\n");
1464 goto err_release_group_1
;
1466 rc
= devm_request_irq(&altdev
->ddev
, altdev
->db_irq
,
1467 prv
->ecc_irq_handler
,
1468 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1471 edac_printk(KERN_ERR
, EDAC_DEVICE
, "PortB DBERR IRQ error\n");
1472 goto err_release_group_1
;
1475 rc
= edac_device_add_device(dci
);
1477 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1478 "edac_device_add_device portB failed\n");
1480 goto err_release_group_1
;
1482 altr_create_edacdev_dbgfs(dci
, prv
);
1484 list_add(&altdev
->next
, &altdev
->edac
->a10_ecc_devices
);
1486 devres_remove_group(&altdev
->ddev
, altr_portb_setup
);
1490 err_release_group_1
:
1491 edac_device_free_ctl_info(dci
);
1492 devres_release_group(&altdev
->ddev
, altr_portb_setup
);
1493 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1494 "%s:Error setting up EDAC device: %d\n", ecc_name
, rc
);
1498 static irqreturn_t
altr_edac_a10_ecc_irq_portb(int irq
, void *dev_id
)
1500 struct altr_edac_device_dev
*ad
= dev_id
;
1501 void __iomem
*base
= ad
->base
;
1502 const struct edac_device_prv_data
*priv
= ad
->data
;
1504 if (irq
== ad
->sb_irq
) {
1505 writel(priv
->ce_clear_mask
,
1506 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
1507 edac_device_handle_ce(ad
->edac_dev
, 0, 0, ad
->edac_dev_name
);
1509 } else if (irq
== ad
->db_irq
) {
1510 writel(priv
->ue_clear_mask
,
1511 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
1512 edac_device_handle_ue(ad
->edac_dev
, 0, 0, ad
->edac_dev_name
);
1516 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq
);
1521 static const struct edac_device_prv_data a10_sdmmcecca_data
= {
1522 .setup
= altr_portb_setup
,
1523 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1524 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1525 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1526 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1527 .ce_set_mask
= ALTR_A10_ECC_SERRPENA
,
1528 .ue_set_mask
= ALTR_A10_ECC_DERRPENA
,
1529 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1530 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1531 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1534 static const struct edac_device_prv_data a10_sdmmceccb_data
= {
1535 .setup
= altr_portb_setup
,
1536 .ce_clear_mask
= ALTR_A10_ECC_SERRPENB
,
1537 .ue_clear_mask
= ALTR_A10_ECC_DERRPENB
,
1538 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1539 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1540 .ce_set_mask
= ALTR_A10_ECC_TSERRB
,
1541 .ue_set_mask
= ALTR_A10_ECC_TDERRB
,
1542 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1543 .ecc_irq_handler
= altr_edac_a10_ecc_irq_portb
,
1544 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1547 static int __init
socfpga_init_sdmmc_ecc(void)
1550 struct device_node
*child
;
1552 if (!socfpga_is_a10())
1555 child
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-sdmmc-ecc");
1557 edac_printk(KERN_WARNING
, EDAC_DEVICE
, "SDMMC node not found\n");
1561 if (!of_device_is_available(child
))
1564 if (validate_parent_available(child
))
1567 rc
= altr_init_a10_ecc_block(child
, ALTR_A10_SDMMC_IRQ_MASK
,
1568 a10_sdmmcecca_data
.ecc_enable_mask
, 1);
1574 early_initcall(socfpga_init_sdmmc_ecc
);
1576 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1578 /********************* Arria10 EDAC Device Functions *************************/
1579 static const struct of_device_id altr_edac_a10_device_of_match
[] = {
1580 #ifdef CONFIG_EDAC_ALTERA_L2C
1581 { .compatible
= "altr,socfpga-a10-l2-ecc", .data
= &a10_l2ecc_data
},
1583 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1584 { .compatible
= "altr,socfpga-a10-ocram-ecc",
1585 .data
= &a10_ocramecc_data
},
1587 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1588 { .compatible
= "altr,socfpga-eth-mac-ecc",
1589 .data
= &a10_enetecc_data
},
1591 #ifdef CONFIG_EDAC_ALTERA_NAND
1592 { .compatible
= "altr,socfpga-nand-ecc", .data
= &a10_nandecc_data
},
1594 #ifdef CONFIG_EDAC_ALTERA_DMA
1595 { .compatible
= "altr,socfpga-dma-ecc", .data
= &a10_dmaecc_data
},
1597 #ifdef CONFIG_EDAC_ALTERA_USB
1598 { .compatible
= "altr,socfpga-usb-ecc", .data
= &a10_usbecc_data
},
1600 #ifdef CONFIG_EDAC_ALTERA_QSPI
1601 { .compatible
= "altr,socfpga-qspi-ecc", .data
= &a10_qspiecc_data
},
1603 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1604 { .compatible
= "altr,socfpga-sdmmc-ecc", .data
= &a10_sdmmcecca_data
},
1608 MODULE_DEVICE_TABLE(of
, altr_edac_a10_device_of_match
);
1611 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1612 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1613 * manager manages the IRQs and the children.
1614 * Based on xgene_edac.c peripheral code.
1617 static ssize_t
altr_edac_a10_device_trig(struct file
*file
,
1618 const char __user
*user_buf
,
1619 size_t count
, loff_t
*ppos
)
1621 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
1622 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
1623 const struct edac_device_prv_data
*priv
= drvdata
->data
;
1624 void __iomem
*set_addr
= (drvdata
->base
+ priv
->set_err_ofst
);
1625 unsigned long flags
;
1628 if (!user_buf
|| get_user(trig_type
, user_buf
))
1631 local_irq_save(flags
);
1632 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
1633 writel(priv
->ue_set_mask
, set_addr
);
1635 writel(priv
->ce_set_mask
, set_addr
);
1636 /* Ensure the interrupt test bits are set */
1638 local_irq_restore(flags
);
1643 static void altr_edac_a10_irq_handler(struct irq_desc
*desc
)
1645 int dberr
, bit
, sm_offset
, irq_status
;
1646 struct altr_arria10_edac
*edac
= irq_desc_get_handler_data(desc
);
1647 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1648 int irq
= irq_desc_get_irq(desc
);
1650 dberr
= (irq
== edac
->db_irq
) ? 1 : 0;
1651 sm_offset
= dberr
? A10_SYSMGR_ECC_INTSTAT_DERR_OFST
:
1652 A10_SYSMGR_ECC_INTSTAT_SERR_OFST
;
1654 chained_irq_enter(chip
, desc
);
1656 regmap_read(edac
->ecc_mgr_map
, sm_offset
, &irq_status
);
1658 for_each_set_bit(bit
, (unsigned long *)&irq_status
, 32) {
1659 irq
= irq_linear_revmap(edac
->domain
, dberr
* 32 + bit
);
1661 generic_handle_irq(irq
);
1664 chained_irq_exit(chip
, desc
);
1667 static int validate_parent_available(struct device_node
*np
)
1669 struct device_node
*parent
;
1672 /* Ensure parent device is enabled if parent node exists */
1673 parent
= of_parse_phandle(np
, "altr,ecc-parent", 0);
1674 if (parent
&& !of_device_is_available(parent
))
1677 of_node_put(parent
);
1681 static int altr_edac_a10_device_add(struct altr_arria10_edac
*edac
,
1682 struct device_node
*np
)
1684 struct edac_device_ctl_info
*dci
;
1685 struct altr_edac_device_dev
*altdev
;
1686 char *ecc_name
= (char *)np
->name
;
1687 struct resource res
;
1690 const struct edac_device_prv_data
*prv
;
1691 /* Get matching node and check for valid result */
1692 const struct of_device_id
*pdev_id
=
1693 of_match_node(altr_edac_a10_device_of_match
, np
);
1694 if (IS_ERR_OR_NULL(pdev_id
))
1697 /* Get driver specific data for this EDAC device */
1698 prv
= pdev_id
->data
;
1699 if (IS_ERR_OR_NULL(prv
))
1702 if (validate_parent_available(np
))
1705 if (!devres_open_group(edac
->dev
, altr_edac_a10_device_add
, GFP_KERNEL
))
1708 rc
= of_address_to_resource(np
, 0, &res
);
1710 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1711 "%s: no resource address\n", ecc_name
);
1712 goto err_release_group
;
1715 edac_idx
= edac_device_alloc_index();
1716 dci
= edac_device_alloc_ctl_info(sizeof(*altdev
), ecc_name
,
1717 1, ecc_name
, 1, 0, NULL
, 0,
1721 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1722 "%s: Unable to allocate EDAC device\n", ecc_name
);
1724 goto err_release_group
;
1727 altdev
= dci
->pvt_info
;
1728 dci
->dev
= edac
->dev
;
1729 altdev
->edac_dev_name
= ecc_name
;
1730 altdev
->edac_idx
= edac_idx
;
1731 altdev
->edac
= edac
;
1732 altdev
->edac_dev
= dci
;
1734 altdev
->ddev
= *edac
->dev
;
1735 dci
->dev
= &altdev
->ddev
;
1736 dci
->ctl_name
= "Altera ECC Manager";
1737 dci
->mod_name
= ecc_name
;
1738 dci
->dev_name
= ecc_name
;
1740 altdev
->base
= devm_ioremap_resource(edac
->dev
, &res
);
1741 if (IS_ERR(altdev
->base
)) {
1742 rc
= PTR_ERR(altdev
->base
);
1743 goto err_release_group1
;
1746 /* Check specific dependencies for the module */
1747 if (altdev
->data
->setup
) {
1748 rc
= altdev
->data
->setup(altdev
);
1750 goto err_release_group1
;
1753 altdev
->sb_irq
= irq_of_parse_and_map(np
, 0);
1754 if (!altdev
->sb_irq
) {
1755 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error allocating SBIRQ\n");
1757 goto err_release_group1
;
1759 rc
= devm_request_irq(edac
->dev
, altdev
->sb_irq
, prv
->ecc_irq_handler
,
1760 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1763 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No SBERR IRQ resource\n");
1764 goto err_release_group1
;
1767 altdev
->db_irq
= irq_of_parse_and_map(np
, 1);
1768 if (!altdev
->db_irq
) {
1769 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error allocating DBIRQ\n");
1771 goto err_release_group1
;
1773 rc
= devm_request_irq(edac
->dev
, altdev
->db_irq
, prv
->ecc_irq_handler
,
1774 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1777 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No DBERR IRQ resource\n");
1778 goto err_release_group1
;
1781 rc
= edac_device_add_device(dci
);
1783 dev_err(edac
->dev
, "edac_device_add_device failed\n");
1785 goto err_release_group1
;
1788 altr_create_edacdev_dbgfs(dci
, prv
);
1790 list_add(&altdev
->next
, &edac
->a10_ecc_devices
);
1792 devres_remove_group(edac
->dev
, altr_edac_a10_device_add
);
1797 edac_device_free_ctl_info(dci
);
1799 devres_release_group(edac
->dev
, NULL
);
1800 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1801 "%s:Error setting up EDAC device: %d\n", ecc_name
, rc
);
1806 static void a10_eccmgr_irq_mask(struct irq_data
*d
)
1808 struct altr_arria10_edac
*edac
= irq_data_get_irq_chip_data(d
);
1810 regmap_write(edac
->ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_SET_OFST
,
1814 static void a10_eccmgr_irq_unmask(struct irq_data
*d
)
1816 struct altr_arria10_edac
*edac
= irq_data_get_irq_chip_data(d
);
1818 regmap_write(edac
->ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_CLR_OFST
,
1822 static int a10_eccmgr_irqdomain_map(struct irq_domain
*d
, unsigned int irq
,
1823 irq_hw_number_t hwirq
)
1825 struct altr_arria10_edac
*edac
= d
->host_data
;
1827 irq_set_chip_and_handler(irq
, &edac
->irq_chip
, handle_simple_irq
);
1828 irq_set_chip_data(irq
, edac
);
1829 irq_set_noprobe(irq
);
1834 static const struct irq_domain_ops a10_eccmgr_ic_ops
= {
1835 .map
= a10_eccmgr_irqdomain_map
,
1836 .xlate
= irq_domain_xlate_twocell
,
1839 static int altr_edac_a10_probe(struct platform_device
*pdev
)
1841 struct altr_arria10_edac
*edac
;
1842 struct device_node
*child
;
1844 edac
= devm_kzalloc(&pdev
->dev
, sizeof(*edac
), GFP_KERNEL
);
1848 edac
->dev
= &pdev
->dev
;
1849 platform_set_drvdata(pdev
, edac
);
1850 INIT_LIST_HEAD(&edac
->a10_ecc_devices
);
1852 edac
->ecc_mgr_map
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
1853 "altr,sysmgr-syscon");
1854 if (IS_ERR(edac
->ecc_mgr_map
)) {
1855 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1856 "Unable to get syscon altr,sysmgr-syscon\n");
1857 return PTR_ERR(edac
->ecc_mgr_map
);
1860 edac
->irq_chip
.name
= pdev
->dev
.of_node
->name
;
1861 edac
->irq_chip
.irq_mask
= a10_eccmgr_irq_mask
;
1862 edac
->irq_chip
.irq_unmask
= a10_eccmgr_irq_unmask
;
1863 edac
->domain
= irq_domain_add_linear(pdev
->dev
.of_node
, 64,
1864 &a10_eccmgr_ic_ops
, edac
);
1865 if (!edac
->domain
) {
1866 dev_err(&pdev
->dev
, "Error adding IRQ domain\n");
1870 edac
->sb_irq
= platform_get_irq(pdev
, 0);
1871 if (edac
->sb_irq
< 0) {
1872 dev_err(&pdev
->dev
, "No SBERR IRQ resource\n");
1873 return edac
->sb_irq
;
1876 irq_set_chained_handler_and_data(edac
->sb_irq
,
1877 altr_edac_a10_irq_handler
,
1880 edac
->db_irq
= platform_get_irq(pdev
, 1);
1881 if (edac
->db_irq
< 0) {
1882 dev_err(&pdev
->dev
, "No DBERR IRQ resource\n");
1883 return edac
->db_irq
;
1885 irq_set_chained_handler_and_data(edac
->db_irq
,
1886 altr_edac_a10_irq_handler
,
1889 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
1890 if (!of_device_is_available(child
))
1893 if (of_device_is_compatible(child
, "altr,socfpga-a10-l2-ecc") ||
1894 of_device_is_compatible(child
, "altr,socfpga-a10-ocram-ecc") ||
1895 of_device_is_compatible(child
, "altr,socfpga-eth-mac-ecc") ||
1896 of_device_is_compatible(child
, "altr,socfpga-nand-ecc") ||
1897 of_device_is_compatible(child
, "altr,socfpga-dma-ecc") ||
1898 of_device_is_compatible(child
, "altr,socfpga-usb-ecc") ||
1899 of_device_is_compatible(child
, "altr,socfpga-qspi-ecc") ||
1900 of_device_is_compatible(child
, "altr,socfpga-sdmmc-ecc"))
1902 altr_edac_a10_device_add(edac
, child
);
1904 else if (of_device_is_compatible(child
, "altr,sdram-edac-a10"))
1905 of_platform_populate(pdev
->dev
.of_node
,
1906 altr_sdram_ctrl_of_match
,
1913 static const struct of_device_id altr_edac_a10_of_match
[] = {
1914 { .compatible
= "altr,socfpga-a10-ecc-manager" },
1917 MODULE_DEVICE_TABLE(of
, altr_edac_a10_of_match
);
1919 static struct platform_driver altr_edac_a10_driver
= {
1920 .probe
= altr_edac_a10_probe
,
1922 .name
= "socfpga_a10_ecc_manager",
1923 .of_match_table
= altr_edac_a10_of_match
,
1926 module_platform_driver(altr_edac_a10_driver
);
1928 MODULE_LICENSE("GPL v2");
1929 MODULE_AUTHOR("Thor Thayer");
1930 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");