2 * Intel e7xxx Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * See "enum e7xxx_chips" below for supported chipsets
9 * Written by Thayne Harbaugh
10 * Based on work by Dan Hollis <goemon at anime dot net> and others.
11 * http://www.anime.net/~goemon/linux-ecc/
14 * Eric Biederman (Linux Networx)
15 * Tom Zimmerman (Linux Networx)
16 * Jim Garlick (Lawrence Livermore National Labs)
17 * Dave Peterson (Lawrence Livermore National Labs)
18 * That One Guy (Some other place)
19 * Wang Zhenyu (intel.com)
21 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
26 #include <linux/config.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/pci_ids.h>
31 #include <linux/slab.h>
35 #define e7xxx_printk(level, fmt, arg...) \
36 edac_printk(level, "e7xxx", fmt, ##arg)
39 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
40 edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
43 #ifndef PCI_DEVICE_ID_INTEL_7205_0
44 #define PCI_DEVICE_ID_INTEL_7205_0 0x255d
45 #endif /* PCI_DEVICE_ID_INTEL_7205_0 */
47 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
48 #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
49 #endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
51 #ifndef PCI_DEVICE_ID_INTEL_7500_0
52 #define PCI_DEVICE_ID_INTEL_7500_0 0x2540
53 #endif /* PCI_DEVICE_ID_INTEL_7500_0 */
55 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
56 #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
57 #endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
59 #ifndef PCI_DEVICE_ID_INTEL_7501_0
60 #define PCI_DEVICE_ID_INTEL_7501_0 0x254c
61 #endif /* PCI_DEVICE_ID_INTEL_7501_0 */
63 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
64 #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
65 #endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
67 #ifndef PCI_DEVICE_ID_INTEL_7505_0
68 #define PCI_DEVICE_ID_INTEL_7505_0 0x2550
69 #endif /* PCI_DEVICE_ID_INTEL_7505_0 */
71 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
72 #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
73 #endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
76 #define E7XXX_NR_CSROWS 8 /* number of csrows */
77 #define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */
80 /* E7XXX register addresses - device 0 function 0 */
81 #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
82 #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
84 * 31 Device width row 7 0=x8 1=x4
85 * 27 Device width row 6
86 * 23 Device width row 5
87 * 19 Device width row 4
88 * 15 Device width row 3
89 * 11 Device width row 2
90 * 7 Device width row 1
91 * 3 Device width row 0
93 #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
95 * 22 Number channels 0=1,1=2
96 * 19:18 DRB Granularity 32/64MB
98 #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
99 #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
100 #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
102 /* E7XXX register addresses - device 0 function 1 */
103 #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
104 #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
105 #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
106 /* error address register (32b) */
109 * 27:6 CE address (4k block 33:12)
112 #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
113 /* error address register (32b) */
116 * 27:6 CE address (4k block 33:12)
119 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
120 /* error syndrome register (16b) */
131 struct pci_dev
*bridge_ck
;
135 const struct e7xxx_dev_info
*dev_info
;
139 struct e7xxx_dev_info
{
141 const char *ctl_name
;
145 struct e7xxx_error_info
{
149 u16 dram_celog_syndrome
;
153 static const struct e7xxx_dev_info e7xxx_devs
[] = {
155 .err_dev
= PCI_DEVICE_ID_INTEL_7500_1_ERR
,
156 .ctl_name
= "E7500"},
158 .err_dev
= PCI_DEVICE_ID_INTEL_7501_1_ERR
,
159 .ctl_name
= "E7501"},
161 .err_dev
= PCI_DEVICE_ID_INTEL_7505_1_ERR
,
162 .ctl_name
= "E7505"},
164 .err_dev
= PCI_DEVICE_ID_INTEL_7205_1_ERR
,
165 .ctl_name
= "E7205"},
169 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
170 static inline int e7xxx_find_channel(u16 syndrome
)
172 debugf3("%s()\n", __func__
);
174 if ((syndrome
& 0xff00) == 0)
176 if ((syndrome
& 0x00ff) == 0)
178 if ((syndrome
& 0xf000) == 0 || (syndrome
& 0x0f00) == 0)
185 ctl_page_to_phys(struct mem_ctl_info
*mci
, unsigned long page
)
188 struct e7xxx_pvt
*pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
190 debugf3("%s()\n", __func__
);
192 if ((page
< pvt
->tolm
) ||
193 ((page
>= 0x100000) && (page
< pvt
->remapbase
)))
195 remap
= (page
- pvt
->tolm
) + pvt
->remapbase
;
196 if (remap
< pvt
->remaplimit
)
198 e7xxx_printk(KERN_ERR
, "Invalid page %lx - out of range\n", page
);
199 return pvt
->tolm
- 1;
203 static void process_ce(struct mem_ctl_info
*mci
, struct e7xxx_error_info
*info
)
210 debugf3("%s()\n", __func__
);
212 /* read the error address */
213 error_1b
= info
->dram_celog_add
;
214 /* FIXME - should use PAGE_SHIFT */
215 page
= error_1b
>> 6; /* convert the address to 4k page */
216 /* read the syndrome */
217 syndrome
= info
->dram_celog_syndrome
;
218 /* FIXME - check for -1 */
219 row
= edac_mc_find_csrow_by_page(mci
, page
);
220 /* convert syndrome to channel */
221 channel
= e7xxx_find_channel(syndrome
);
222 edac_mc_handle_ce(mci
, page
, 0, syndrome
, row
, channel
,
227 static void process_ce_no_info(struct mem_ctl_info
*mci
)
229 debugf3("%s()\n", __func__
);
230 edac_mc_handle_ce_no_info(mci
, "e7xxx CE log register overflow");
234 static void process_ue(struct mem_ctl_info
*mci
, struct e7xxx_error_info
*info
)
236 u32 error_2b
, block_page
;
239 debugf3("%s()\n", __func__
);
241 /* read the error address */
242 error_2b
= info
->dram_uelog_add
;
243 /* FIXME - should use PAGE_SHIFT */
244 block_page
= error_2b
>> 6; /* convert to 4k address */
245 row
= edac_mc_find_csrow_by_page(mci
, block_page
);
246 edac_mc_handle_ue(mci
, block_page
, 0, row
, "e7xxx UE");
250 static void process_ue_no_info(struct mem_ctl_info
*mci
)
252 debugf3("%s()\n", __func__
);
253 edac_mc_handle_ue_no_info(mci
, "e7xxx UE log register overflow");
257 static void e7xxx_get_error_info (struct mem_ctl_info
*mci
,
258 struct e7xxx_error_info
*info
)
260 struct e7xxx_pvt
*pvt
;
262 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
263 pci_read_config_byte(pvt
->bridge_ck
, E7XXX_DRAM_FERR
,
265 pci_read_config_byte(pvt
->bridge_ck
, E7XXX_DRAM_NERR
,
268 if ((info
->dram_ferr
& 1) || (info
->dram_nerr
& 1)) {
269 pci_read_config_dword(pvt
->bridge_ck
, E7XXX_DRAM_CELOG_ADD
,
270 &info
->dram_celog_add
);
271 pci_read_config_word(pvt
->bridge_ck
,
272 E7XXX_DRAM_CELOG_SYNDROME
, &info
->dram_celog_syndrome
);
275 if ((info
->dram_ferr
& 2) || (info
->dram_nerr
& 2))
276 pci_read_config_dword(pvt
->bridge_ck
, E7XXX_DRAM_UELOG_ADD
,
277 &info
->dram_uelog_add
);
279 if (info
->dram_ferr
& 3)
280 pci_write_bits8(pvt
->bridge_ck
, E7XXX_DRAM_FERR
, 0x03,
283 if (info
->dram_nerr
& 3)
284 pci_write_bits8(pvt
->bridge_ck
, E7XXX_DRAM_NERR
, 0x03,
289 static int e7xxx_process_error_info (struct mem_ctl_info
*mci
,
290 struct e7xxx_error_info
*info
, int handle_errors
)
296 /* decode and report errors */
297 if (info
->dram_ferr
& 1) { /* check first error correctable */
301 process_ce(mci
, info
);
304 if (info
->dram_ferr
& 2) { /* check first error uncorrectable */
308 process_ue(mci
, info
);
311 if (info
->dram_nerr
& 1) { /* check next error correctable */
315 if (info
->dram_ferr
& 1)
316 process_ce_no_info(mci
);
318 process_ce(mci
, info
);
322 if (info
->dram_nerr
& 2) { /* check next error uncorrectable */
326 if (info
->dram_ferr
& 2)
327 process_ue_no_info(mci
);
329 process_ue(mci
, info
);
337 static void e7xxx_check(struct mem_ctl_info
*mci
)
339 struct e7xxx_error_info info
;
341 debugf3("%s()\n", __func__
);
342 e7xxx_get_error_info(mci
, &info
);
343 e7xxx_process_error_info(mci
, &info
, 1);
347 static int e7xxx_probe1(struct pci_dev
*pdev
, int dev_idx
)
352 struct mem_ctl_info
*mci
= NULL
;
353 struct e7xxx_pvt
*pvt
= NULL
;
355 int drc_chan
= 1; /* Number of channels 0=1chan,1=2chan */
356 int drc_drbg
= 1; /* DRB granularity 0=32mb,1=64mb */
357 int drc_ddim
; /* DRAM Data Integrity Mode 0=none,2=edac */
359 unsigned long last_cumul_size
;
362 debugf0("%s(): mci\n", __func__
);
364 /* need to find out the number of channels */
365 pci_read_config_dword(pdev
, E7XXX_DRC
, &drc
);
366 /* only e7501 can be single channel */
367 if (dev_idx
== E7501
) {
368 drc_chan
= ((drc
>> 22) & 0x1);
369 drc_drbg
= (drc
>> 18) & 0x3;
371 drc_ddim
= (drc
>> 20) & 0x3;
373 mci
= edac_mc_alloc(sizeof(*pvt
), E7XXX_NR_CSROWS
, drc_chan
+ 1);
380 debugf3("%s(): init mci\n", __func__
);
382 mci
->mtype_cap
= MEM_FLAG_RDDR
;
384 EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
| EDAC_FLAG_S4ECD4ED
;
385 /* FIXME - what if different memory types are in different csrows? */
386 mci
->mod_name
= BS_MOD_STR
;
387 mci
->mod_ver
= "$Revision: 1.5.2.9 $";
390 debugf3("%s(): init pvt\n", __func__
);
391 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
392 pvt
->dev_info
= &e7xxx_devs
[dev_idx
];
393 pvt
->bridge_ck
= pci_get_device(PCI_VENDOR_ID_INTEL
,
394 pvt
->dev_info
->err_dev
,
396 if (!pvt
->bridge_ck
) {
397 e7xxx_printk(KERN_ERR
, "error reporting device not found:"
398 "vendor %x device 0x%x (broken BIOS?)\n",
400 e7xxx_devs
[dev_idx
].err_dev
);
404 debugf3("%s(): more mci init\n", __func__
);
405 mci
->ctl_name
= pvt
->dev_info
->ctl_name
;
407 mci
->edac_check
= e7xxx_check
;
408 mci
->ctl_page_to_phys
= ctl_page_to_phys
;
410 /* find out the device types */
411 pci_read_config_dword(pdev
, E7XXX_DRA
, &dra
);
414 * The dram row boundary (DRB) reg values are boundary address
415 * for each DRAM row with a granularity of 32 or 64MB (single/dual
416 * channel operation). DRB regs are cumulative; therefore DRB7 will
417 * contain the total memory contained in all eight rows.
419 for (last_cumul_size
= index
= 0; index
< mci
->nr_csrows
; index
++) {
422 /* mem_dev 0=x8, 1=x4 */
423 int mem_dev
= (dra
>> (index
* 4 + 3)) & 0x1;
424 struct csrow_info
*csrow
= &mci
->csrows
[index
];
426 pci_read_config_byte(mci
->pdev
, E7XXX_DRB
+ index
, &value
);
427 /* convert a 64 or 32 MiB DRB to a page size. */
428 cumul_size
= value
<< (25 + drc_drbg
- PAGE_SHIFT
);
429 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__
, index
,
431 if (cumul_size
== last_cumul_size
)
432 continue; /* not populated */
434 csrow
->first_page
= last_cumul_size
;
435 csrow
->last_page
= cumul_size
- 1;
436 csrow
->nr_pages
= cumul_size
- last_cumul_size
;
437 last_cumul_size
= cumul_size
;
438 csrow
->grain
= 1 << 12; /* 4KiB - resolution of CELOG */
439 csrow
->mtype
= MEM_RDDR
; /* only one type supported */
440 csrow
->dtype
= mem_dev
? DEV_X4
: DEV_X8
;
443 * if single channel or x8 devices then SECDED
444 * if dual channel and x4 then S4ECD4ED
447 if (drc_chan
&& mem_dev
) {
448 csrow
->edac_mode
= EDAC_S4ECD4ED
;
449 mci
->edac_cap
|= EDAC_FLAG_S4ECD4ED
;
451 csrow
->edac_mode
= EDAC_SECDED
;
452 mci
->edac_cap
|= EDAC_FLAG_SECDED
;
455 csrow
->edac_mode
= EDAC_NONE
;
458 mci
->edac_cap
|= EDAC_FLAG_NONE
;
460 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__
);
461 /* load the top of low memory, remap base, and remap limit vars */
462 pci_read_config_word(mci
->pdev
, E7XXX_TOLM
, &pci_data
);
463 pvt
->tolm
= ((u32
) pci_data
) << 4;
464 pci_read_config_word(mci
->pdev
, E7XXX_REMAPBASE
, &pci_data
);
465 pvt
->remapbase
= ((u32
) pci_data
) << 14;
466 pci_read_config_word(mci
->pdev
, E7XXX_REMAPLIMIT
, &pci_data
);
467 pvt
->remaplimit
= ((u32
) pci_data
) << 14;
468 e7xxx_printk(KERN_INFO
,
469 "tolm = %x, remapbase = %x, remaplimit = %x\n",
470 pvt
->tolm
, pvt
->remapbase
, pvt
->remaplimit
);
472 /* clear any pending errors, or initial state bits */
473 pci_write_bits8(pvt
->bridge_ck
, E7XXX_DRAM_FERR
, 0x03, 0x03);
474 pci_write_bits8(pvt
->bridge_ck
, E7XXX_DRAM_NERR
, 0x03, 0x03);
476 if (edac_mc_add_mc(mci
) != 0) {
477 debugf3("%s(): failed edac_mc_add_mc()\n", __func__
);
481 /* get this far and it's successful */
482 debugf3("%s(): success\n", __func__
);
487 if(pvt
!= NULL
&& pvt
->bridge_ck
)
488 pci_dev_put(pvt
->bridge_ck
);
495 /* returns count (>= 0), or negative on error */
497 e7xxx_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
499 debugf0("%s()\n", __func__
);
501 /* wake up and enable device */
502 return pci_enable_device(pdev
) ?
503 -EIO
: e7xxx_probe1(pdev
, ent
->driver_data
);
507 static void __devexit
e7xxx_remove_one(struct pci_dev
*pdev
)
509 struct mem_ctl_info
*mci
;
510 struct e7xxx_pvt
*pvt
;
512 debugf0("%s()\n", __func__
);
514 if (((mci
= edac_mc_find_mci_by_pdev(pdev
)) != 0) &&
515 edac_mc_del_mc(mci
)) {
516 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
517 pci_dev_put(pvt
->bridge_ck
);
523 static const struct pci_device_id e7xxx_pci_tbl
[] __devinitdata
= {
524 {PCI_VEND_DEV(INTEL
, 7205_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
526 {PCI_VEND_DEV(INTEL
, 7500_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
528 {PCI_VEND_DEV(INTEL
, 7501_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
530 {PCI_VEND_DEV(INTEL
, 7505_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
532 {0,} /* 0 terminated list. */
535 MODULE_DEVICE_TABLE(pci
, e7xxx_pci_tbl
);
538 static struct pci_driver e7xxx_driver
= {
540 .probe
= e7xxx_init_one
,
541 .remove
= __devexit_p(e7xxx_remove_one
),
542 .id_table
= e7xxx_pci_tbl
,
546 static int __init
e7xxx_init(void)
548 return pci_register_driver(&e7xxx_driver
);
552 static void __exit
e7xxx_exit(void)
554 pci_unregister_driver(&e7xxx_driver
);
557 module_init(e7xxx_init
);
558 module_exit(e7xxx_exit
);
561 MODULE_LICENSE("GPL");
562 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
563 "Based on.work by Dan Hollis et al");
564 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");