2 * Intel e7xxx Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * See "enum e7xxx_chips" below for supported chipsets
9 * Written by Thayne Harbaugh
10 * Based on work by Dan Hollis <goemon at anime dot net> and others.
11 * http://www.anime.net/~goemon/linux-ecc/
14 * Eric Biederman (Linux Networx)
15 * Tom Zimmerman (Linux Networx)
16 * Jim Garlick (Lawrence Livermore National Labs)
17 * Dave Peterson (Lawrence Livermore National Labs)
18 * That One Guy (Some other place)
19 * Wang Zhenyu (intel.com)
21 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/pci_ids.h>
29 #include <linux/slab.h>
32 #define e7xxx_printk(level, fmt, arg...) \
33 edac_printk(level, "e7xxx", fmt, ##arg)
35 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
36 edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
38 #ifndef PCI_DEVICE_ID_INTEL_7205_0
39 #define PCI_DEVICE_ID_INTEL_7205_0 0x255d
40 #endif /* PCI_DEVICE_ID_INTEL_7205_0 */
42 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
43 #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
44 #endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
46 #ifndef PCI_DEVICE_ID_INTEL_7500_0
47 #define PCI_DEVICE_ID_INTEL_7500_0 0x2540
48 #endif /* PCI_DEVICE_ID_INTEL_7500_0 */
50 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
51 #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
52 #endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
54 #ifndef PCI_DEVICE_ID_INTEL_7501_0
55 #define PCI_DEVICE_ID_INTEL_7501_0 0x254c
56 #endif /* PCI_DEVICE_ID_INTEL_7501_0 */
58 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
59 #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
60 #endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
62 #ifndef PCI_DEVICE_ID_INTEL_7505_0
63 #define PCI_DEVICE_ID_INTEL_7505_0 0x2550
64 #endif /* PCI_DEVICE_ID_INTEL_7505_0 */
66 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
67 #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
68 #endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
70 #define E7XXX_NR_CSROWS 8 /* number of csrows */
71 #define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */
73 /* E7XXX register addresses - device 0 function 0 */
74 #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
75 #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
77 * 31 Device width row 7 0=x8 1=x4
78 * 27 Device width row 6
79 * 23 Device width row 5
80 * 19 Device width row 4
81 * 15 Device width row 3
82 * 11 Device width row 2
83 * 7 Device width row 1
84 * 3 Device width row 0
86 #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
88 * 22 Number channels 0=1,1=2
89 * 19:18 DRB Granularity 32/64MB
91 #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
92 #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
93 #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
95 /* E7XXX register addresses - device 0 function 1 */
96 #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
97 #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
98 #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
99 /* error address register (32b) */
102 * 27:6 CE address (4k block 33:12)
105 #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
106 /* error address register (32b) */
109 * 27:6 CE address (4k block 33:12)
112 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
113 /* error syndrome register (16b) */
123 struct pci_dev
*bridge_ck
;
127 const struct e7xxx_dev_info
*dev_info
;
130 struct e7xxx_dev_info
{
132 const char *ctl_name
;
135 struct e7xxx_error_info
{
139 u16 dram_celog_syndrome
;
143 static const struct e7xxx_dev_info e7xxx_devs
[] = {
145 .err_dev
= PCI_DEVICE_ID_INTEL_7500_1_ERR
,
149 .err_dev
= PCI_DEVICE_ID_INTEL_7501_1_ERR
,
153 .err_dev
= PCI_DEVICE_ID_INTEL_7505_1_ERR
,
157 .err_dev
= PCI_DEVICE_ID_INTEL_7205_1_ERR
,
162 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
163 static inline int e7xxx_find_channel(u16 syndrome
)
165 debugf3("%s()\n", __func__
);
167 if ((syndrome
& 0xff00) == 0)
170 if ((syndrome
& 0x00ff) == 0)
173 if ((syndrome
& 0xf000) == 0 || (syndrome
& 0x0f00) == 0)
179 static unsigned long ctl_page_to_phys(struct mem_ctl_info
*mci
,
183 struct e7xxx_pvt
*pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
185 debugf3("%s()\n", __func__
);
187 if ((page
< pvt
->tolm
) ||
188 ((page
>= 0x100000) && (page
< pvt
->remapbase
)))
191 remap
= (page
- pvt
->tolm
) + pvt
->remapbase
;
193 if (remap
< pvt
->remaplimit
)
196 e7xxx_printk(KERN_ERR
, "Invalid page %lx - out of range\n", page
);
197 return pvt
->tolm
- 1;
200 static void process_ce(struct mem_ctl_info
*mci
,
201 struct e7xxx_error_info
*info
)
208 debugf3("%s()\n", __func__
);
209 /* read the error address */
210 error_1b
= info
->dram_celog_add
;
211 /* FIXME - should use PAGE_SHIFT */
212 page
= error_1b
>> 6; /* convert the address to 4k page */
213 /* read the syndrome */
214 syndrome
= info
->dram_celog_syndrome
;
215 /* FIXME - check for -1 */
216 row
= edac_mc_find_csrow_by_page(mci
, page
);
217 /* convert syndrome to channel */
218 channel
= e7xxx_find_channel(syndrome
);
219 edac_mc_handle_ce(mci
, page
, 0, syndrome
, row
, channel
, "e7xxx CE");
222 static void process_ce_no_info(struct mem_ctl_info
*mci
)
224 debugf3("%s()\n", __func__
);
225 edac_mc_handle_ce_no_info(mci
, "e7xxx CE log register overflow");
228 static void process_ue(struct mem_ctl_info
*mci
,
229 struct e7xxx_error_info
*info
)
231 u32 error_2b
, block_page
;
234 debugf3("%s()\n", __func__
);
235 /* read the error address */
236 error_2b
= info
->dram_uelog_add
;
237 /* FIXME - should use PAGE_SHIFT */
238 block_page
= error_2b
>> 6; /* convert to 4k address */
239 row
= edac_mc_find_csrow_by_page(mci
, block_page
);
240 edac_mc_handle_ue(mci
, block_page
, 0, row
, "e7xxx UE");
243 static void process_ue_no_info(struct mem_ctl_info
*mci
)
245 debugf3("%s()\n", __func__
);
246 edac_mc_handle_ue_no_info(mci
, "e7xxx UE log register overflow");
249 static void e7xxx_get_error_info (struct mem_ctl_info
*mci
,
250 struct e7xxx_error_info
*info
)
252 struct e7xxx_pvt
*pvt
;
254 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
255 pci_read_config_byte(pvt
->bridge_ck
, E7XXX_DRAM_FERR
,
257 pci_read_config_byte(pvt
->bridge_ck
, E7XXX_DRAM_NERR
,
260 if ((info
->dram_ferr
& 1) || (info
->dram_nerr
& 1)) {
261 pci_read_config_dword(pvt
->bridge_ck
, E7XXX_DRAM_CELOG_ADD
,
262 &info
->dram_celog_add
);
263 pci_read_config_word(pvt
->bridge_ck
,
264 E7XXX_DRAM_CELOG_SYNDROME
,
265 &info
->dram_celog_syndrome
);
268 if ((info
->dram_ferr
& 2) || (info
->dram_nerr
& 2))
269 pci_read_config_dword(pvt
->bridge_ck
, E7XXX_DRAM_UELOG_ADD
,
270 &info
->dram_uelog_add
);
272 if (info
->dram_ferr
& 3)
273 pci_write_bits8(pvt
->bridge_ck
, E7XXX_DRAM_FERR
, 0x03, 0x03);
275 if (info
->dram_nerr
& 3)
276 pci_write_bits8(pvt
->bridge_ck
, E7XXX_DRAM_NERR
, 0x03, 0x03);
279 static int e7xxx_process_error_info (struct mem_ctl_info
*mci
,
280 struct e7xxx_error_info
*info
, int handle_errors
)
286 /* decode and report errors */
287 if (info
->dram_ferr
& 1) { /* check first error correctable */
291 process_ce(mci
, info
);
294 if (info
->dram_ferr
& 2) { /* check first error uncorrectable */
298 process_ue(mci
, info
);
301 if (info
->dram_nerr
& 1) { /* check next error correctable */
305 if (info
->dram_ferr
& 1)
306 process_ce_no_info(mci
);
308 process_ce(mci
, info
);
312 if (info
->dram_nerr
& 2) { /* check next error uncorrectable */
316 if (info
->dram_ferr
& 2)
317 process_ue_no_info(mci
);
319 process_ue(mci
, info
);
326 static void e7xxx_check(struct mem_ctl_info
*mci
)
328 struct e7xxx_error_info info
;
330 debugf3("%s()\n", __func__
);
331 e7xxx_get_error_info(mci
, &info
);
332 e7xxx_process_error_info(mci
, &info
, 1);
335 static int e7xxx_probe1(struct pci_dev
*pdev
, int dev_idx
)
340 struct mem_ctl_info
*mci
= NULL
;
341 struct e7xxx_pvt
*pvt
= NULL
;
343 int drc_chan
= 1; /* Number of channels 0=1chan,1=2chan */
344 int drc_drbg
= 1; /* DRB granularity 0=32mb,1=64mb */
345 int drc_ddim
; /* DRAM Data Integrity Mode 0=none,2=edac */
347 unsigned long last_cumul_size
;
348 struct e7xxx_error_info discard
;
350 debugf0("%s(): mci\n", __func__
);
352 /* need to find out the number of channels */
353 pci_read_config_dword(pdev
, E7XXX_DRC
, &drc
);
355 /* only e7501 can be single channel */
356 if (dev_idx
== E7501
) {
357 drc_chan
= ((drc
>> 22) & 0x1);
358 drc_drbg
= (drc
>> 18) & 0x3;
361 drc_ddim
= (drc
>> 20) & 0x3;
362 mci
= edac_mc_alloc(sizeof(*pvt
), E7XXX_NR_CSROWS
, drc_chan
+ 1);
369 debugf3("%s(): init mci\n", __func__
);
370 mci
->mtype_cap
= MEM_FLAG_RDDR
;
371 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
|
373 /* FIXME - what if different memory types are in different csrows? */
374 mci
->mod_name
= EDAC_MOD_STR
;
375 mci
->mod_ver
= "$Revision: 1.5.2.9 $";
378 debugf3("%s(): init pvt\n", __func__
);
379 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
380 pvt
->dev_info
= &e7xxx_devs
[dev_idx
];
381 pvt
->bridge_ck
= pci_get_device(PCI_VENDOR_ID_INTEL
,
382 pvt
->dev_info
->err_dev
,
385 if (!pvt
->bridge_ck
) {
386 e7xxx_printk(KERN_ERR
, "error reporting device not found:"
387 "vendor %x device 0x%x (broken BIOS?)\n",
388 PCI_VENDOR_ID_INTEL
, e7xxx_devs
[dev_idx
].err_dev
);
392 debugf3("%s(): more mci init\n", __func__
);
393 mci
->ctl_name
= pvt
->dev_info
->ctl_name
;
394 mci
->edac_check
= e7xxx_check
;
395 mci
->ctl_page_to_phys
= ctl_page_to_phys
;
397 /* find out the device types */
398 pci_read_config_dword(pdev
, E7XXX_DRA
, &dra
);
401 * The dram row boundary (DRB) reg values are boundary address
402 * for each DRAM row with a granularity of 32 or 64MB (single/dual
403 * channel operation). DRB regs are cumulative; therefore DRB7 will
404 * contain the total memory contained in all eight rows.
406 for (last_cumul_size
= index
= 0; index
< mci
->nr_csrows
; index
++) {
409 /* mem_dev 0=x8, 1=x4 */
410 int mem_dev
= (dra
>> (index
* 4 + 3)) & 0x1;
411 struct csrow_info
*csrow
= &mci
->csrows
[index
];
413 pci_read_config_byte(mci
->pdev
, E7XXX_DRB
+ index
, &value
);
414 /* convert a 64 or 32 MiB DRB to a page size. */
415 cumul_size
= value
<< (25 + drc_drbg
- PAGE_SHIFT
);
416 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__
, index
,
419 if (cumul_size
== last_cumul_size
)
420 continue; /* not populated */
422 csrow
->first_page
= last_cumul_size
;
423 csrow
->last_page
= cumul_size
- 1;
424 csrow
->nr_pages
= cumul_size
- last_cumul_size
;
425 last_cumul_size
= cumul_size
;
426 csrow
->grain
= 1 << 12; /* 4KiB - resolution of CELOG */
427 csrow
->mtype
= MEM_RDDR
; /* only one type supported */
428 csrow
->dtype
= mem_dev
? DEV_X4
: DEV_X8
;
431 * if single channel or x8 devices then SECDED
432 * if dual channel and x4 then S4ECD4ED
435 if (drc_chan
&& mem_dev
) {
436 csrow
->edac_mode
= EDAC_S4ECD4ED
;
437 mci
->edac_cap
|= EDAC_FLAG_S4ECD4ED
;
439 csrow
->edac_mode
= EDAC_SECDED
;
440 mci
->edac_cap
|= EDAC_FLAG_SECDED
;
443 csrow
->edac_mode
= EDAC_NONE
;
446 mci
->edac_cap
|= EDAC_FLAG_NONE
;
448 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__
);
449 /* load the top of low memory, remap base, and remap limit vars */
450 pci_read_config_word(mci
->pdev
, E7XXX_TOLM
, &pci_data
);
451 pvt
->tolm
= ((u32
) pci_data
) << 4;
452 pci_read_config_word(mci
->pdev
, E7XXX_REMAPBASE
, &pci_data
);
453 pvt
->remapbase
= ((u32
) pci_data
) << 14;
454 pci_read_config_word(mci
->pdev
, E7XXX_REMAPLIMIT
, &pci_data
);
455 pvt
->remaplimit
= ((u32
) pci_data
) << 14;
456 e7xxx_printk(KERN_INFO
,
457 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt
->tolm
,
458 pvt
->remapbase
, pvt
->remaplimit
);
460 /* clear any pending errors, or initial state bits */
461 e7xxx_get_error_info(mci
, &discard
);
463 if (edac_mc_add_mc(mci
) != 0) {
464 debugf3("%s(): failed edac_mc_add_mc()\n", __func__
);
468 /* get this far and it's successful */
469 debugf3("%s(): success\n", __func__
);
474 if(pvt
!= NULL
&& pvt
->bridge_ck
)
475 pci_dev_put(pvt
->bridge_ck
);
482 /* returns count (>= 0), or negative on error */
483 static int __devinit
e7xxx_init_one(struct pci_dev
*pdev
,
484 const struct pci_device_id
*ent
)
486 debugf0("%s()\n", __func__
);
488 /* wake up and enable device */
489 return pci_enable_device(pdev
) ?
490 -EIO
: e7xxx_probe1(pdev
, ent
->driver_data
);
493 static void __devexit
e7xxx_remove_one(struct pci_dev
*pdev
)
495 struct mem_ctl_info
*mci
;
496 struct e7xxx_pvt
*pvt
;
498 debugf0("%s()\n", __func__
);
500 if ((mci
= edac_mc_del_mc(pdev
)) == NULL
)
503 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
504 pci_dev_put(pvt
->bridge_ck
);
508 static const struct pci_device_id e7xxx_pci_tbl
[] __devinitdata
= {
510 PCI_VEND_DEV(INTEL
, 7205_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
514 PCI_VEND_DEV(INTEL
, 7500_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
518 PCI_VEND_DEV(INTEL
, 7501_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
522 PCI_VEND_DEV(INTEL
, 7505_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
527 } /* 0 terminated list. */
530 MODULE_DEVICE_TABLE(pci
, e7xxx_pci_tbl
);
532 static struct pci_driver e7xxx_driver
= {
533 .name
= EDAC_MOD_STR
,
534 .probe
= e7xxx_init_one
,
535 .remove
= __devexit_p(e7xxx_remove_one
),
536 .id_table
= e7xxx_pci_tbl
,
539 static int __init
e7xxx_init(void)
541 return pci_register_driver(&e7xxx_driver
);
544 static void __exit
e7xxx_exit(void)
546 pci_unregister_driver(&e7xxx_driver
);
549 module_init(e7xxx_init
);
550 module_exit(e7xxx_exit
);
552 MODULE_LICENSE("GPL");
553 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
554 "Based on.work by Dan Hollis et al");
555 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");