drivers/edac/edac_mc.h

   1 /*
   2  * MC kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Based on work by Dan Hollis <goemon at anime dot net> and others.
   9  *      http://www.anime.net/~goemon/linux-ecc/
  10  *
  11  * NMI handling support added by
  12  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  13  *
  14  * $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $
  15  *
  16  */
  17
  18 #ifndef _EDAC_MC_H_
  19 #define _EDAC_MC_H_
  20
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/module.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/smp.h>
  26 #include <linux/pci.h>
  27 #include <linux/time.h>
  28 #include <linux/nmi.h>
  29 #include <linux/rcupdate.h>
  30 #include <linux/completion.h>
  31 #include <linux/kobject.h>
  32
  33 #define EDAC_MC_LABEL_LEN       31
  34 #define MC_PROC_NAME_MAX_LEN 7
  35
  36 #if PAGE_SHIFT < 20
  37 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  38 #else                           /* PAGE_SHIFT > 20 */
  39 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  40 #endif
  41
  42 #define edac_printk(level, prefix, fmt, arg...) \
  43         printk(level "EDAC " prefix ": " fmt, ##arg)
  44
  45 #define edac_mc_printk(mci, level, fmt, arg...) \
  46         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  47
  48 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  49         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  50
  51 /* prefixes for edac_printk() and edac_mc_printk() */
  52 #define EDAC_MC "MC"
  53 #define EDAC_PCI "PCI"
  54 #define EDAC_DEBUG "DEBUG"
  55
  56 #ifdef CONFIG_EDAC_DEBUG
  57 extern int edac_debug_level;
  58
  59 #define edac_debug_printk(level, fmt, arg...)                            \
  60         do {                                                             \
  61                 if (level <= edac_debug_level)                           \
  62                         edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
  63         } while(0)
  64
  65 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  66 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  67 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  68 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  69 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  70
  71 #else  /* !CONFIG_EDAC_DEBUG */
  72
  73 #define debugf0( ... )
  74 #define debugf1( ... )
  75 #define debugf2( ... )
  76 #define debugf3( ... )
  77 #define debugf4( ... )
  78
  79 #endif  /* !CONFIG_EDAC_DEBUG */
  80
  81 #define edac_xstr(s) edac_str(s)
  82 #define edac_str(s) #s
  83 #define EDAC_MOD_STR edac_xstr(KBUILD_BASENAME)
  84
  85 #define BIT(x) (1 << (x))
  86
  87 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
  88         PCI_DEVICE_ID_ ## vend ## _ ## dev
  89
  90 #if defined(CONFIG_X86) && defined(CONFIG_PCI)
  91 #define dev_name(dev) pci_name(to_pci_dev(dev))
  92 #else
  93 #define dev_name(dev) to_platform_device(dev)->name
  94 #endif
  95
  96 /* memory devices */
  97 enum dev_type {
  98         DEV_UNKNOWN = 0,
  99         DEV_X1,
 100         DEV_X2,
 101         DEV_X4,
 102         DEV_X8,
 103         DEV_X16,
 104         DEV_X32,                /* Do these parts exist? */
 105         DEV_X64                 /* Do these parts exist? */
 106 };
 107
 108 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 109 #define DEV_FLAG_X1             BIT(DEV_X1)
 110 #define DEV_FLAG_X2             BIT(DEV_X2)
 111 #define DEV_FLAG_X4             BIT(DEV_X4)
 112 #define DEV_FLAG_X8             BIT(DEV_X8)
 113 #define DEV_FLAG_X16            BIT(DEV_X16)
 114 #define DEV_FLAG_X32            BIT(DEV_X32)
 115 #define DEV_FLAG_X64            BIT(DEV_X64)
 116
 117 /* memory types */
 118 enum mem_type {
 119         MEM_EMPTY = 0,          /* Empty csrow */
 120         MEM_RESERVED,           /* Reserved csrow type */
 121         MEM_UNKNOWN,            /* Unknown csrow type */
 122         MEM_FPM,                /* Fast page mode */
 123         MEM_EDO,                /* Extended data out */
 124         MEM_BEDO,               /* Burst Extended data out */
 125         MEM_SDR,                /* Single data rate SDRAM */
 126         MEM_RDR,                /* Registered single data rate SDRAM */
 127         MEM_DDR,                /* Double data rate SDRAM */
 128         MEM_RDDR,               /* Registered Double data rate SDRAM */
 129         MEM_RMBS                /* Rambus DRAM */
 130 };
 131
 132 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 133 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 134 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 135 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 136 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 137 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 138 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 139 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 140 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 141 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 142 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 143
 144 /* chipset Error Detection and Correction capabilities and mode */
 145 enum edac_type {
 146         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 147         EDAC_NONE,              /* Doesnt support ECC */
 148         EDAC_RESERVED,          /* Reserved ECC type */
 149         EDAC_PARITY,            /* Detects parity errors */
 150         EDAC_EC,                /* Error Checking - no correction */
 151         EDAC_SECDED,            /* Single bit error correction, Double detection */
 152         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 153         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 154         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 155         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 156 };
 157
 158 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 159 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 160 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 161 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 162 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 163 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 164 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 165 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 166 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 167
 168 /* scrubbing capabilities */
 169 enum scrub_type {
 170         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 171         SCRUB_NONE,             /* No scrubber */
 172         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 173         SCRUB_SW_SRC,           /* Software scrub only errors */
 174         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 175         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 176         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 177         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 178         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 179         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 180 };
 181
 182 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 183 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC_CORR)
 184 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC_CORR)
 185 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 186 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 187 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC_CORR)
 188 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC_CORR)
 189 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 190
 191 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 192
 193 /*
 194  * There are several things to be aware of that aren't at all obvious:
 195  *
 196  *
 197  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 198  *
 199  * These are some of the many terms that are thrown about that don't always
 200  * mean what people think they mean (Inconceivable!).  In the interest of
 201  * creating a common ground for discussion, terms and their definitions
 202  * will be established.
 203  *
 204  * Memory devices:      The individual chip on a memory stick.  These devices
 205  *                      commonly output 4 and 8 bits each.  Grouping several
 206  *                      of these in parallel provides 64 bits which is common
 207  *                      for a memory stick.
 208  *
 209  * Memory Stick:        A printed circuit board that agregates multiple
 210  *                      memory devices in parallel.  This is the atomic
 211  *                      memory component that is purchaseable by Joe consumer
 212  *                      and loaded into a memory socket.
 213  *
 214  * Socket:              A physical connector on the motherboard that accepts
 215  *                      a single memory stick.
 216  *
 217  * Channel:             Set of memory devices on a memory stick that must be
 218  *                      grouped in parallel with one or more additional
 219  *                      channels from other memory sticks.  This parallel
 220  *                      grouping of the output from multiple channels are
 221  *                      necessary for the smallest granularity of memory access.
 222  *                      Some memory controllers are capable of single channel -
 223  *                      which means that memory sticks can be loaded
 224  *                      individually.  Other memory controllers are only
 225  *                      capable of dual channel - which means that memory
 226  *                      sticks must be loaded as pairs (see "socket set").
 227  *
 228  * Chip-select row:     All of the memory devices that are selected together.
 229  *                      for a single, minimum grain of memory access.
 230  *                      This selects all of the parallel memory devices across
 231  *                      all of the parallel channels.  Common chip-select rows
 232  *                      for single channel are 64 bits, for dual channel 128
 233  *                      bits.
 234  *
 235  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 236  *                      Motherboards commonly drive two chip-select pins to
 237  *                      a memory stick. A single-ranked stick, will occupy
 238  *                      only one of those rows. The other will be unused.
 239  *
 240  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 241  *                      access different sets of memory devices.  The two
 242  *                      rows cannot be accessed concurrently.
 243  *
 244  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 245  *                      A double-sided stick has two chip-select rows which
 246  *                      access different sets of memory devices.  The two
 247  *                      rows cannot be accessed concurrently.  "Double-sided"
 248  *                      is irrespective of the memory devices being mounted
 249  *                      on both sides of the memory stick.
 250  *
 251  * Socket set:          All of the memory sticks that are required for for
 252  *                      a single memory access or all of the memory sticks
 253  *                      spanned by a chip-select row.  A single socket set
 254  *                      has two chip-select rows and if double-sided sticks
 255  *                      are used these will occupy those chip-select rows.
 256  *
 257  * Bank:                This term is avoided because it is unclear when
 258  *                      needing to distinguish between chip-select rows and
 259  *                      socket sets.
 260  *
 261  * Controller pages:
 262  *
 263  * Physical pages:
 264  *
 265  * Virtual pages:
 266  *
 267  *
 268  * STRUCTURE ORGANIZATION AND CHOICES
 269  *
 270  *
 271  *
 272  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 273  */
 274
 275 struct channel_info {
 276         int chan_idx;           /* channel index */
 277         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 278         char label[EDAC_MC_LABEL_LEN + 1];  /* DIMM label on motherboard */
 279         struct csrow_info *csrow;       /* the parent */
 280 };
 281
 282 struct csrow_info {
 283         unsigned long first_page;       /* first page number in dimm */
 284         unsigned long last_page;        /* last page number in dimm */
 285         unsigned long page_mask;        /* used for interleaving -
 286                                          * 0UL for non intlv
 287                                          */
 288         u32 nr_pages;           /* number of pages in csrow */
 289         u32 grain;              /* granularity of reported error in bytes */
 290         int csrow_idx;          /* the chip-select row */
 291         enum dev_type dtype;    /* memory device type */
 292         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 293         u32 ce_count;           /* Correctable Errors for this csrow */
 294         enum mem_type mtype;    /* memory csrow type */
 295         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 296         struct mem_ctl_info *mci;       /* the parent */
 297
 298         struct kobject kobj;    /* sysfs kobject for this csrow */
 299         struct completion kobj_complete;
 300
 301         /* FIXME the number of CHANNELs might need to become dynamic */
 302         u32 nr_channels;
 303         struct channel_info *channels;
 304 };
 305
 306 struct mem_ctl_info {
 307         struct list_head link;  /* for global list of mem_ctl_info structs */
 308         unsigned long mtype_cap;        /* memory types supported by mc */
 309         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 310         unsigned long edac_cap; /* configuration capabilities - this is
 311                                  * closely related to edac_ctl_cap.  The
 312                                  * difference is that the controller may be
 313                                  * capable of s4ecd4ed which would be listed
 314                                  * in edac_ctl_cap, but if channels aren't
 315                                  * capable of s4ecd4ed then the edac_cap would
 316                                  * not have that capability.
 317                                  */
 318         unsigned long scrub_cap;        /* chipset scrub capabilities */
 319         enum scrub_type scrub_mode;     /* current scrub mode */
 320
 321         /* pointer to edac checking routine */
 322         void (*edac_check) (struct mem_ctl_info * mci);
 323         /*
 324          * Remaps memory pages: controller pages to physical pages.
 325          * For most MC's, this will be NULL.
 326          */
 327         /* FIXME - why not send the phys page to begin with? */
 328         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 329                                         unsigned long page);
 330         int mc_idx;
 331         int nr_csrows;
 332         struct csrow_info *csrows;
 333         /*
 334          * FIXME - what about controllers on other busses? - IDs must be
 335          * unique.  dev pointer should be sufficiently unique, but
 336          * BUS:SLOT.FUNC numbers may not be unique.
 337          */
 338         struct device *dev;
 339         const char *mod_name;
 340         const char *mod_ver;
 341         const char *ctl_name;
 342         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 343         void *pvt_info;
 344         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 345         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 346         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 347         u32 ce_count;           /* Total Correctable Errors for this MC */
 348         unsigned long start_time;       /* mci load start time (in jiffies) */
 349
 350         /* this stuff is for safe removal of mc devices from global list while
 351          * NMI handlers may be traversing list
 352          */
 353         struct rcu_head rcu;
 354         struct completion complete;
 355
 356         /* edac sysfs device control */
 357         struct kobject edac_mci_kobj;
 358         struct completion kobj_complete;
 359 };
 360
 361 #ifdef CONFIG_PCI
 362
 363 /* write all or some bits in a byte-register*/
 364 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 365                 u8 mask)
 366 {
 367         if (mask != 0xff) {
 368                 u8 buf;
 369
 370                 pci_read_config_byte(pdev, offset, &buf);
 371                 value &= mask;
 372                 buf &= ~mask;
 373                 value |= buf;
 374         }
 375
 376         pci_write_config_byte(pdev, offset, value);
 377 }
 378
 379 /* write all or some bits in a word-register*/
 380 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 381                 u16 value, u16 mask)
 382 {
 383         if (mask != 0xffff) {
 384                 u16 buf;
 385
 386                 pci_read_config_word(pdev, offset, &buf);
 387                 value &= mask;
 388                 buf &= ~mask;
 389                 value |= buf;
 390         }
 391
 392         pci_write_config_word(pdev, offset, value);
 393 }
 394
 395 /* write all or some bits in a dword-register*/
 396 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 397                 u32 value, u32 mask)
 398 {
 399         if (mask != 0xffff) {
 400                 u32 buf;
 401
 402                 pci_read_config_dword(pdev, offset, &buf);
 403                 value &= mask;
 404                 buf &= ~mask;
 405                 value |= buf;
 406         }
 407
 408         pci_write_config_dword(pdev, offset, value);
 409 }
 410
 411 #endif /* CONFIG_PCI */
 412
 413 #ifdef CONFIG_EDAC_DEBUG
 414 void edac_mc_dump_channel(struct channel_info *chan);
 415 void edac_mc_dump_mci(struct mem_ctl_info *mci);
 416 void edac_mc_dump_csrow(struct csrow_info *csrow);
 417 #endif  /* CONFIG_EDAC_DEBUG */
 418
 419 extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx);
 420 extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
 421 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 422                                         unsigned long page);
 423 extern void edac_mc_scrub_block(unsigned long page, unsigned long offset,
 424                 u32 size);
 425
 426 /*
 427  * The no info errors are used when error overflows are reported.
 428  * There are a limited number of error logging registers that can
 429  * be exausted.  When all registers are exhausted and an additional
 430  * error occurs then an error overflow register records that an
 431  * error occured and the type of error, but doesn't have any
 432  * further information.  The ce/ue versions make for cleaner
 433  * reporting logic and function interface - reduces conditional
 434  * statement clutter and extra function arguments.
 435  */
 436 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 437                 unsigned long page_frame_number, unsigned long offset_in_page,
 438                 unsigned long syndrome, int row, int channel,
 439                 const char *msg);
 440 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 441                 const char *msg);
 442 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 443                 unsigned long page_frame_number, unsigned long offset_in_page,
 444                 int row, const char *msg);
 445 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 446                 const char *msg);
 447
 448 /*
 449  * This kmalloc's and initializes all the structures.
 450  * Can't be used if all structures don't have the same lifetime.
 451  */
 452 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 453                 unsigned nr_chans);
 454
 455 /* Free an mc previously allocated by edac_mc_alloc() */
 456 extern void edac_mc_free(struct mem_ctl_info *mci);
 457
 458 #endif                          /* _EDAC_MC_H_ */