drivers/edac/mpc85xx_edac.c

   1 /*
   2  * Freescale MPC85xx Memory Controller kernel module
   3  *
   4  * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
   5  *
   6  * Author: Dave Jiang <djiang@mvista.com>
   7  *
   8  * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
   9  * the terms of the GNU General Public License version 2. This program
  10  * is licensed "as is" without any warranty of any kind, whether express
  11  * or implied.
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/ctype.h>
  18 #include <linux/io.h>
  19 #include <linux/mod_devicetable.h>
  20 #include <linux/edac.h>
  21 #include <linux/smp.h>
  22 #include <linux/gfp.h>
  23
  24 #include <linux/of_platform.h>
  25 #include <linux/of_device.h>
  26 #include "edac_module.h"
  27 #include "edac_core.h"
  28 #include "mpc85xx_edac.h"
  29
  30 static int edac_dev_idx;
  31 #ifdef CONFIG_PCI
  32 static int edac_pci_idx;
  33 #endif
  34 static int edac_mc_idx;
  35
  36 static u32 orig_ddr_err_disable;
  37 static u32 orig_ddr_err_sbe;
  38
  39 /*
  40  * PCI Err defines
  41  */
  42 #ifdef CONFIG_PCI
  43 static u32 orig_pci_err_cap_dr;
  44 static u32 orig_pci_err_en;
  45 #endif
  46
  47 static u32 orig_l2_err_disable;
  48 #ifdef CONFIG_FSL_SOC_BOOKE
  49 static u32 orig_hid1[2];
  50 #endif
  51
  52 /************************ MC SYSFS parts ***********************************/
  53
  54 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  55
  56 static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev,
  57                                               struct device_attribute *mattr,
  58                                               char *data)
  59 {
  60         struct mem_ctl_info *mci = to_mci(dev);
  61         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  62         return sprintf(data, "0x%08x",
  63                        in_be32(pdata->mc_vbase +
  64                                MPC85XX_MC_DATA_ERR_INJECT_HI));
  65 }
  66
  67 static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev,
  68                                               struct device_attribute *mattr,
  69                                               char *data)
  70 {
  71         struct mem_ctl_info *mci = to_mci(dev);
  72         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  73         return sprintf(data, "0x%08x",
  74                        in_be32(pdata->mc_vbase +
  75                                MPC85XX_MC_DATA_ERR_INJECT_LO));
  76 }
  77
  78 static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev,
  79                                            struct device_attribute *mattr,
  80                                            char *data)
  81 {
  82         struct mem_ctl_info *mci = to_mci(dev);
  83         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  84         return sprintf(data, "0x%08x",
  85                        in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
  86 }
  87
  88 static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev,
  89                                                struct device_attribute *mattr,
  90                                                const char *data, size_t count)
  91 {
  92         struct mem_ctl_info *mci = to_mci(dev);
  93         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  94         if (isdigit(*data)) {
  95                 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
  96                          simple_strtoul(data, NULL, 0));
  97                 return count;
  98         }
  99         return 0;
 100 }
 101
 102 static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev,
 103                                                struct device_attribute *mattr,
 104                                                const char *data, size_t count)
 105 {
 106         struct mem_ctl_info *mci = to_mci(dev);
 107         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 108         if (isdigit(*data)) {
 109                 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
 110                          simple_strtoul(data, NULL, 0));
 111                 return count;
 112         }
 113         return 0;
 114 }
 115
 116 static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
 117                                                struct device_attribute *mattr,
 118                                                const char *data, size_t count)
 119 {
 120         struct mem_ctl_info *mci = to_mci(dev);
 121         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 122         if (isdigit(*data)) {
 123                 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
 124                          simple_strtoul(data, NULL, 0));
 125                 return count;
 126         }
 127         return 0;
 128 }
 129
 130 DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
 131             mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store);
 132 DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
 133             mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store);
 134 DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
 135             mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store);
 136
 137 static struct attribute *mpc85xx_dev_attrs[] = {
 138         &dev_attr_inject_data_hi.attr,
 139         &dev_attr_inject_data_lo.attr,
 140         &dev_attr_inject_ctrl.attr,
 141         NULL
 142 };
 143
 144 ATTRIBUTE_GROUPS(mpc85xx_dev);
 145
 146 /**************************** PCI Err device ***************************/
 147 #ifdef CONFIG_PCI
 148
 149 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
 150 {
 151         struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 152         u32 err_detect;
 153
 154         err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
 155
 156         /* master aborts can happen during PCI config cycles */
 157         if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
 158                 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
 159                 return;
 160         }
 161
 162         printk(KERN_ERR "PCI error(s) detected\n");
 163         printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
 164
 165         printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
 166                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
 167         printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
 168                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
 169         printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
 170                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
 171         printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
 172                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
 173         printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
 174                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
 175
 176         /* clear error bits */
 177         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
 178
 179         if (err_detect & PCI_EDE_PERR_MASK)
 180                 edac_pci_handle_pe(pci, pci->ctl_name);
 181
 182         if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
 183                 edac_pci_handle_npe(pci, pci->ctl_name);
 184 }
 185
 186 static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
 187 {
 188         struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 189         u32 err_detect;
 190
 191         err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
 192
 193         pr_err("PCIe error(s) detected\n");
 194         pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
 195         pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n",
 196                         in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR));
 197         pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
 198                         in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
 199         pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
 200                         in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
 201         pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
 202                         in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
 203         pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
 204                         in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
 205
 206         /* clear error bits */
 207         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
 208 }
 209
 210 static int mpc85xx_pcie_find_capability(struct device_node *np)
 211 {
 212         struct pci_controller *hose;
 213
 214         if (!np)
 215                 return -EINVAL;
 216
 217         hose = pci_find_hose_for_OF_device(np);
 218
 219         return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
 220 }
 221
 222 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
 223 {
 224         struct edac_pci_ctl_info *pci = dev_id;
 225         struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 226         u32 err_detect;
 227
 228         err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
 229
 230         if (!err_detect)
 231                 return IRQ_NONE;
 232
 233         if (pdata->is_pcie)
 234                 mpc85xx_pcie_check(pci);
 235         else
 236                 mpc85xx_pci_check(pci);
 237
 238         return IRQ_HANDLED;
 239 }
 240
 241 int mpc85xx_pci_err_probe(struct platform_device *op)
 242 {
 243         struct edac_pci_ctl_info *pci;
 244         struct mpc85xx_pci_pdata *pdata;
 245         struct resource r;
 246         int res = 0;
 247
 248         if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
 249                 return -ENOMEM;
 250
 251         pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
 252         if (!pci)
 253                 return -ENOMEM;
 254
 255         /* make sure error reporting method is sane */
 256         switch (edac_op_state) {
 257         case EDAC_OPSTATE_POLL:
 258         case EDAC_OPSTATE_INT:
 259                 break;
 260         default:
 261                 edac_op_state = EDAC_OPSTATE_INT;
 262                 break;
 263         }
 264
 265         pdata = pci->pvt_info;
 266         pdata->name = "mpc85xx_pci_err";
 267         pdata->irq = NO_IRQ;
 268
 269         if (mpc85xx_pcie_find_capability(op->dev.of_node) > 0)
 270                 pdata->is_pcie = true;
 271
 272         dev_set_drvdata(&op->dev, pci);
 273         pci->dev = &op->dev;
 274         pci->mod_name = EDAC_MOD_STR;
 275         pci->ctl_name = pdata->name;
 276         pci->dev_name = dev_name(&op->dev);
 277
 278         if (edac_op_state == EDAC_OPSTATE_POLL) {
 279                 if (pdata->is_pcie)
 280                         pci->edac_check = mpc85xx_pcie_check;
 281                 else
 282                         pci->edac_check = mpc85xx_pci_check;
 283         }
 284
 285         pdata->edac_idx = edac_pci_idx++;
 286
 287         res = of_address_to_resource(op->dev.of_node, 0, &r);
 288         if (res) {
 289                 printk(KERN_ERR "%s: Unable to get resource for "
 290                        "PCI err regs\n", __func__);
 291                 goto err;
 292         }
 293
 294         /* we only need the error registers */
 295         r.start += 0xe00;
 296
 297         if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
 298                                         pdata->name)) {
 299                 printk(KERN_ERR "%s: Error while requesting mem region\n",
 300                        __func__);
 301                 res = -EBUSY;
 302                 goto err;
 303         }
 304
 305         pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
 306         if (!pdata->pci_vbase) {
 307                 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
 308                 res = -ENOMEM;
 309                 goto err;
 310         }
 311
 312         if (pdata->is_pcie) {
 313                 orig_pci_err_cap_dr =
 314                     in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
 315                 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
 316                 orig_pci_err_en =
 317                     in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
 318                 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
 319         } else {
 320                 orig_pci_err_cap_dr =
 321                     in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
 322
 323                 /* PCI master abort is expected during config cycles */
 324                 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
 325
 326                 orig_pci_err_en =
 327                     in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
 328
 329                 /* disable master abort reporting */
 330                 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
 331         }
 332
 333         /* clear error bits */
 334         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
 335
 336         if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
 337                 edac_dbg(3, "failed edac_pci_add_device()\n");
 338                 goto err;
 339         }
 340
 341         if (edac_op_state == EDAC_OPSTATE_INT) {
 342                 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 343                 res = devm_request_irq(&op->dev, pdata->irq,
 344                                        mpc85xx_pci_isr,
 345                                        IRQF_SHARED,
 346                                        "[EDAC] PCI err", pci);
 347                 if (res < 0) {
 348                         printk(KERN_ERR
 349                                "%s: Unable to request irq %d for "
 350                                "MPC85xx PCI err\n", __func__, pdata->irq);
 351                         irq_dispose_mapping(pdata->irq);
 352                         res = -ENODEV;
 353                         goto err2;
 354                 }
 355
 356                 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
 357                        pdata->irq);
 358         }
 359
 360         if (pdata->is_pcie) {
 361                 /*
 362                  * Enable all PCIe error interrupt & error detect except invalid
 363                  * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
 364                  * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
 365                  * detection enable bit. Because PCIe bus code to initialize and
 366                  * configure these PCIe devices on booting will use some invalid
 367                  * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
 368                  * notice information. So disable this detect to fix ugly print.
 369                  */
 370                 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
 371                          & ~PEX_ERR_ICCAIE_EN_BIT);
 372                 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
 373                          | PEX_ERR_ICCAD_DISR_BIT);
 374         }
 375
 376         devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
 377         edac_dbg(3, "success\n");
 378         printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
 379
 380         return 0;
 381
 382 err2:
 383         edac_pci_del_device(&op->dev);
 384 err:
 385         edac_pci_free_ctl_info(pci);
 386         devres_release_group(&op->dev, mpc85xx_pci_err_probe);
 387         return res;
 388 }
 389 EXPORT_SYMBOL(mpc85xx_pci_err_probe);
 390
 391 #endif                          /* CONFIG_PCI */
 392
 393 /**************************** L2 Err device ***************************/
 394
 395 /************************ L2 SYSFS parts ***********************************/
 396
 397 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
 398                                               *edac_dev, char *data)
 399 {
 400         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 401         return sprintf(data, "0x%08x",
 402                        in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
 403 }
 404
 405 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
 406                                               *edac_dev, char *data)
 407 {
 408         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 409         return sprintf(data, "0x%08x",
 410                        in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
 411 }
 412
 413 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
 414                                            *edac_dev, char *data)
 415 {
 416         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 417         return sprintf(data, "0x%08x",
 418                        in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
 419 }
 420
 421 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
 422                                                *edac_dev, const char *data,
 423                                                size_t count)
 424 {
 425         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 426         if (isdigit(*data)) {
 427                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
 428                          simple_strtoul(data, NULL, 0));
 429                 return count;
 430         }
 431         return 0;
 432 }
 433
 434 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
 435                                                *edac_dev, const char *data,
 436                                                size_t count)
 437 {
 438         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 439         if (isdigit(*data)) {
 440                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
 441                          simple_strtoul(data, NULL, 0));
 442                 return count;
 443         }
 444         return 0;
 445 }
 446
 447 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
 448                                             *edac_dev, const char *data,
 449                                             size_t count)
 450 {
 451         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 452         if (isdigit(*data)) {
 453                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
 454                          simple_strtoul(data, NULL, 0));
 455                 return count;
 456         }
 457         return 0;
 458 }
 459
 460 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
 461         {
 462          .attr = {
 463                   .name = "inject_data_hi",
 464                   .mode = (S_IRUGO | S_IWUSR)
 465                   },
 466          .show = mpc85xx_l2_inject_data_hi_show,
 467          .store = mpc85xx_l2_inject_data_hi_store},
 468         {
 469          .attr = {
 470                   .name = "inject_data_lo",
 471                   .mode = (S_IRUGO | S_IWUSR)
 472                   },
 473          .show = mpc85xx_l2_inject_data_lo_show,
 474          .store = mpc85xx_l2_inject_data_lo_store},
 475         {
 476          .attr = {
 477                   .name = "inject_ctrl",
 478                   .mode = (S_IRUGO | S_IWUSR)
 479                   },
 480          .show = mpc85xx_l2_inject_ctrl_show,
 481          .store = mpc85xx_l2_inject_ctrl_store},
 482
 483         /* End of list */
 484         {
 485          .attr = {.name = NULL}
 486          }
 487 };
 488
 489 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
 490                                             *edac_dev)
 491 {
 492         edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
 493 }
 494
 495 /***************************** L2 ops ***********************************/
 496
 497 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
 498 {
 499         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 500         u32 err_detect;
 501
 502         err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
 503
 504         if (!(err_detect & L2_EDE_MASK))
 505                 return;
 506
 507         printk(KERN_ERR "ECC Error in CPU L2 cache\n");
 508         printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
 509         printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
 510                in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
 511         printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
 512                in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
 513         printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
 514                in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
 515         printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
 516                in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
 517         printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
 518                in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
 519
 520         /* clear error detect register */
 521         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
 522
 523         if (err_detect & L2_EDE_CE_MASK)
 524                 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
 525
 526         if (err_detect & L2_EDE_UE_MASK)
 527                 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
 528 }
 529
 530 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
 531 {
 532         struct edac_device_ctl_info *edac_dev = dev_id;
 533         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 534         u32 err_detect;
 535
 536         err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
 537
 538         if (!(err_detect & L2_EDE_MASK))
 539                 return IRQ_NONE;
 540
 541         mpc85xx_l2_check(edac_dev);
 542
 543         return IRQ_HANDLED;
 544 }
 545
 546 static int mpc85xx_l2_err_probe(struct platform_device *op)
 547 {
 548         struct edac_device_ctl_info *edac_dev;
 549         struct mpc85xx_l2_pdata *pdata;
 550         struct resource r;
 551         int res;
 552
 553         if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
 554                 return -ENOMEM;
 555
 556         edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
 557                                               "cpu", 1, "L", 1, 2, NULL, 0,
 558                                               edac_dev_idx);
 559         if (!edac_dev) {
 560                 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
 561                 return -ENOMEM;
 562         }
 563
 564         pdata = edac_dev->pvt_info;
 565         pdata->name = "mpc85xx_l2_err";
 566         pdata->irq = NO_IRQ;
 567         edac_dev->dev = &op->dev;
 568         dev_set_drvdata(edac_dev->dev, edac_dev);
 569         edac_dev->ctl_name = pdata->name;
 570         edac_dev->dev_name = pdata->name;
 571
 572         res = of_address_to_resource(op->dev.of_node, 0, &r);
 573         if (res) {
 574                 printk(KERN_ERR "%s: Unable to get resource for "
 575                        "L2 err regs\n", __func__);
 576                 goto err;
 577         }
 578
 579         /* we only need the error registers */
 580         r.start += 0xe00;
 581
 582         if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
 583                                      pdata->name)) {
 584                 printk(KERN_ERR "%s: Error while requesting mem region\n",
 585                        __func__);
 586                 res = -EBUSY;
 587                 goto err;
 588         }
 589
 590         pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
 591         if (!pdata->l2_vbase) {
 592                 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
 593                 res = -ENOMEM;
 594                 goto err;
 595         }
 596
 597         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
 598
 599         orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
 600
 601         /* clear the err_dis */
 602         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
 603
 604         edac_dev->mod_name = EDAC_MOD_STR;
 605
 606         if (edac_op_state == EDAC_OPSTATE_POLL)
 607                 edac_dev->edac_check = mpc85xx_l2_check;
 608
 609         mpc85xx_set_l2_sysfs_attributes(edac_dev);
 610
 611         pdata->edac_idx = edac_dev_idx++;
 612
 613         if (edac_device_add_device(edac_dev) > 0) {
 614                 edac_dbg(3, "failed edac_device_add_device()\n");
 615                 goto err;
 616         }
 617
 618         if (edac_op_state == EDAC_OPSTATE_INT) {
 619                 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 620                 res = devm_request_irq(&op->dev, pdata->irq,
 621                                        mpc85xx_l2_isr, IRQF_SHARED,
 622                                        "[EDAC] L2 err", edac_dev);
 623                 if (res < 0) {
 624                         printk(KERN_ERR
 625                                "%s: Unable to request irq %d for "
 626                                "MPC85xx L2 err\n", __func__, pdata->irq);
 627                         irq_dispose_mapping(pdata->irq);
 628                         res = -ENODEV;
 629                         goto err2;
 630                 }
 631
 632                 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
 633                        pdata->irq);
 634
 635                 edac_dev->op_state = OP_RUNNING_INTERRUPT;
 636
 637                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
 638         }
 639
 640         devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
 641
 642         edac_dbg(3, "success\n");
 643         printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
 644
 645         return 0;
 646
 647 err2:
 648         edac_device_del_device(&op->dev);
 649 err:
 650         devres_release_group(&op->dev, mpc85xx_l2_err_probe);
 651         edac_device_free_ctl_info(edac_dev);
 652         return res;
 653 }
 654
 655 static int mpc85xx_l2_err_remove(struct platform_device *op)
 656 {
 657         struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
 658         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 659
 660         edac_dbg(0, "\n");
 661
 662         if (edac_op_state == EDAC_OPSTATE_INT) {
 663                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
 664                 irq_dispose_mapping(pdata->irq);
 665         }
 666
 667         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
 668         edac_device_del_device(&op->dev);
 669         edac_device_free_ctl_info(edac_dev);
 670         return 0;
 671 }
 672
 673 static const struct of_device_id mpc85xx_l2_err_of_match[] = {
 674 /* deprecate the fsl,85.. forms in the future, 2.6.30? */
 675         { .compatible = "fsl,8540-l2-cache-controller", },
 676         { .compatible = "fsl,8541-l2-cache-controller", },
 677         { .compatible = "fsl,8544-l2-cache-controller", },
 678         { .compatible = "fsl,8548-l2-cache-controller", },
 679         { .compatible = "fsl,8555-l2-cache-controller", },
 680         { .compatible = "fsl,8568-l2-cache-controller", },
 681         { .compatible = "fsl,mpc8536-l2-cache-controller", },
 682         { .compatible = "fsl,mpc8540-l2-cache-controller", },
 683         { .compatible = "fsl,mpc8541-l2-cache-controller", },
 684         { .compatible = "fsl,mpc8544-l2-cache-controller", },
 685         { .compatible = "fsl,mpc8548-l2-cache-controller", },
 686         { .compatible = "fsl,mpc8555-l2-cache-controller", },
 687         { .compatible = "fsl,mpc8560-l2-cache-controller", },
 688         { .compatible = "fsl,mpc8568-l2-cache-controller", },
 689         { .compatible = "fsl,mpc8569-l2-cache-controller", },
 690         { .compatible = "fsl,mpc8572-l2-cache-controller", },
 691         { .compatible = "fsl,p1020-l2-cache-controller", },
 692         { .compatible = "fsl,p1021-l2-cache-controller", },
 693         { .compatible = "fsl,p2020-l2-cache-controller", },
 694         {},
 695 };
 696 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
 697
 698 static struct platform_driver mpc85xx_l2_err_driver = {
 699         .probe = mpc85xx_l2_err_probe,
 700         .remove = mpc85xx_l2_err_remove,
 701         .driver = {
 702                 .name = "mpc85xx_l2_err",
 703                 .of_match_table = mpc85xx_l2_err_of_match,
 704         },
 705 };
 706
 707 /**************************** MC Err device ***************************/
 708
 709 /*
 710  * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
 711  * MPC8572 User's Manual.  Each line represents a syndrome bit column as a
 712  * 64-bit value, but split into an upper and lower 32-bit chunk.  The labels
 713  * below correspond to Freescale's manuals.
 714  */
 715 static unsigned int ecc_table[16] = {
 716         /* MSB           LSB */
 717         /* [0:31]    [32:63] */
 718         0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
 719         0x00ff00ff, 0x00fff0ff,
 720         0x0f0f0f0f, 0x0f0fff00,
 721         0x11113333, 0x7777000f,
 722         0x22224444, 0x8888222f,
 723         0x44448888, 0xffff4441,
 724         0x8888ffff, 0x11118882,
 725         0xffff1111, 0x22221114, /* Syndrome bit 0 */
 726 };
 727
 728 /*
 729  * Calculate the correct ECC value for a 64-bit value specified by high:low
 730  */
 731 static u8 calculate_ecc(u32 high, u32 low)
 732 {
 733         u32 mask_low;
 734         u32 mask_high;
 735         int bit_cnt;
 736         u8 ecc = 0;
 737         int i;
 738         int j;
 739
 740         for (i = 0; i < 8; i++) {
 741                 mask_high = ecc_table[i * 2];
 742                 mask_low = ecc_table[i * 2 + 1];
 743                 bit_cnt = 0;
 744
 745                 for (j = 0; j < 32; j++) {
 746                         if ((mask_high >> j) & 1)
 747                                 bit_cnt ^= (high >> j) & 1;
 748                         if ((mask_low >> j) & 1)
 749                                 bit_cnt ^= (low >> j) & 1;
 750                 }
 751
 752                 ecc |= bit_cnt << i;
 753         }
 754
 755         return ecc;
 756 }
 757
 758 /*
 759  * Create the syndrome code which is generated if the data line specified by
 760  * 'bit' failed.  Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
 761  * User's Manual and 9-61 in the MPC8572 User's Manual.
 762  */
 763 static u8 syndrome_from_bit(unsigned int bit) {
 764         int i;
 765         u8 syndrome = 0;
 766
 767         /*
 768          * Cycle through the upper or lower 32-bit portion of each value in
 769          * ecc_table depending on if 'bit' is in the upper or lower half of
 770          * 64-bit data.
 771          */
 772         for (i = bit < 32; i < 16; i += 2)
 773                 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
 774
 775         return syndrome;
 776 }
 777
 778 /*
 779  * Decode data and ecc syndrome to determine what went wrong
 780  * Note: This can only decode single-bit errors
 781  */
 782 static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
 783                        int *bad_data_bit, int *bad_ecc_bit)
 784 {
 785         int i;
 786         u8 syndrome;
 787
 788         *bad_data_bit = -1;
 789         *bad_ecc_bit = -1;
 790
 791         /*
 792          * Calculate the ECC of the captured data and XOR it with the captured
 793          * ECC to find an ECC syndrome value we can search for
 794          */
 795         syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
 796
 797         /* Check if a data line is stuck... */
 798         for (i = 0; i < 64; i++) {
 799                 if (syndrome == syndrome_from_bit(i)) {
 800                         *bad_data_bit = i;
 801                         return;
 802                 }
 803         }
 804
 805         /* If data is correct, check ECC bits for errors... */
 806         for (i = 0; i < 8; i++) {
 807                 if ((syndrome >> i) & 0x1) {
 808                         *bad_ecc_bit = i;
 809                         return;
 810                 }
 811         }
 812 }
 813
 814 #define make64(high, low) (((u64)(high) << 32) | (low))
 815
 816 static void mpc85xx_mc_check(struct mem_ctl_info *mci)
 817 {
 818         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 819         struct csrow_info *csrow;
 820         u32 bus_width;
 821         u32 err_detect;
 822         u32 syndrome;
 823         u64 err_addr;
 824         u32 pfn;
 825         int row_index;
 826         u32 cap_high;
 827         u32 cap_low;
 828         int bad_data_bit;
 829         int bad_ecc_bit;
 830
 831         err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
 832         if (!err_detect)
 833                 return;
 834
 835         mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
 836                           err_detect);
 837
 838         /* no more processing if not ECC bit errors */
 839         if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
 840                 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
 841                 return;
 842         }
 843
 844         syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
 845
 846         /* Mask off appropriate bits of syndrome based on bus width */
 847         bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
 848                         DSC_DBW_MASK) ? 32 : 64;
 849         if (bus_width == 64)
 850                 syndrome &= 0xff;
 851         else
 852                 syndrome &= 0xffff;
 853
 854         err_addr = make64(
 855                 in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_EXT_ADDRESS),
 856                 in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS));
 857         pfn = err_addr >> PAGE_SHIFT;
 858
 859         for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
 860                 csrow = mci->csrows[row_index];
 861                 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
 862                         break;
 863         }
 864
 865         cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
 866         cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
 867
 868         /*
 869          * Analyze single-bit errors on 64-bit wide buses
 870          * TODO: Add support for 32-bit wide buses
 871          */
 872         if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
 873                 sbe_ecc_decode(cap_high, cap_low, syndrome,
 874                                 &bad_data_bit, &bad_ecc_bit);
 875
 876                 if (bad_data_bit != -1)
 877                         mpc85xx_mc_printk(mci, KERN_ERR,
 878                                 "Faulty Data bit: %d\n", bad_data_bit);
 879                 if (bad_ecc_bit != -1)
 880                         mpc85xx_mc_printk(mci, KERN_ERR,
 881                                 "Faulty ECC bit: %d\n", bad_ecc_bit);
 882
 883                 mpc85xx_mc_printk(mci, KERN_ERR,
 884                         "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
 885                         cap_high ^ (1 << (bad_data_bit - 32)),
 886                         cap_low ^ (1 << bad_data_bit),
 887                         syndrome ^ (1 << bad_ecc_bit));
 888         }
 889
 890         mpc85xx_mc_printk(mci, KERN_ERR,
 891                         "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
 892                         cap_high, cap_low, syndrome);
 893         mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
 894         mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
 895
 896         /* we are out of range */
 897         if (row_index == mci->nr_csrows)
 898                 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
 899
 900         if (err_detect & DDR_EDE_SBE)
 901                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
 902                                      pfn, err_addr & ~PAGE_MASK, syndrome,
 903                                      row_index, 0, -1,
 904                                      mci->ctl_name, "");
 905
 906         if (err_detect & DDR_EDE_MBE)
 907                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
 908                                      pfn, err_addr & ~PAGE_MASK, syndrome,
 909                                      row_index, 0, -1,
 910                                      mci->ctl_name, "");
 911
 912         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
 913 }
 914
 915 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
 916 {
 917         struct mem_ctl_info *mci = dev_id;
 918         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 919         u32 err_detect;
 920
 921         err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
 922         if (!err_detect)
 923                 return IRQ_NONE;
 924
 925         mpc85xx_mc_check(mci);
 926
 927         return IRQ_HANDLED;
 928 }
 929
 930 static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
 931 {
 932         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 933         struct csrow_info *csrow;
 934         struct dimm_info *dimm;
 935         u32 sdram_ctl;
 936         u32 sdtype;
 937         enum mem_type mtype;
 938         u32 cs_bnds;
 939         int index;
 940
 941         sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
 942
 943         sdtype = sdram_ctl & DSC_SDTYPE_MASK;
 944         if (sdram_ctl & DSC_RD_EN) {
 945                 switch (sdtype) {
 946                 case DSC_SDTYPE_DDR:
 947                         mtype = MEM_RDDR;
 948                         break;
 949                 case DSC_SDTYPE_DDR2:
 950                         mtype = MEM_RDDR2;
 951                         break;
 952                 case DSC_SDTYPE_DDR3:
 953                         mtype = MEM_RDDR3;
 954                         break;
 955                 default:
 956                         mtype = MEM_UNKNOWN;
 957                         break;
 958                 }
 959         } else {
 960                 switch (sdtype) {
 961                 case DSC_SDTYPE_DDR:
 962                         mtype = MEM_DDR;
 963                         break;
 964                 case DSC_SDTYPE_DDR2:
 965                         mtype = MEM_DDR2;
 966                         break;
 967                 case DSC_SDTYPE_DDR3:
 968                         mtype = MEM_DDR3;
 969                         break;
 970                 default:
 971                         mtype = MEM_UNKNOWN;
 972                         break;
 973                 }
 974         }
 975
 976         for (index = 0; index < mci->nr_csrows; index++) {
 977                 u32 start;
 978                 u32 end;
 979
 980                 csrow = mci->csrows[index];
 981                 dimm = csrow->channels[0]->dimm;
 982
 983                 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
 984                                   (index * MPC85XX_MC_CS_BNDS_OFS));
 985
 986                 start = (cs_bnds & 0xffff0000) >> 16;
 987                 end   = (cs_bnds & 0x0000ffff);
 988
 989                 if (start == end)
 990                         continue;       /* not populated */
 991
 992                 start <<= (24 - PAGE_SHIFT);
 993                 end   <<= (24 - PAGE_SHIFT);
 994                 end    |= (1 << (24 - PAGE_SHIFT)) - 1;
 995
 996                 csrow->first_page = start;
 997                 csrow->last_page = end;
 998
 999                 dimm->nr_pages = end + 1 - start;
1000                 dimm->grain = 8;
1001                 dimm->mtype = mtype;
1002                 dimm->dtype = DEV_UNKNOWN;
1003                 if (sdram_ctl & DSC_X32_EN)
1004                         dimm->dtype = DEV_X32;
1005                 dimm->edac_mode = EDAC_SECDED;
1006         }
1007 }
1008
1009 static int mpc85xx_mc_err_probe(struct platform_device *op)
1010 {
1011         struct mem_ctl_info *mci;
1012         struct edac_mc_layer layers[2];
1013         struct mpc85xx_mc_pdata *pdata;
1014         struct resource r;
1015         u32 sdram_ctl;
1016         int res;
1017
1018         if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
1019                 return -ENOMEM;
1020
1021         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1022         layers[0].size = 4;
1023         layers[0].is_virt_csrow = true;
1024         layers[1].type = EDAC_MC_LAYER_CHANNEL;
1025         layers[1].size = 1;
1026         layers[1].is_virt_csrow = false;
1027         mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
1028                             sizeof(*pdata));
1029         if (!mci) {
1030                 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1031                 return -ENOMEM;
1032         }
1033
1034         pdata = mci->pvt_info;
1035         pdata->name = "mpc85xx_mc_err";
1036         pdata->irq = NO_IRQ;
1037         mci->pdev = &op->dev;
1038         pdata->edac_idx = edac_mc_idx++;
1039         dev_set_drvdata(mci->pdev, mci);
1040         mci->ctl_name = pdata->name;
1041         mci->dev_name = pdata->name;
1042
1043         res = of_address_to_resource(op->dev.of_node, 0, &r);
1044         if (res) {
1045                 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
1046                        __func__);
1047                 goto err;
1048         }
1049
1050         if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
1051                                      pdata->name)) {
1052                 printk(KERN_ERR "%s: Error while requesting mem region\n",
1053                        __func__);
1054                 res = -EBUSY;
1055                 goto err;
1056         }
1057
1058         pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
1059         if (!pdata->mc_vbase) {
1060                 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
1061                 res = -ENOMEM;
1062                 goto err;
1063         }
1064
1065         sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
1066         if (!(sdram_ctl & DSC_ECC_EN)) {
1067                 /* no ECC */
1068                 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
1069                 res = -ENODEV;
1070                 goto err;
1071         }
1072
1073         edac_dbg(3, "init mci\n");
1074         mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1075             MEM_FLAG_DDR | MEM_FLAG_DDR2;
1076         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1077         mci->edac_cap = EDAC_FLAG_SECDED;
1078         mci->mod_name = EDAC_MOD_STR;
1079         mci->mod_ver = MPC85XX_REVISION;
1080
1081         if (edac_op_state == EDAC_OPSTATE_POLL)
1082                 mci->edac_check = mpc85xx_mc_check;
1083
1084         mci->ctl_page_to_phys = NULL;
1085
1086         mci->scrub_mode = SCRUB_SW_SRC;
1087
1088         mpc85xx_init_csrows(mci);
1089
1090         /* store the original error disable bits */
1091         orig_ddr_err_disable =
1092             in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
1093         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
1094
1095         /* clear all error bits */
1096         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1097
1098         if (edac_mc_add_mc_with_groups(mci, mpc85xx_dev_groups)) {
1099                 edac_dbg(3, "failed edac_mc_add_mc()\n");
1100                 goto err;
1101         }
1102
1103         if (edac_op_state == EDAC_OPSTATE_INT) {
1104                 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
1105                          DDR_EIE_MBEE | DDR_EIE_SBEE);
1106
1107                 /* store the original error management threshold */
1108                 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
1109                                            MPC85XX_MC_ERR_SBE) & 0xff0000;
1110
1111                 /* set threshold to 1 error per interrupt */
1112                 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
1113
1114                 /* register interrupts */
1115                 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1116                 res = devm_request_irq(&op->dev, pdata->irq,
1117                                        mpc85xx_mc_isr,
1118                                        IRQF_SHARED,
1119                                        "[EDAC] MC err", mci);
1120                 if (res < 0) {
1121                         printk(KERN_ERR "%s: Unable to request irq %d for "
1122                                "MPC85xx DRAM ERR\n", __func__, pdata->irq);
1123                         irq_dispose_mapping(pdata->irq);
1124                         res = -ENODEV;
1125                         goto err2;
1126                 }
1127
1128                 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
1129                        pdata->irq);
1130         }
1131
1132         devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
1133         edac_dbg(3, "success\n");
1134         printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1135
1136         return 0;
1137
1138 err2:
1139         edac_mc_del_mc(&op->dev);
1140 err:
1141         devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1142         edac_mc_free(mci);
1143         return res;
1144 }
1145
1146 static int mpc85xx_mc_err_remove(struct platform_device *op)
1147 {
1148         struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1149         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1150
1151         edac_dbg(0, "\n");
1152
1153         if (edac_op_state == EDAC_OPSTATE_INT) {
1154                 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
1155                 irq_dispose_mapping(pdata->irq);
1156         }
1157
1158         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
1159                  orig_ddr_err_disable);
1160         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
1161
1162         edac_mc_del_mc(&op->dev);
1163         edac_mc_free(mci);
1164         return 0;
1165 }
1166
1167 static const struct of_device_id mpc85xx_mc_err_of_match[] = {
1168 /* deprecate the fsl,85.. forms in the future, 2.6.30? */
1169         { .compatible = "fsl,8540-memory-controller", },
1170         { .compatible = "fsl,8541-memory-controller", },
1171         { .compatible = "fsl,8544-memory-controller", },
1172         { .compatible = "fsl,8548-memory-controller", },
1173         { .compatible = "fsl,8555-memory-controller", },
1174         { .compatible = "fsl,8568-memory-controller", },
1175         { .compatible = "fsl,mpc8536-memory-controller", },
1176         { .compatible = "fsl,mpc8540-memory-controller", },
1177         { .compatible = "fsl,mpc8541-memory-controller", },
1178         { .compatible = "fsl,mpc8544-memory-controller", },
1179         { .compatible = "fsl,mpc8548-memory-controller", },
1180         { .compatible = "fsl,mpc8555-memory-controller", },
1181         { .compatible = "fsl,mpc8560-memory-controller", },
1182         { .compatible = "fsl,mpc8568-memory-controller", },
1183         { .compatible = "fsl,mpc8569-memory-controller", },
1184         { .compatible = "fsl,mpc8572-memory-controller", },
1185         { .compatible = "fsl,mpc8349-memory-controller", },
1186         { .compatible = "fsl,p1020-memory-controller", },
1187         { .compatible = "fsl,p1021-memory-controller", },
1188         { .compatible = "fsl,p2020-memory-controller", },
1189         { .compatible = "fsl,qoriq-memory-controller", },
1190         {},
1191 };
1192 MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
1193
1194 static struct platform_driver mpc85xx_mc_err_driver = {
1195         .probe = mpc85xx_mc_err_probe,
1196         .remove = mpc85xx_mc_err_remove,
1197         .driver = {
1198                 .name = "mpc85xx_mc_err",
1199                 .of_match_table = mpc85xx_mc_err_of_match,
1200         },
1201 };
1202
1203 #ifdef CONFIG_FSL_SOC_BOOKE
1204 static void __init mpc85xx_mc_clear_rfxe(void *data)
1205 {
1206         orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1207         mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
1208 }
1209 #endif
1210
1211 static int __init mpc85xx_mc_init(void)
1212 {
1213         int res = 0;
1214         u32 pvr = 0;
1215
1216         printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1217                "(C) 2006 Montavista Software\n");
1218
1219         /* make sure error reporting method is sane */
1220         switch (edac_op_state) {
1221         case EDAC_OPSTATE_POLL:
1222         case EDAC_OPSTATE_INT:
1223                 break;
1224         default:
1225                 edac_op_state = EDAC_OPSTATE_INT;
1226                 break;
1227         }
1228
1229         res = platform_driver_register(&mpc85xx_mc_err_driver);
1230         if (res)
1231                 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1232
1233         res = platform_driver_register(&mpc85xx_l2_err_driver);
1234         if (res)
1235                 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1236
1237 #ifdef CONFIG_FSL_SOC_BOOKE
1238         pvr = mfspr(SPRN_PVR);
1239
1240         if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
1241             (PVR_VER(pvr) == PVR_VER_E500V2)) {
1242                 /*
1243                  * need to clear HID1[RFXE] to disable machine check int
1244                  * so we can catch it
1245                  */
1246                 if (edac_op_state == EDAC_OPSTATE_INT)
1247                         on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
1248         }
1249 #endif
1250
1251         return 0;
1252 }
1253
1254 module_init(mpc85xx_mc_init);
1255
1256 #ifdef CONFIG_FSL_SOC_BOOKE
1257 static void __exit mpc85xx_mc_restore_hid1(void *data)
1258 {
1259         mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1260 }
1261 #endif
1262
1263 static void __exit mpc85xx_mc_exit(void)
1264 {
1265 #ifdef CONFIG_FSL_SOC_BOOKE
1266         u32 pvr = mfspr(SPRN_PVR);
1267
1268         if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
1269             (PVR_VER(pvr) == PVR_VER_E500V2)) {
1270                 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
1271         }
1272 #endif
1273         platform_driver_unregister(&mpc85xx_l2_err_driver);
1274         platform_driver_unregister(&mpc85xx_mc_err_driver);
1275 }
1276
1277 module_exit(mpc85xx_mc_exit);
1278
1279 MODULE_LICENSE("GPL");
1280 MODULE_AUTHOR("Montavista Software, Inc.");
1281 module_param(edac_op_state, int, 0444);
1282 MODULE_PARM_DESC(edac_op_state,
1283                  "EDAC Error Reporting state: 0=Poll, 2=Interrupt");