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Merge branch 'mm-readonly-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / edac / sb_edac.c
1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab
11 */
12
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
25 #include <asm/mce.h>
26
27 #include "edac_core.h"
28
29 /* Static vars */
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
32 static int probed;
33
34 /*
35 * Alter this version for the module when modifications are made
36 */
37 #define SBRIDGE_REVISION " Ver: 1.1.1 "
38 #define EDAC_MOD_STR "sbridge_edac"
39
40 /*
41 * Debug macros
42 */
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49 /*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
54
55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
56 static const u32 sbridge_dram_rule[] = {
57 0x80, 0x88, 0x90, 0x98, 0xa0,
58 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
59 };
60
61 static const u32 ibridge_dram_rule[] = {
62 0x60, 0x68, 0x70, 0x78, 0x80,
63 0x88, 0x90, 0x98, 0xa0, 0xa8,
64 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
65 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
66 };
67
68 static const u32 knl_dram_rule[] = {
69 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
70 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
71 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
72 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
73 0x100, 0x108, 0x110, 0x118, /* 20-23 */
74 };
75
76 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
77 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
78
79 static char *show_dram_attr(u32 attr)
80 {
81 switch (attr) {
82 case 0:
83 return "DRAM";
84 case 1:
85 return "MMCFG";
86 case 2:
87 return "NXM";
88 default:
89 return "unknown";
90 }
91 }
92
93 static const u32 sbridge_interleave_list[] = {
94 0x84, 0x8c, 0x94, 0x9c, 0xa4,
95 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
96 };
97
98 static const u32 ibridge_interleave_list[] = {
99 0x64, 0x6c, 0x74, 0x7c, 0x84,
100 0x8c, 0x94, 0x9c, 0xa4, 0xac,
101 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
102 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
103 };
104
105 static const u32 knl_interleave_list[] = {
106 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
107 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
108 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
109 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
110 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */
111 };
112
113 struct interleave_pkg {
114 unsigned char start;
115 unsigned char end;
116 };
117
118 static const struct interleave_pkg sbridge_interleave_pkg[] = {
119 { 0, 2 },
120 { 3, 5 },
121 { 8, 10 },
122 { 11, 13 },
123 { 16, 18 },
124 { 19, 21 },
125 { 24, 26 },
126 { 27, 29 },
127 };
128
129 static const struct interleave_pkg ibridge_interleave_pkg[] = {
130 { 0, 3 },
131 { 4, 7 },
132 { 8, 11 },
133 { 12, 15 },
134 { 16, 19 },
135 { 20, 23 },
136 { 24, 27 },
137 { 28, 31 },
138 };
139
140 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
141 int interleave)
142 {
143 return GET_BITFIELD(reg, table[interleave].start,
144 table[interleave].end);
145 }
146
147 /* Devices 12 Function 7 */
148
149 #define TOLM 0x80
150 #define TOHM 0x84
151 #define HASWELL_TOLM 0xd0
152 #define HASWELL_TOHM_0 0xd4
153 #define HASWELL_TOHM_1 0xd8
154 #define KNL_TOLM 0xd0
155 #define KNL_TOHM_0 0xd4
156 #define KNL_TOHM_1 0xd8
157
158 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
159 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
160
161 /* Device 13 Function 6 */
162
163 #define SAD_TARGET 0xf0
164
165 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
166
167 #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14)
168
169 #define SAD_CONTROL 0xf4
170
171 /* Device 14 function 0 */
172
173 static const u32 tad_dram_rule[] = {
174 0x40, 0x44, 0x48, 0x4c,
175 0x50, 0x54, 0x58, 0x5c,
176 0x60, 0x64, 0x68, 0x6c,
177 };
178 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
179
180 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
181 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
182 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
183 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
184 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
185 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
186 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
187
188 /* Device 15, function 0 */
189
190 #define MCMTR 0x7c
191 #define KNL_MCMTR 0x624
192
193 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
194 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
195 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
196
197 /* Device 15, function 1 */
198
199 #define RASENABLES 0xac
200 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
201
202 /* Device 15, functions 2-5 */
203
204 static const int mtr_regs[] = {
205 0x80, 0x84, 0x88,
206 };
207
208 static const int knl_mtr_reg = 0xb60;
209
210 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
211 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
212 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
213 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
214 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
215
216 static const u32 tad_ch_nilv_offset[] = {
217 0x90, 0x94, 0x98, 0x9c,
218 0xa0, 0xa4, 0xa8, 0xac,
219 0xb0, 0xb4, 0xb8, 0xbc,
220 };
221 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
222 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
223
224 static const u32 rir_way_limit[] = {
225 0x108, 0x10c, 0x110, 0x114, 0x118,
226 };
227 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
228
229 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
230 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
231
232 #define MAX_RIR_WAY 8
233
234 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
235 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
236 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
237 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
238 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
239 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
240 };
241
242 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
243 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
244
245 /* Device 16, functions 2-7 */
246
247 /*
248 * FIXME: Implement the error count reads directly
249 */
250
251 static const u32 correrrcnt[] = {
252 0x104, 0x108, 0x10c, 0x110,
253 };
254
255 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
256 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
257 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
258 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
259
260 static const u32 correrrthrsld[] = {
261 0x11c, 0x120, 0x124, 0x128,
262 };
263
264 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
265 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
266
267
268 /* Device 17, function 0 */
269
270 #define SB_RANK_CFG_A 0x0328
271
272 #define IB_RANK_CFG_A 0x0320
273
274 /*
275 * sbridge structs
276 */
277
278 #define NUM_CHANNELS 8 /* 2MC per socket, four chan per MC */
279 #define MAX_DIMMS 3 /* Max DIMMS per channel */
280 #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */
281 #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */
282 #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */
283 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
284
285 enum type {
286 SANDY_BRIDGE,
287 IVY_BRIDGE,
288 HASWELL,
289 BROADWELL,
290 KNIGHTS_LANDING,
291 };
292
293 struct sbridge_pvt;
294 struct sbridge_info {
295 enum type type;
296 u32 mcmtr;
297 u32 rankcfgr;
298 u64 (*get_tolm)(struct sbridge_pvt *pvt);
299 u64 (*get_tohm)(struct sbridge_pvt *pvt);
300 u64 (*rir_limit)(u32 reg);
301 u64 (*sad_limit)(u32 reg);
302 u32 (*interleave_mode)(u32 reg);
303 char* (*show_interleave_mode)(u32 reg);
304 u32 (*dram_attr)(u32 reg);
305 const u32 *dram_rule;
306 const u32 *interleave_list;
307 const struct interleave_pkg *interleave_pkg;
308 u8 max_sad;
309 u8 max_interleave;
310 u8 (*get_node_id)(struct sbridge_pvt *pvt);
311 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
312 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
313 struct pci_dev *pci_vtd;
314 };
315
316 struct sbridge_channel {
317 u32 ranks;
318 u32 dimms;
319 };
320
321 struct pci_id_descr {
322 int dev_id;
323 int optional;
324 };
325
326 struct pci_id_table {
327 const struct pci_id_descr *descr;
328 int n_devs;
329 };
330
331 struct sbridge_dev {
332 struct list_head list;
333 u8 bus, mc;
334 u8 node_id, source_id;
335 struct pci_dev **pdev;
336 int n_devs;
337 struct mem_ctl_info *mci;
338 };
339
340 struct knl_pvt {
341 struct pci_dev *pci_cha[KNL_MAX_CHAS];
342 struct pci_dev *pci_channel[KNL_MAX_CHANNELS];
343 struct pci_dev *pci_mc0;
344 struct pci_dev *pci_mc1;
345 struct pci_dev *pci_mc0_misc;
346 struct pci_dev *pci_mc1_misc;
347 struct pci_dev *pci_mc_info; /* tolm, tohm */
348 };
349
350 struct sbridge_pvt {
351 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
352 struct pci_dev *pci_sad0, *pci_sad1;
353 struct pci_dev *pci_ha0, *pci_ha1;
354 struct pci_dev *pci_br0, *pci_br1;
355 struct pci_dev *pci_ha1_ta;
356 struct pci_dev *pci_tad[NUM_CHANNELS];
357
358 struct sbridge_dev *sbridge_dev;
359
360 struct sbridge_info info;
361 struct sbridge_channel channel[NUM_CHANNELS];
362
363 /* Memory type detection */
364 bool is_mirrored, is_lockstep, is_close_pg;
365
366 /* Fifo double buffers */
367 struct mce mce_entry[MCE_LOG_LEN];
368 struct mce mce_outentry[MCE_LOG_LEN];
369
370 /* Fifo in/out counters */
371 unsigned mce_in, mce_out;
372
373 /* Count indicator to show errors not got */
374 unsigned mce_overrun;
375
376 /* Memory description */
377 u64 tolm, tohm;
378 struct knl_pvt knl;
379 };
380
381 #define PCI_DESCR(device_id, opt) \
382 .dev_id = (device_id), \
383 .optional = opt
384
385 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
386 /* Processor Home Agent */
387 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
388
389 /* Memory controller */
390 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
391 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
392 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
393 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
394 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
395 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
396 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
397
398 /* System Address Decoder */
399 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
400 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
401
402 /* Broadcast Registers */
403 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
404 };
405
406 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
407 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
408 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
409 {0,} /* 0 terminated list. */
410 };
411
412 /* This changes depending if 1HA or 2HA:
413 * 1HA:
414 * 0x0eb8 (17.0) is DDRIO0
415 * 2HA:
416 * 0x0ebc (17.4) is DDRIO0
417 */
418 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
419 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
420
421 /* pci ids */
422 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
423 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
424 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
425 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
426 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
427 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
428 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
429 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
430 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
431 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
432 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
433 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
434 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
435 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
436 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
437 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c
438 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d
439
440 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
441 /* Processor Home Agent */
442 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
443
444 /* Memory controller */
445 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
446 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
447 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
448 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
449 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
450 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
451
452 /* System Address Decoder */
453 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
454
455 /* Broadcast Registers */
456 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
457 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
458
459 /* Optional, mode 2HA */
460 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
461 #if 0
462 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
463 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
464 #endif
465 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
466 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
467 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) },
468 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) },
469
470 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
471 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
472 };
473
474 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
475 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
476 {0,} /* 0 terminated list. */
477 };
478
479 /* Haswell support */
480 /* EN processor:
481 * - 1 IMC
482 * - 3 DDR3 channels, 2 DPC per channel
483 * EP processor:
484 * - 1 or 2 IMC
485 * - 4 DDR4 channels, 3 DPC per channel
486 * EP 4S processor:
487 * - 2 IMC
488 * - 4 DDR4 channels, 3 DPC per channel
489 * EX processor:
490 * - 2 IMC
491 * - each IMC interfaces with a SMI 2 channel
492 * - each SMI channel interfaces with a scalable memory buffer
493 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
494 */
495 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
496 #define HASWELL_HASYSDEFEATURE2 0x84
497 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
498 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
499 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
500 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
501 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
502 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
503 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
504 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
505 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
506 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
507 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
508 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
509 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
510 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
511 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
512 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
513 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
514 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
515 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
516 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
517 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
518 static const struct pci_id_descr pci_dev_descr_haswell[] = {
519 /* first item must be the HA */
520 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
521
522 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) },
523 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) },
524
525 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) },
526
527 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) },
528 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) },
529 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) },
530 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) },
531 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) },
532 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
533
534 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
535 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) },
536 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) },
537 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) },
538
539 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
540 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
541 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) },
542 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) },
543 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
544 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
545 };
546
547 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
548 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
549 {0,} /* 0 terminated list. */
550 };
551
552 /* Knight's Landing Support */
553 /*
554 * KNL's memory channels are swizzled between memory controllers.
555 * MC0 is mapped to CH3,5,6 and MC1 is mapped to CH0,1,2
556 */
557 #define knl_channel_remap(channel) ((channel + 3) % 6)
558
559 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
560 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840
561 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
562 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL 0x7843
563 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
564 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844
565 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
566 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a
567 /* SAD target - 1-29-1 (1 of these) */
568 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b
569 /* Caching / Home Agent */
570 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c
571 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
572 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810
573
574 /*
575 * KNL differs from SB, IB, and Haswell in that it has multiple
576 * instances of the same device with the same device ID, so we handle that
577 * by creating as many copies in the table as we expect to find.
578 * (Like device ID must be grouped together.)
579 */
580
581 static const struct pci_id_descr pci_dev_descr_knl[] = {
582 [0] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0) },
583 [1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0) },
584 [2 ... 3] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0)},
585 [4 ... 41] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0) },
586 [42 ... 47] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL, 0) },
587 [48] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0) },
588 [49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0) },
589 };
590
591 static const struct pci_id_table pci_dev_descr_knl_table[] = {
592 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl),
593 {0,}
594 };
595
596 /*
597 * Broadwell support
598 *
599 * DE processor:
600 * - 1 IMC
601 * - 2 DDR3 channels, 2 DPC per channel
602 * EP processor:
603 * - 1 or 2 IMC
604 * - 4 DDR4 channels, 3 DPC per channel
605 * EP 4S processor:
606 * - 2 IMC
607 * - 4 DDR4 channels, 3 DPC per channel
608 * EX processor:
609 * - 2 IMC
610 * - each IMC interfaces with a SMI 2 channel
611 * - each SMI channel interfaces with a scalable memory buffer
612 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
613 */
614 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
615 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
616 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
617 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
618 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
619 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
620 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
621 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
622 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
623 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
624 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
625 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
626 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
627 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
628 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
629 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
630 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
631 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
632
633 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
634 /* first item must be the HA */
635 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) },
636
637 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) },
638 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) },
639
640 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1) },
641
642 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) },
643 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) },
644 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) },
645 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) },
646 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1) },
647 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1) },
648
649 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) },
650
651 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1) },
652 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1) },
653 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1) },
654 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1) },
655 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1) },
656 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1) },
657 };
658
659 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
660 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
661 {0,} /* 0 terminated list. */
662 };
663
664 /*
665 * pci_device_id table for which devices we are looking for
666 */
667 static const struct pci_device_id sbridge_pci_tbl[] = {
668 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
669 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
670 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
671 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
672 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0)},
673 {0,} /* 0 terminated list. */
674 };
675
676
677 /****************************************************************************
678 Ancillary status routines
679 ****************************************************************************/
680
681 static inline int numrank(enum type type, u32 mtr)
682 {
683 int ranks = (1 << RANK_CNT_BITS(mtr));
684 int max = 4;
685
686 if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
687 max = 8;
688
689 if (ranks > max) {
690 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
691 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
692 return -EINVAL;
693 }
694
695 return ranks;
696 }
697
698 static inline int numrow(u32 mtr)
699 {
700 int rows = (RANK_WIDTH_BITS(mtr) + 12);
701
702 if (rows < 13 || rows > 18) {
703 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
704 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
705 return -EINVAL;
706 }
707
708 return 1 << rows;
709 }
710
711 static inline int numcol(u32 mtr)
712 {
713 int cols = (COL_WIDTH_BITS(mtr) + 10);
714
715 if (cols > 12) {
716 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
717 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
718 return -EINVAL;
719 }
720
721 return 1 << cols;
722 }
723
724 static struct sbridge_dev *get_sbridge_dev(u8 bus, int multi_bus)
725 {
726 struct sbridge_dev *sbridge_dev;
727
728 /*
729 * If we have devices scattered across several busses that pertain
730 * to the same memory controller, we'll lump them all together.
731 */
732 if (multi_bus) {
733 return list_first_entry_or_null(&sbridge_edac_list,
734 struct sbridge_dev, list);
735 }
736
737 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
738 if (sbridge_dev->bus == bus)
739 return sbridge_dev;
740 }
741
742 return NULL;
743 }
744
745 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
746 const struct pci_id_table *table)
747 {
748 struct sbridge_dev *sbridge_dev;
749
750 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
751 if (!sbridge_dev)
752 return NULL;
753
754 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
755 GFP_KERNEL);
756 if (!sbridge_dev->pdev) {
757 kfree(sbridge_dev);
758 return NULL;
759 }
760
761 sbridge_dev->bus = bus;
762 sbridge_dev->n_devs = table->n_devs;
763 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
764
765 return sbridge_dev;
766 }
767
768 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
769 {
770 list_del(&sbridge_dev->list);
771 kfree(sbridge_dev->pdev);
772 kfree(sbridge_dev);
773 }
774
775 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
776 {
777 u32 reg;
778
779 /* Address range is 32:28 */
780 pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
781 return GET_TOLM(reg);
782 }
783
784 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
785 {
786 u32 reg;
787
788 pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
789 return GET_TOHM(reg);
790 }
791
792 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
793 {
794 u32 reg;
795
796 pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
797
798 return GET_TOLM(reg);
799 }
800
801 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
802 {
803 u32 reg;
804
805 pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
806
807 return GET_TOHM(reg);
808 }
809
810 static u64 rir_limit(u32 reg)
811 {
812 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
813 }
814
815 static u64 sad_limit(u32 reg)
816 {
817 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
818 }
819
820 static u32 interleave_mode(u32 reg)
821 {
822 return GET_BITFIELD(reg, 1, 1);
823 }
824
825 char *show_interleave_mode(u32 reg)
826 {
827 return interleave_mode(reg) ? "8:6" : "[8:6]XOR[18:16]";
828 }
829
830 static u32 dram_attr(u32 reg)
831 {
832 return GET_BITFIELD(reg, 2, 3);
833 }
834
835 static u64 knl_sad_limit(u32 reg)
836 {
837 return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
838 }
839
840 static u32 knl_interleave_mode(u32 reg)
841 {
842 return GET_BITFIELD(reg, 1, 2);
843 }
844
845 static char *knl_show_interleave_mode(u32 reg)
846 {
847 char *s;
848
849 switch (knl_interleave_mode(reg)) {
850 case 0:
851 s = "use address bits [8:6]";
852 break;
853 case 1:
854 s = "use address bits [10:8]";
855 break;
856 case 2:
857 s = "use address bits [14:12]";
858 break;
859 case 3:
860 s = "use address bits [32:30]";
861 break;
862 default:
863 WARN_ON(1);
864 break;
865 }
866
867 return s;
868 }
869
870 static u32 dram_attr_knl(u32 reg)
871 {
872 return GET_BITFIELD(reg, 3, 4);
873 }
874
875
876 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
877 {
878 u32 reg;
879 enum mem_type mtype;
880
881 if (pvt->pci_ddrio) {
882 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
883 &reg);
884 if (GET_BITFIELD(reg, 11, 11))
885 /* FIXME: Can also be LRDIMM */
886 mtype = MEM_RDDR3;
887 else
888 mtype = MEM_DDR3;
889 } else
890 mtype = MEM_UNKNOWN;
891
892 return mtype;
893 }
894
895 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
896 {
897 u32 reg;
898 bool registered = false;
899 enum mem_type mtype = MEM_UNKNOWN;
900
901 if (!pvt->pci_ddrio)
902 goto out;
903
904 pci_read_config_dword(pvt->pci_ddrio,
905 HASWELL_DDRCRCLKCONTROLS, &reg);
906 /* Is_Rdimm */
907 if (GET_BITFIELD(reg, 16, 16))
908 registered = true;
909
910 pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
911 if (GET_BITFIELD(reg, 14, 14)) {
912 if (registered)
913 mtype = MEM_RDDR4;
914 else
915 mtype = MEM_DDR4;
916 } else {
917 if (registered)
918 mtype = MEM_RDDR3;
919 else
920 mtype = MEM_DDR3;
921 }
922
923 out:
924 return mtype;
925 }
926
927 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
928 {
929 /* for KNL value is fixed */
930 return DEV_X16;
931 }
932
933 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
934 {
935 /* there's no way to figure out */
936 return DEV_UNKNOWN;
937 }
938
939 static enum dev_type __ibridge_get_width(u32 mtr)
940 {
941 enum dev_type type;
942
943 switch (mtr) {
944 case 3:
945 type = DEV_UNKNOWN;
946 break;
947 case 2:
948 type = DEV_X16;
949 break;
950 case 1:
951 type = DEV_X8;
952 break;
953 case 0:
954 type = DEV_X4;
955 break;
956 }
957
958 return type;
959 }
960
961 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
962 {
963 /*
964 * ddr3_width on the documentation but also valid for DDR4 on
965 * Haswell
966 */
967 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
968 }
969
970 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
971 {
972 /* ddr3_width on the documentation but also valid for DDR4 */
973 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
974 }
975
976 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
977 {
978 /* DDR4 RDIMMS and LRDIMMS are supported */
979 return MEM_RDDR4;
980 }
981
982 static u8 get_node_id(struct sbridge_pvt *pvt)
983 {
984 u32 reg;
985 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
986 return GET_BITFIELD(reg, 0, 2);
987 }
988
989 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
990 {
991 u32 reg;
992
993 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
994 return GET_BITFIELD(reg, 0, 3);
995 }
996
997 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
998 {
999 u32 reg;
1000
1001 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
1002 return GET_BITFIELD(reg, 0, 2);
1003 }
1004
1005
1006 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
1007 {
1008 u32 reg;
1009
1010 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
1011 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1012 }
1013
1014 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1015 {
1016 u64 rc;
1017 u32 reg;
1018
1019 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
1020 rc = GET_BITFIELD(reg, 26, 31);
1021 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
1022 rc = ((reg << 6) | rc) << 26;
1023
1024 return rc | 0x1ffffff;
1025 }
1026
1027 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1028 {
1029 u32 reg;
1030
1031 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
1032 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1033 }
1034
1035 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1036 {
1037 u64 rc;
1038 u32 reg_lo, reg_hi;
1039
1040 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, &reg_lo);
1041 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, &reg_hi);
1042 rc = ((u64)reg_hi << 32) | reg_lo;
1043 return rc | 0x3ffffff;
1044 }
1045
1046
1047 static u64 haswell_rir_limit(u32 reg)
1048 {
1049 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
1050 }
1051
1052 static inline u8 sad_pkg_socket(u8 pkg)
1053 {
1054 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
1055 return ((pkg >> 3) << 2) | (pkg & 0x3);
1056 }
1057
1058 static inline u8 sad_pkg_ha(u8 pkg)
1059 {
1060 return (pkg >> 2) & 0x1;
1061 }
1062
1063 /****************************************************************************
1064 Memory check routines
1065 ****************************************************************************/
1066 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
1067 {
1068 struct pci_dev *pdev = NULL;
1069
1070 do {
1071 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
1072 if (pdev && pdev->bus->number == bus)
1073 break;
1074 } while (pdev);
1075
1076 return pdev;
1077 }
1078
1079 /**
1080 * check_if_ecc_is_active() - Checks if ECC is active
1081 * @bus: Device bus
1082 * @type: Memory controller type
1083 * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
1084 * disabled
1085 */
1086 static int check_if_ecc_is_active(const u8 bus, enum type type)
1087 {
1088 struct pci_dev *pdev = NULL;
1089 u32 mcmtr, id;
1090
1091 switch (type) {
1092 case IVY_BRIDGE:
1093 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
1094 break;
1095 case HASWELL:
1096 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
1097 break;
1098 case SANDY_BRIDGE:
1099 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
1100 break;
1101 case BROADWELL:
1102 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
1103 break;
1104 case KNIGHTS_LANDING:
1105 /*
1106 * KNL doesn't group things by bus the same way
1107 * SB/IB/Haswell does.
1108 */
1109 id = PCI_DEVICE_ID_INTEL_KNL_IMC_TA;
1110 break;
1111 default:
1112 return -ENODEV;
1113 }
1114
1115 if (type != KNIGHTS_LANDING)
1116 pdev = get_pdev_same_bus(bus, id);
1117 else
1118 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, 0);
1119
1120 if (!pdev) {
1121 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
1122 "%04x:%04x! on bus %02d\n",
1123 PCI_VENDOR_ID_INTEL, id, bus);
1124 return -ENODEV;
1125 }
1126
1127 pci_read_config_dword(pdev,
1128 type == KNIGHTS_LANDING ? KNL_MCMTR : MCMTR, &mcmtr);
1129 if (!IS_ECC_ENABLED(mcmtr)) {
1130 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
1131 return -ENODEV;
1132 }
1133 return 0;
1134 }
1135
1136 /* Low bits of TAD limit, and some metadata. */
1137 static const u32 knl_tad_dram_limit_lo[] = {
1138 0x400, 0x500, 0x600, 0x700,
1139 0x800, 0x900, 0xa00, 0xb00,
1140 };
1141
1142 /* Low bits of TAD offset. */
1143 static const u32 knl_tad_dram_offset_lo[] = {
1144 0x404, 0x504, 0x604, 0x704,
1145 0x804, 0x904, 0xa04, 0xb04,
1146 };
1147
1148 /* High 16 bits of TAD limit and offset. */
1149 static const u32 knl_tad_dram_hi[] = {
1150 0x408, 0x508, 0x608, 0x708,
1151 0x808, 0x908, 0xa08, 0xb08,
1152 };
1153
1154 /* Number of ways a tad entry is interleaved. */
1155 static const u32 knl_tad_ways[] = {
1156 8, 6, 4, 3, 2, 1,
1157 };
1158
1159 /*
1160 * Retrieve the n'th Target Address Decode table entry
1161 * from the memory controller's TAD table.
1162 *
1163 * @pvt: driver private data
1164 * @entry: which entry you want to retrieve
1165 * @mc: which memory controller (0 or 1)
1166 * @offset: output tad range offset
1167 * @limit: output address of first byte above tad range
1168 * @ways: output number of interleave ways
1169 *
1170 * The offset value has curious semantics. It's a sort of running total
1171 * of the sizes of all the memory regions that aren't mapped in this
1172 * tad table.
1173 */
1174 static int knl_get_tad(const struct sbridge_pvt *pvt,
1175 const int entry,
1176 const int mc,
1177 u64 *offset,
1178 u64 *limit,
1179 int *ways)
1180 {
1181 u32 reg_limit_lo, reg_offset_lo, reg_hi;
1182 struct pci_dev *pci_mc;
1183 int way_id;
1184
1185 switch (mc) {
1186 case 0:
1187 pci_mc = pvt->knl.pci_mc0;
1188 break;
1189 case 1:
1190 pci_mc = pvt->knl.pci_mc1;
1191 break;
1192 default:
1193 WARN_ON(1);
1194 return -EINVAL;
1195 }
1196
1197 pci_read_config_dword(pci_mc,
1198 knl_tad_dram_limit_lo[entry], &reg_limit_lo);
1199 pci_read_config_dword(pci_mc,
1200 knl_tad_dram_offset_lo[entry], &reg_offset_lo);
1201 pci_read_config_dword(pci_mc,
1202 knl_tad_dram_hi[entry], &reg_hi);
1203
1204 /* Is this TAD entry enabled? */
1205 if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1206 return -ENODEV;
1207
1208 way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1209
1210 if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1211 *ways = knl_tad_ways[way_id];
1212 } else {
1213 *ways = 0;
1214 sbridge_printk(KERN_ERR,
1215 "Unexpected value %d in mc_tad_limit_lo wayness field\n",
1216 way_id);
1217 return -ENODEV;
1218 }
1219
1220 /*
1221 * The least significant 6 bits of base and limit are truncated.
1222 * For limit, we fill the missing bits with 1s.
1223 */
1224 *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1225 ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32);
1226 *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 |
1227 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1228
1229 return 0;
1230 }
1231
1232 /* Determine which memory controller is responsible for a given channel. */
1233 static int knl_channel_mc(int channel)
1234 {
1235 WARN_ON(channel < 0 || channel >= 6);
1236
1237 return channel < 3 ? 1 : 0;
1238 }
1239
1240 /*
1241 * Get the Nth entry from EDC_ROUTE_TABLE register.
1242 * (This is the per-tile mapping of logical interleave targets to
1243 * physical EDC modules.)
1244 *
1245 * entry 0: 0:2
1246 * 1: 3:5
1247 * 2: 6:8
1248 * 3: 9:11
1249 * 4: 12:14
1250 * 5: 15:17
1251 * 6: 18:20
1252 * 7: 21:23
1253 * reserved: 24:31
1254 */
1255 static u32 knl_get_edc_route(int entry, u32 reg)
1256 {
1257 WARN_ON(entry >= KNL_MAX_EDCS);
1258 return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1259 }
1260
1261 /*
1262 * Get the Nth entry from MC_ROUTE_TABLE register.
1263 * (This is the per-tile mapping of logical interleave targets to
1264 * physical DRAM channels modules.)
1265 *
1266 * entry 0: mc 0:2 channel 18:19
1267 * 1: mc 3:5 channel 20:21
1268 * 2: mc 6:8 channel 22:23
1269 * 3: mc 9:11 channel 24:25
1270 * 4: mc 12:14 channel 26:27
1271 * 5: mc 15:17 channel 28:29
1272 * reserved: 30:31
1273 *
1274 * Though we have 3 bits to identify the MC, we should only see
1275 * the values 0 or 1.
1276 */
1277
1278 static u32 knl_get_mc_route(int entry, u32 reg)
1279 {
1280 int mc, chan;
1281
1282 WARN_ON(entry >= KNL_MAX_CHANNELS);
1283
1284 mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1285 chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1286
1287 return knl_channel_remap(mc*3 + chan);
1288 }
1289
1290 /*
1291 * Render the EDC_ROUTE register in human-readable form.
1292 * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1293 */
1294 static void knl_show_edc_route(u32 reg, char *s)
1295 {
1296 int i;
1297
1298 for (i = 0; i < KNL_MAX_EDCS; i++) {
1299 s[i*2] = knl_get_edc_route(i, reg) + '0';
1300 s[i*2+1] = '-';
1301 }
1302
1303 s[KNL_MAX_EDCS*2 - 1] = '\0';
1304 }
1305
1306 /*
1307 * Render the MC_ROUTE register in human-readable form.
1308 * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1309 */
1310 static void knl_show_mc_route(u32 reg, char *s)
1311 {
1312 int i;
1313
1314 for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1315 s[i*2] = knl_get_mc_route(i, reg) + '0';
1316 s[i*2+1] = '-';
1317 }
1318
1319 s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1320 }
1321
1322 #define KNL_EDC_ROUTE 0xb8
1323 #define KNL_MC_ROUTE 0xb4
1324
1325 /* Is this dram rule backed by regular DRAM in flat mode? */
1326 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1327
1328 /* Is this dram rule cached? */
1329 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1330
1331 /* Is this rule backed by edc ? */
1332 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1333
1334 /* Is this rule backed by DRAM, cacheable in EDRAM? */
1335 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1336
1337 /* Is this rule mod3? */
1338 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1339
1340 /*
1341 * Figure out how big our RAM modules are.
1342 *
1343 * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1344 * have to figure this out from the SAD rules, interleave lists, route tables,
1345 * and TAD rules.
1346 *
1347 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1348 * inspect the TAD rules to figure out how large the SAD regions really are.
1349 *
1350 * When we know the real size of a SAD region and how many ways it's
1351 * interleaved, we know the individual contribution of each channel to
1352 * TAD is size/ways.
1353 *
1354 * Finally, we have to check whether each channel participates in each SAD
1355 * region.
1356 *
1357 * Fortunately, KNL only supports one DIMM per channel, so once we know how
1358 * much memory the channel uses, we know the DIMM is at least that large.
1359 * (The BIOS might possibly choose not to map all available memory, in which
1360 * case we will underreport the size of the DIMM.)
1361 *
1362 * In theory, we could try to determine the EDC sizes as well, but that would
1363 * only work in flat mode, not in cache mode.
1364 *
1365 * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1366 * elements)
1367 */
1368 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1369 {
1370 u64 sad_base, sad_size, sad_limit = 0;
1371 u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1372 int sad_rule = 0;
1373 int tad_rule = 0;
1374 int intrlv_ways, tad_ways;
1375 u32 first_pkg, pkg;
1376 int i;
1377 u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1378 u32 dram_rule, interleave_reg;
1379 u32 mc_route_reg[KNL_MAX_CHAS];
1380 u32 edc_route_reg[KNL_MAX_CHAS];
1381 int edram_only;
1382 char edc_route_string[KNL_MAX_EDCS*2];
1383 char mc_route_string[KNL_MAX_CHANNELS*2];
1384 int cur_reg_start;
1385 int mc;
1386 int channel;
1387 int way;
1388 int participants[KNL_MAX_CHANNELS];
1389 int participant_count = 0;
1390
1391 for (i = 0; i < KNL_MAX_CHANNELS; i++)
1392 mc_sizes[i] = 0;
1393
1394 /* Read the EDC route table in each CHA. */
1395 cur_reg_start = 0;
1396 for (i = 0; i < KNL_MAX_CHAS; i++) {
1397 pci_read_config_dword(pvt->knl.pci_cha[i],
1398 KNL_EDC_ROUTE, &edc_route_reg[i]);
1399
1400 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1401 knl_show_edc_route(edc_route_reg[i-1],
1402 edc_route_string);
1403 if (cur_reg_start == i-1)
1404 edac_dbg(0, "edc route table for CHA %d: %s\n",
1405 cur_reg_start, edc_route_string);
1406 else
1407 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1408 cur_reg_start, i-1, edc_route_string);
1409 cur_reg_start = i;
1410 }
1411 }
1412 knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1413 if (cur_reg_start == i-1)
1414 edac_dbg(0, "edc route table for CHA %d: %s\n",
1415 cur_reg_start, edc_route_string);
1416 else
1417 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1418 cur_reg_start, i-1, edc_route_string);
1419
1420 /* Read the MC route table in each CHA. */
1421 cur_reg_start = 0;
1422 for (i = 0; i < KNL_MAX_CHAS; i++) {
1423 pci_read_config_dword(pvt->knl.pci_cha[i],
1424 KNL_MC_ROUTE, &mc_route_reg[i]);
1425
1426 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1427 knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1428 if (cur_reg_start == i-1)
1429 edac_dbg(0, "mc route table for CHA %d: %s\n",
1430 cur_reg_start, mc_route_string);
1431 else
1432 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1433 cur_reg_start, i-1, mc_route_string);
1434 cur_reg_start = i;
1435 }
1436 }
1437 knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1438 if (cur_reg_start == i-1)
1439 edac_dbg(0, "mc route table for CHA %d: %s\n",
1440 cur_reg_start, mc_route_string);
1441 else
1442 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1443 cur_reg_start, i-1, mc_route_string);
1444
1445 /* Process DRAM rules */
1446 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1447 /* previous limit becomes the new base */
1448 sad_base = sad_limit;
1449
1450 pci_read_config_dword(pvt->pci_sad0,
1451 pvt->info.dram_rule[sad_rule], &dram_rule);
1452
1453 if (!DRAM_RULE_ENABLE(dram_rule))
1454 break;
1455
1456 edram_only = KNL_EDRAM_ONLY(dram_rule);
1457
1458 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1459 sad_size = sad_limit - sad_base;
1460
1461 pci_read_config_dword(pvt->pci_sad0,
1462 pvt->info.interleave_list[sad_rule], &interleave_reg);
1463
1464 /*
1465 * Find out how many ways this dram rule is interleaved.
1466 * We stop when we see the first channel again.
1467 */
1468 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1469 interleave_reg, 0);
1470 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1471 pkg = sad_pkg(pvt->info.interleave_pkg,
1472 interleave_reg, intrlv_ways);
1473
1474 if ((pkg & 0x8) == 0) {
1475 /*
1476 * 0 bit means memory is non-local,
1477 * which KNL doesn't support
1478 */
1479 edac_dbg(0, "Unexpected interleave target %d\n",
1480 pkg);
1481 return -1;
1482 }
1483
1484 if (pkg == first_pkg)
1485 break;
1486 }
1487 if (KNL_MOD3(dram_rule))
1488 intrlv_ways *= 3;
1489
1490 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1491 sad_rule,
1492 sad_base,
1493 sad_limit,
1494 intrlv_ways,
1495 edram_only ? ", EDRAM" : "");
1496
1497 /*
1498 * Find out how big the SAD region really is by iterating
1499 * over TAD tables (SAD regions may contain holes).
1500 * Each memory controller might have a different TAD table, so
1501 * we have to look at both.
1502 *
1503 * Livespace is the memory that's mapped in this TAD table,
1504 * deadspace is the holes (this could be the MMIO hole, or it
1505 * could be memory that's mapped by the other TAD table but
1506 * not this one).
1507 */
1508 for (mc = 0; mc < 2; mc++) {
1509 sad_actual_size[mc] = 0;
1510 tad_livespace = 0;
1511 for (tad_rule = 0;
1512 tad_rule < ARRAY_SIZE(
1513 knl_tad_dram_limit_lo);
1514 tad_rule++) {
1515 if (knl_get_tad(pvt,
1516 tad_rule,
1517 mc,
1518 &tad_deadspace,
1519 &tad_limit,
1520 &tad_ways))
1521 break;
1522
1523 tad_size = (tad_limit+1) -
1524 (tad_livespace + tad_deadspace);
1525 tad_livespace += tad_size;
1526 tad_base = (tad_limit+1) - tad_size;
1527
1528 if (tad_base < sad_base) {
1529 if (tad_limit > sad_base)
1530 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1531 } else if (tad_base < sad_limit) {
1532 if (tad_limit+1 > sad_limit) {
1533 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1534 } else {
1535 /* TAD region is completely inside SAD region */
1536 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1537 tad_rule, tad_base,
1538 tad_limit, tad_size,
1539 mc);
1540 sad_actual_size[mc] += tad_size;
1541 }
1542 }
1543 tad_base = tad_limit+1;
1544 }
1545 }
1546
1547 for (mc = 0; mc < 2; mc++) {
1548 edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1549 mc, sad_actual_size[mc], sad_actual_size[mc]);
1550 }
1551
1552 /* Ignore EDRAM rule */
1553 if (edram_only)
1554 continue;
1555
1556 /* Figure out which channels participate in interleave. */
1557 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1558 participants[channel] = 0;
1559
1560 /* For each channel, does at least one CHA have
1561 * this channel mapped to the given target?
1562 */
1563 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1564 for (way = 0; way < intrlv_ways; way++) {
1565 int target;
1566 int cha;
1567
1568 if (KNL_MOD3(dram_rule))
1569 target = way;
1570 else
1571 target = 0x7 & sad_pkg(
1572 pvt->info.interleave_pkg, interleave_reg, way);
1573
1574 for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1575 if (knl_get_mc_route(target,
1576 mc_route_reg[cha]) == channel
1577 && !participants[channel]) {
1578 participant_count++;
1579 participants[channel] = 1;
1580 break;
1581 }
1582 }
1583 }
1584 }
1585
1586 if (participant_count != intrlv_ways)
1587 edac_dbg(0, "participant_count (%d) != interleave_ways (%d): DIMM size may be incorrect\n",
1588 participant_count, intrlv_ways);
1589
1590 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1591 mc = knl_channel_mc(channel);
1592 if (participants[channel]) {
1593 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1594 channel,
1595 sad_actual_size[mc]/intrlv_ways,
1596 sad_rule);
1597 mc_sizes[channel] +=
1598 sad_actual_size[mc]/intrlv_ways;
1599 }
1600 }
1601 }
1602
1603 return 0;
1604 }
1605
1606 static int get_dimm_config(struct mem_ctl_info *mci)
1607 {
1608 struct sbridge_pvt *pvt = mci->pvt_info;
1609 struct dimm_info *dimm;
1610 unsigned i, j, banks, ranks, rows, cols, npages;
1611 u64 size;
1612 u32 reg;
1613 enum edac_type mode;
1614 enum mem_type mtype;
1615 int channels = pvt->info.type == KNIGHTS_LANDING ?
1616 KNL_MAX_CHANNELS : NUM_CHANNELS;
1617 u64 knl_mc_sizes[KNL_MAX_CHANNELS];
1618
1619 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1620 pvt->info.type == KNIGHTS_LANDING)
1621 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
1622 else
1623 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
1624
1625 if (pvt->info.type == KNIGHTS_LANDING)
1626 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1627 else
1628 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1629
1630 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1631 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1632 pvt->sbridge_dev->mc,
1633 pvt->sbridge_dev->node_id,
1634 pvt->sbridge_dev->source_id);
1635
1636 /* KNL doesn't support mirroring or lockstep,
1637 * and is always closed page
1638 */
1639 if (pvt->info.type == KNIGHTS_LANDING) {
1640 mode = EDAC_S4ECD4ED;
1641 pvt->is_mirrored = false;
1642
1643 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1644 return -1;
1645 } else {
1646 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
1647 if (IS_MIRROR_ENABLED(reg)) {
1648 edac_dbg(0, "Memory mirror is enabled\n");
1649 pvt->is_mirrored = true;
1650 } else {
1651 edac_dbg(0, "Memory mirror is disabled\n");
1652 pvt->is_mirrored = false;
1653 }
1654
1655 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
1656 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1657 edac_dbg(0, "Lockstep is enabled\n");
1658 mode = EDAC_S8ECD8ED;
1659 pvt->is_lockstep = true;
1660 } else {
1661 edac_dbg(0, "Lockstep is disabled\n");
1662 mode = EDAC_S4ECD4ED;
1663 pvt->is_lockstep = false;
1664 }
1665 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1666 edac_dbg(0, "address map is on closed page mode\n");
1667 pvt->is_close_pg = true;
1668 } else {
1669 edac_dbg(0, "address map is on open page mode\n");
1670 pvt->is_close_pg = false;
1671 }
1672 }
1673
1674 mtype = pvt->info.get_memory_type(pvt);
1675 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
1676 edac_dbg(0, "Memory is registered\n");
1677 else if (mtype == MEM_UNKNOWN)
1678 edac_dbg(0, "Cannot determine memory type\n");
1679 else
1680 edac_dbg(0, "Memory is unregistered\n");
1681
1682 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
1683 banks = 16;
1684 else
1685 banks = 8;
1686
1687 for (i = 0; i < channels; i++) {
1688 u32 mtr;
1689
1690 int max_dimms_per_channel;
1691
1692 if (pvt->info.type == KNIGHTS_LANDING) {
1693 max_dimms_per_channel = 1;
1694 if (!pvt->knl.pci_channel[i])
1695 continue;
1696 } else {
1697 max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1698 if (!pvt->pci_tad[i])
1699 continue;
1700 }
1701
1702 for (j = 0; j < max_dimms_per_channel; j++) {
1703 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1704 i, j, 0);
1705 if (pvt->info.type == KNIGHTS_LANDING) {
1706 pci_read_config_dword(pvt->knl.pci_channel[i],
1707 knl_mtr_reg, &mtr);
1708 } else {
1709 pci_read_config_dword(pvt->pci_tad[i],
1710 mtr_regs[j], &mtr);
1711 }
1712 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
1713 if (IS_DIMM_PRESENT(mtr)) {
1714 pvt->channel[i].dimms++;
1715
1716 ranks = numrank(pvt->info.type, mtr);
1717
1718 if (pvt->info.type == KNIGHTS_LANDING) {
1719 /* For DDR4, this is fixed. */
1720 cols = 1 << 10;
1721 rows = knl_mc_sizes[i] /
1722 ((u64) cols * ranks * banks * 8);
1723 } else {
1724 rows = numrow(mtr);
1725 cols = numcol(mtr);
1726 }
1727
1728 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1729 npages = MiB_TO_PAGES(size);
1730
1731 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1732 pvt->sbridge_dev->mc, i/4, i%4, j,
1733 size, npages,
1734 banks, ranks, rows, cols);
1735
1736 dimm->nr_pages = npages;
1737 dimm->grain = 32;
1738 dimm->dtype = pvt->info.get_width(pvt, mtr);
1739 dimm->mtype = mtype;
1740 dimm->edac_mode = mode;
1741 snprintf(dimm->label, sizeof(dimm->label),
1742 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1743 pvt->sbridge_dev->source_id, i/4, i%4, j);
1744 }
1745 }
1746 }
1747
1748 return 0;
1749 }
1750
1751 static void get_memory_layout(const struct mem_ctl_info *mci)
1752 {
1753 struct sbridge_pvt *pvt = mci->pvt_info;
1754 int i, j, k, n_sads, n_tads, sad_interl;
1755 u32 reg;
1756 u64 limit, prv = 0;
1757 u64 tmp_mb;
1758 u32 gb, mb;
1759 u32 rir_way;
1760
1761 /*
1762 * Step 1) Get TOLM/TOHM ranges
1763 */
1764
1765 pvt->tolm = pvt->info.get_tolm(pvt);
1766 tmp_mb = (1 + pvt->tolm) >> 20;
1767
1768 gb = div_u64_rem(tmp_mb, 1024, &mb);
1769 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1770 gb, (mb*1000)/1024, (u64)pvt->tolm);
1771
1772 /* Address range is already 45:25 */
1773 pvt->tohm = pvt->info.get_tohm(pvt);
1774 tmp_mb = (1 + pvt->tohm) >> 20;
1775
1776 gb = div_u64_rem(tmp_mb, 1024, &mb);
1777 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1778 gb, (mb*1000)/1024, (u64)pvt->tohm);
1779
1780 /*
1781 * Step 2) Get SAD range and SAD Interleave list
1782 * TAD registers contain the interleave wayness. However, it
1783 * seems simpler to just discover it indirectly, with the
1784 * algorithm bellow.
1785 */
1786 prv = 0;
1787 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1788 /* SAD_LIMIT Address range is 45:26 */
1789 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1790 &reg);
1791 limit = pvt->info.sad_limit(reg);
1792
1793 if (!DRAM_RULE_ENABLE(reg))
1794 continue;
1795
1796 if (limit <= prv)
1797 break;
1798
1799 tmp_mb = (limit + 1) >> 20;
1800 gb = div_u64_rem(tmp_mb, 1024, &mb);
1801 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1802 n_sads,
1803 show_dram_attr(pvt->info.dram_attr(reg)),
1804 gb, (mb*1000)/1024,
1805 ((u64)tmp_mb) << 20L,
1806 pvt->info.show_interleave_mode(reg),
1807 reg);
1808 prv = limit;
1809
1810 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1811 &reg);
1812 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1813 for (j = 0; j < 8; j++) {
1814 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1815 if (j > 0 && sad_interl == pkg)
1816 break;
1817
1818 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1819 n_sads, j, pkg);
1820 }
1821 }
1822
1823 if (pvt->info.type == KNIGHTS_LANDING)
1824 return;
1825
1826 /*
1827 * Step 3) Get TAD range
1828 */
1829 prv = 0;
1830 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1831 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1832 &reg);
1833 limit = TAD_LIMIT(reg);
1834 if (limit <= prv)
1835 break;
1836 tmp_mb = (limit + 1) >> 20;
1837
1838 gb = div_u64_rem(tmp_mb, 1024, &mb);
1839 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1840 n_tads, gb, (mb*1000)/1024,
1841 ((u64)tmp_mb) << 20L,
1842 (u32)TAD_SOCK(reg),
1843 (u32)TAD_CH(reg),
1844 (u32)TAD_TGT0(reg),
1845 (u32)TAD_TGT1(reg),
1846 (u32)TAD_TGT2(reg),
1847 (u32)TAD_TGT3(reg),
1848 reg);
1849 prv = limit;
1850 }
1851
1852 /*
1853 * Step 4) Get TAD offsets, per each channel
1854 */
1855 for (i = 0; i < NUM_CHANNELS; i++) {
1856 if (!pvt->channel[i].dimms)
1857 continue;
1858 for (j = 0; j < n_tads; j++) {
1859 pci_read_config_dword(pvt->pci_tad[i],
1860 tad_ch_nilv_offset[j],
1861 &reg);
1862 tmp_mb = TAD_OFFSET(reg) >> 20;
1863 gb = div_u64_rem(tmp_mb, 1024, &mb);
1864 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1865 i, j,
1866 gb, (mb*1000)/1024,
1867 ((u64)tmp_mb) << 20L,
1868 reg);
1869 }
1870 }
1871
1872 /*
1873 * Step 6) Get RIR Wayness/Limit, per each channel
1874 */
1875 for (i = 0; i < NUM_CHANNELS; i++) {
1876 if (!pvt->channel[i].dimms)
1877 continue;
1878 for (j = 0; j < MAX_RIR_RANGES; j++) {
1879 pci_read_config_dword(pvt->pci_tad[i],
1880 rir_way_limit[j],
1881 &reg);
1882
1883 if (!IS_RIR_VALID(reg))
1884 continue;
1885
1886 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1887 rir_way = 1 << RIR_WAY(reg);
1888 gb = div_u64_rem(tmp_mb, 1024, &mb);
1889 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1890 i, j,
1891 gb, (mb*1000)/1024,
1892 ((u64)tmp_mb) << 20L,
1893 rir_way,
1894 reg);
1895
1896 for (k = 0; k < rir_way; k++) {
1897 pci_read_config_dword(pvt->pci_tad[i],
1898 rir_offset[j][k],
1899 &reg);
1900 tmp_mb = RIR_OFFSET(reg) << 6;
1901
1902 gb = div_u64_rem(tmp_mb, 1024, &mb);
1903 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1904 i, j, k,
1905 gb, (mb*1000)/1024,
1906 ((u64)tmp_mb) << 20L,
1907 (u32)RIR_RNK_TGT(reg),
1908 reg);
1909 }
1910 }
1911 }
1912 }
1913
1914 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1915 {
1916 struct sbridge_dev *sbridge_dev;
1917
1918 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1919 if (sbridge_dev->node_id == node_id)
1920 return sbridge_dev->mci;
1921 }
1922 return NULL;
1923 }
1924
1925 static int get_memory_error_data(struct mem_ctl_info *mci,
1926 u64 addr,
1927 u8 *socket, u8 *ha,
1928 long *channel_mask,
1929 u8 *rank,
1930 char **area_type, char *msg)
1931 {
1932 struct mem_ctl_info *new_mci;
1933 struct sbridge_pvt *pvt = mci->pvt_info;
1934 struct pci_dev *pci_ha;
1935 int n_rir, n_sads, n_tads, sad_way, sck_xch;
1936 int sad_interl, idx, base_ch;
1937 int interleave_mode, shiftup = 0;
1938 unsigned sad_interleave[pvt->info.max_interleave];
1939 u32 reg, dram_rule;
1940 u8 ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
1941 u32 tad_offset;
1942 u32 rir_way;
1943 u32 mb, gb;
1944 u64 ch_addr, offset, limit = 0, prv = 0;
1945
1946
1947 /*
1948 * Step 0) Check if the address is at special memory ranges
1949 * The check bellow is probably enough to fill all cases where
1950 * the error is not inside a memory, except for the legacy
1951 * range (e. g. VGA addresses). It is unlikely, however, that the
1952 * memory controller would generate an error on that range.
1953 */
1954 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1955 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1956 return -EINVAL;
1957 }
1958 if (addr >= (u64)pvt->tohm) {
1959 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1960 return -EINVAL;
1961 }
1962
1963 /*
1964 * Step 1) Get socket
1965 */
1966 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1967 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1968 &reg);
1969
1970 if (!DRAM_RULE_ENABLE(reg))
1971 continue;
1972
1973 limit = pvt->info.sad_limit(reg);
1974 if (limit <= prv) {
1975 sprintf(msg, "Can't discover the memory socket");
1976 return -EINVAL;
1977 }
1978 if (addr <= limit)
1979 break;
1980 prv = limit;
1981 }
1982 if (n_sads == pvt->info.max_sad) {
1983 sprintf(msg, "Can't discover the memory socket");
1984 return -EINVAL;
1985 }
1986 dram_rule = reg;
1987 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1988 interleave_mode = pvt->info.interleave_mode(dram_rule);
1989
1990 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1991 &reg);
1992
1993 if (pvt->info.type == SANDY_BRIDGE) {
1994 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1995 for (sad_way = 0; sad_way < 8; sad_way++) {
1996 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1997 if (sad_way > 0 && sad_interl == pkg)
1998 break;
1999 sad_interleave[sad_way] = pkg;
2000 edac_dbg(0, "SAD interleave #%d: %d\n",
2001 sad_way, sad_interleave[sad_way]);
2002 }
2003 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
2004 pvt->sbridge_dev->mc,
2005 n_sads,
2006 addr,
2007 limit,
2008 sad_way + 7,
2009 !interleave_mode ? "" : "XOR[18:16]");
2010 if (interleave_mode)
2011 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
2012 else
2013 idx = (addr >> 6) & 7;
2014 switch (sad_way) {
2015 case 1:
2016 idx = 0;
2017 break;
2018 case 2:
2019 idx = idx & 1;
2020 break;
2021 case 4:
2022 idx = idx & 3;
2023 break;
2024 case 8:
2025 break;
2026 default:
2027 sprintf(msg, "Can't discover socket interleave");
2028 return -EINVAL;
2029 }
2030 *socket = sad_interleave[idx];
2031 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2032 idx, sad_way, *socket);
2033 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2034 int bits, a7mode = A7MODE(dram_rule);
2035
2036 if (a7mode) {
2037 /* A7 mode swaps P9 with P6 */
2038 bits = GET_BITFIELD(addr, 7, 8) << 1;
2039 bits |= GET_BITFIELD(addr, 9, 9);
2040 } else
2041 bits = GET_BITFIELD(addr, 6, 8);
2042
2043 if (interleave_mode == 0) {
2044 /* interleave mode will XOR {8,7,6} with {18,17,16} */
2045 idx = GET_BITFIELD(addr, 16, 18);
2046 idx ^= bits;
2047 } else
2048 idx = bits;
2049
2050 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2051 *socket = sad_pkg_socket(pkg);
2052 sad_ha = sad_pkg_ha(pkg);
2053 if (sad_ha)
2054 ch_add = 4;
2055
2056 if (a7mode) {
2057 /* MCChanShiftUpEnable */
2058 pci_read_config_dword(pvt->pci_ha0,
2059 HASWELL_HASYSDEFEATURE2, &reg);
2060 shiftup = GET_BITFIELD(reg, 22, 22);
2061 }
2062
2063 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2064 idx, *socket, sad_ha, shiftup);
2065 } else {
2066 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2067 idx = (addr >> 6) & 7;
2068 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2069 *socket = sad_pkg_socket(pkg);
2070 sad_ha = sad_pkg_ha(pkg);
2071 if (sad_ha)
2072 ch_add = 4;
2073 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2074 idx, *socket, sad_ha);
2075 }
2076
2077 *ha = sad_ha;
2078
2079 /*
2080 * Move to the proper node structure, in order to access the
2081 * right PCI registers
2082 */
2083 new_mci = get_mci_for_node_id(*socket);
2084 if (!new_mci) {
2085 sprintf(msg, "Struct for socket #%u wasn't initialized",
2086 *socket);
2087 return -EINVAL;
2088 }
2089 mci = new_mci;
2090 pvt = mci->pvt_info;
2091
2092 /*
2093 * Step 2) Get memory channel
2094 */
2095 prv = 0;
2096 if (pvt->info.type == SANDY_BRIDGE)
2097 pci_ha = pvt->pci_ha0;
2098 else {
2099 if (sad_ha)
2100 pci_ha = pvt->pci_ha1;
2101 else
2102 pci_ha = pvt->pci_ha0;
2103 }
2104 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
2105 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
2106 limit = TAD_LIMIT(reg);
2107 if (limit <= prv) {
2108 sprintf(msg, "Can't discover the memory channel");
2109 return -EINVAL;
2110 }
2111 if (addr <= limit)
2112 break;
2113 prv = limit;
2114 }
2115 if (n_tads == MAX_TAD) {
2116 sprintf(msg, "Can't discover the memory channel");
2117 return -EINVAL;
2118 }
2119
2120 ch_way = TAD_CH(reg) + 1;
2121 sck_way = TAD_SOCK(reg) + 1;
2122
2123 if (ch_way == 3)
2124 idx = addr >> 6;
2125 else
2126 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
2127 idx = idx % ch_way;
2128
2129 /*
2130 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2131 */
2132 switch (idx) {
2133 case 0:
2134 base_ch = TAD_TGT0(reg);
2135 break;
2136 case 1:
2137 base_ch = TAD_TGT1(reg);
2138 break;
2139 case 2:
2140 base_ch = TAD_TGT2(reg);
2141 break;
2142 case 3:
2143 base_ch = TAD_TGT3(reg);
2144 break;
2145 default:
2146 sprintf(msg, "Can't discover the TAD target");
2147 return -EINVAL;
2148 }
2149 *channel_mask = 1 << base_ch;
2150
2151 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2152 tad_ch_nilv_offset[n_tads],
2153 &tad_offset);
2154
2155 if (pvt->is_mirrored) {
2156 *channel_mask |= 1 << ((base_ch + 2) % 4);
2157 switch(ch_way) {
2158 case 2:
2159 case 4:
2160 sck_xch = 1 << sck_way * (ch_way >> 1);
2161 break;
2162 default:
2163 sprintf(msg, "Invalid mirror set. Can't decode addr");
2164 return -EINVAL;
2165 }
2166 } else
2167 sck_xch = (1 << sck_way) * ch_way;
2168
2169 if (pvt->is_lockstep)
2170 *channel_mask |= 1 << ((base_ch + 1) % 4);
2171
2172 offset = TAD_OFFSET(tad_offset);
2173
2174 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2175 n_tads,
2176 addr,
2177 limit,
2178 (u32)TAD_SOCK(reg),
2179 ch_way,
2180 offset,
2181 idx,
2182 base_ch,
2183 *channel_mask);
2184
2185 /* Calculate channel address */
2186 /* Remove the TAD offset */
2187
2188 if (offset > addr) {
2189 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2190 offset, addr);
2191 return -EINVAL;
2192 }
2193 addr -= offset;
2194 /* Store the low bits [0:6] of the addr */
2195 ch_addr = addr & 0x7f;
2196 /* Remove socket wayness and remove 6 bits */
2197 addr >>= 6;
2198 addr = div_u64(addr, sck_xch);
2199 #if 0
2200 /* Divide by channel way */
2201 addr = addr / ch_way;
2202 #endif
2203 /* Recover the last 6 bits */
2204 ch_addr |= addr << 6;
2205
2206 /*
2207 * Step 3) Decode rank
2208 */
2209 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
2210 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2211 rir_way_limit[n_rir],
2212 &reg);
2213
2214 if (!IS_RIR_VALID(reg))
2215 continue;
2216
2217 limit = pvt->info.rir_limit(reg);
2218 gb = div_u64_rem(limit >> 20, 1024, &mb);
2219 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2220 n_rir,
2221 gb, (mb*1000)/1024,
2222 limit,
2223 1 << RIR_WAY(reg));
2224 if (ch_addr <= limit)
2225 break;
2226 }
2227 if (n_rir == MAX_RIR_RANGES) {
2228 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2229 ch_addr);
2230 return -EINVAL;
2231 }
2232 rir_way = RIR_WAY(reg);
2233
2234 if (pvt->is_close_pg)
2235 idx = (ch_addr >> 6);
2236 else
2237 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
2238 idx %= 1 << rir_way;
2239
2240 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2241 rir_offset[n_rir][idx],
2242 &reg);
2243 *rank = RIR_RNK_TGT(reg);
2244
2245 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2246 n_rir,
2247 ch_addr,
2248 limit,
2249 rir_way,
2250 idx);
2251
2252 return 0;
2253 }
2254
2255 /****************************************************************************
2256 Device initialization routines: put/get, init/exit
2257 ****************************************************************************/
2258
2259 /*
2260 * sbridge_put_all_devices 'put' all the devices that we have
2261 * reserved via 'get'
2262 */
2263 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2264 {
2265 int i;
2266
2267 edac_dbg(0, "\n");
2268 for (i = 0; i < sbridge_dev->n_devs; i++) {
2269 struct pci_dev *pdev = sbridge_dev->pdev[i];
2270 if (!pdev)
2271 continue;
2272 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2273 pdev->bus->number,
2274 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
2275 pci_dev_put(pdev);
2276 }
2277 }
2278
2279 static void sbridge_put_all_devices(void)
2280 {
2281 struct sbridge_dev *sbridge_dev, *tmp;
2282
2283 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2284 sbridge_put_devices(sbridge_dev);
2285 free_sbridge_dev(sbridge_dev);
2286 }
2287 }
2288
2289 static int sbridge_get_onedevice(struct pci_dev **prev,
2290 u8 *num_mc,
2291 const struct pci_id_table *table,
2292 const unsigned devno,
2293 const int multi_bus)
2294 {
2295 struct sbridge_dev *sbridge_dev;
2296 const struct pci_id_descr *dev_descr = &table->descr[devno];
2297 struct pci_dev *pdev = NULL;
2298 u8 bus = 0;
2299
2300 sbridge_printk(KERN_DEBUG,
2301 "Seeking for: PCI ID %04x:%04x\n",
2302 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2303
2304 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2305 dev_descr->dev_id, *prev);
2306
2307 if (!pdev) {
2308 if (*prev) {
2309 *prev = pdev;
2310 return 0;
2311 }
2312
2313 if (dev_descr->optional)
2314 return 0;
2315
2316 /* if the HA wasn't found */
2317 if (devno == 0)
2318 return -ENODEV;
2319
2320 sbridge_printk(KERN_INFO,
2321 "Device not found: %04x:%04x\n",
2322 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2323
2324 /* End of list, leave */
2325 return -ENODEV;
2326 }
2327 bus = pdev->bus->number;
2328
2329 sbridge_dev = get_sbridge_dev(bus, multi_bus);
2330 if (!sbridge_dev) {
2331 sbridge_dev = alloc_sbridge_dev(bus, table);
2332 if (!sbridge_dev) {
2333 pci_dev_put(pdev);
2334 return -ENOMEM;
2335 }
2336 (*num_mc)++;
2337 }
2338
2339 if (sbridge_dev->pdev[devno]) {
2340 sbridge_printk(KERN_ERR,
2341 "Duplicated device for %04x:%04x\n",
2342 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2343 pci_dev_put(pdev);
2344 return -ENODEV;
2345 }
2346
2347 sbridge_dev->pdev[devno] = pdev;
2348
2349 /* Be sure that the device is enabled */
2350 if (unlikely(pci_enable_device(pdev) < 0)) {
2351 sbridge_printk(KERN_ERR,
2352 "Couldn't enable %04x:%04x\n",
2353 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2354 return -ENODEV;
2355 }
2356
2357 edac_dbg(0, "Detected %04x:%04x\n",
2358 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2359
2360 /*
2361 * As stated on drivers/pci/search.c, the reference count for
2362 * @from is always decremented if it is not %NULL. So, as we need
2363 * to get all devices up to null, we need to do a get for the device
2364 */
2365 pci_dev_get(pdev);
2366
2367 *prev = pdev;
2368
2369 return 0;
2370 }
2371
2372 /*
2373 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2374 * devices we want to reference for this driver.
2375 * @num_mc: pointer to the memory controllers count, to be incremented in case
2376 * of success.
2377 * @table: model specific table
2378 * @allow_dups: allow for multiple devices to exist with the same device id
2379 * (as implemented, this isn't expected to work correctly in the
2380 * multi-socket case).
2381 * @multi_bus: don't assume devices on different buses belong to different
2382 * memory controllers.
2383 *
2384 * returns 0 in case of success or error code
2385 */
2386 static int sbridge_get_all_devices_full(u8 *num_mc,
2387 const struct pci_id_table *table,
2388 int allow_dups,
2389 int multi_bus)
2390 {
2391 int i, rc;
2392 struct pci_dev *pdev = NULL;
2393
2394 while (table && table->descr) {
2395 for (i = 0; i < table->n_devs; i++) {
2396 if (!allow_dups || i == 0 ||
2397 table->descr[i].dev_id !=
2398 table->descr[i-1].dev_id) {
2399 pdev = NULL;
2400 }
2401 do {
2402 rc = sbridge_get_onedevice(&pdev, num_mc,
2403 table, i, multi_bus);
2404 if (rc < 0) {
2405 if (i == 0) {
2406 i = table->n_devs;
2407 break;
2408 }
2409 sbridge_put_all_devices();
2410 return -ENODEV;
2411 }
2412 } while (pdev && !allow_dups);
2413 }
2414 table++;
2415 }
2416
2417 return 0;
2418 }
2419
2420 #define sbridge_get_all_devices(num_mc, table) \
2421 sbridge_get_all_devices_full(num_mc, table, 0, 0)
2422 #define sbridge_get_all_devices_knl(num_mc, table) \
2423 sbridge_get_all_devices_full(num_mc, table, 1, 1)
2424
2425 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2426 struct sbridge_dev *sbridge_dev)
2427 {
2428 struct sbridge_pvt *pvt = mci->pvt_info;
2429 struct pci_dev *pdev;
2430 u8 saw_chan_mask = 0;
2431 int i;
2432
2433 for (i = 0; i < sbridge_dev->n_devs; i++) {
2434 pdev = sbridge_dev->pdev[i];
2435 if (!pdev)
2436 continue;
2437
2438 switch (pdev->device) {
2439 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2440 pvt->pci_sad0 = pdev;
2441 break;
2442 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2443 pvt->pci_sad1 = pdev;
2444 break;
2445 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2446 pvt->pci_br0 = pdev;
2447 break;
2448 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2449 pvt->pci_ha0 = pdev;
2450 break;
2451 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2452 pvt->pci_ta = pdev;
2453 break;
2454 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2455 pvt->pci_ras = pdev;
2456 break;
2457 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2458 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2459 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2460 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2461 {
2462 int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
2463 pvt->pci_tad[id] = pdev;
2464 saw_chan_mask |= 1 << id;
2465 }
2466 break;
2467 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2468 pvt->pci_ddrio = pdev;
2469 break;
2470 default:
2471 goto error;
2472 }
2473
2474 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2475 pdev->vendor, pdev->device,
2476 sbridge_dev->bus,
2477 pdev);
2478 }
2479
2480 /* Check if everything were registered */
2481 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
2482 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
2483 goto enodev;
2484
2485 if (saw_chan_mask != 0x0f)
2486 goto enodev;
2487 return 0;
2488
2489 enodev:
2490 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2491 return -ENODEV;
2492
2493 error:
2494 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2495 PCI_VENDOR_ID_INTEL, pdev->device);
2496 return -EINVAL;
2497 }
2498
2499 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2500 struct sbridge_dev *sbridge_dev)
2501 {
2502 struct sbridge_pvt *pvt = mci->pvt_info;
2503 struct pci_dev *pdev;
2504 u8 saw_chan_mask = 0;
2505 int i;
2506
2507 for (i = 0; i < sbridge_dev->n_devs; i++) {
2508 pdev = sbridge_dev->pdev[i];
2509 if (!pdev)
2510 continue;
2511
2512 switch (pdev->device) {
2513 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2514 pvt->pci_ha0 = pdev;
2515 break;
2516 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2517 pvt->pci_ta = pdev;
2518 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2519 pvt->pci_ras = pdev;
2520 break;
2521 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2522 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
2523 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2524 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
2525 {
2526 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
2527 pvt->pci_tad[id] = pdev;
2528 saw_chan_mask |= 1 << id;
2529 }
2530 break;
2531 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2532 pvt->pci_ddrio = pdev;
2533 break;
2534 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
2535 pvt->pci_ddrio = pdev;
2536 break;
2537 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2538 pvt->pci_sad0 = pdev;
2539 break;
2540 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2541 pvt->pci_br0 = pdev;
2542 break;
2543 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2544 pvt->pci_br1 = pdev;
2545 break;
2546 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2547 pvt->pci_ha1 = pdev;
2548 break;
2549 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2550 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
2551 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2552 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
2553 {
2554 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
2555 pvt->pci_tad[id] = pdev;
2556 saw_chan_mask |= 1 << id;
2557 }
2558 break;
2559 default:
2560 goto error;
2561 }
2562
2563 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2564 sbridge_dev->bus,
2565 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2566 pdev);
2567 }
2568
2569 /* Check if everything were registered */
2570 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
2571 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
2572 !pvt->pci_ta)
2573 goto enodev;
2574
2575 if (saw_chan_mask != 0x0f && /* -EN */
2576 saw_chan_mask != 0x33 && /* -EP */
2577 saw_chan_mask != 0xff) /* -EX */
2578 goto enodev;
2579 return 0;
2580
2581 enodev:
2582 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2583 return -ENODEV;
2584
2585 error:
2586 sbridge_printk(KERN_ERR,
2587 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2588 pdev->device);
2589 return -EINVAL;
2590 }
2591
2592 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2593 struct sbridge_dev *sbridge_dev)
2594 {
2595 struct sbridge_pvt *pvt = mci->pvt_info;
2596 struct pci_dev *pdev;
2597 u8 saw_chan_mask = 0;
2598 int i;
2599
2600 /* there's only one device per system; not tied to any bus */
2601 if (pvt->info.pci_vtd == NULL)
2602 /* result will be checked later */
2603 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2604 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2605 NULL);
2606
2607 for (i = 0; i < sbridge_dev->n_devs; i++) {
2608 pdev = sbridge_dev->pdev[i];
2609 if (!pdev)
2610 continue;
2611
2612 switch (pdev->device) {
2613 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2614 pvt->pci_sad0 = pdev;
2615 break;
2616 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2617 pvt->pci_sad1 = pdev;
2618 break;
2619 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2620 pvt->pci_ha0 = pdev;
2621 break;
2622 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2623 pvt->pci_ta = pdev;
2624 break;
2625 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
2626 pvt->pci_ras = pdev;
2627 break;
2628 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
2629 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
2630 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
2631 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
2632 {
2633 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
2634
2635 pvt->pci_tad[id] = pdev;
2636 saw_chan_mask |= 1 << id;
2637 }
2638 break;
2639 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2640 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2641 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2642 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2643 {
2644 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
2645
2646 pvt->pci_tad[id] = pdev;
2647 saw_chan_mask |= 1 << id;
2648 }
2649 break;
2650 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
2651 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2652 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2653 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2654 if (!pvt->pci_ddrio)
2655 pvt->pci_ddrio = pdev;
2656 break;
2657 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2658 pvt->pci_ha1 = pdev;
2659 break;
2660 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2661 pvt->pci_ha1_ta = pdev;
2662 break;
2663 default:
2664 break;
2665 }
2666
2667 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2668 sbridge_dev->bus,
2669 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2670 pdev);
2671 }
2672
2673 /* Check if everything were registered */
2674 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2675 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2676 goto enodev;
2677
2678 if (saw_chan_mask != 0x0f && /* -EN */
2679 saw_chan_mask != 0x33 && /* -EP */
2680 saw_chan_mask != 0xff) /* -EX */
2681 goto enodev;
2682 return 0;
2683
2684 enodev:
2685 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2686 return -ENODEV;
2687 }
2688
2689 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2690 struct sbridge_dev *sbridge_dev)
2691 {
2692 struct sbridge_pvt *pvt = mci->pvt_info;
2693 struct pci_dev *pdev;
2694 u8 saw_chan_mask = 0;
2695 int i;
2696
2697 /* there's only one device per system; not tied to any bus */
2698 if (pvt->info.pci_vtd == NULL)
2699 /* result will be checked later */
2700 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2701 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2702 NULL);
2703
2704 for (i = 0; i < sbridge_dev->n_devs; i++) {
2705 pdev = sbridge_dev->pdev[i];
2706 if (!pdev)
2707 continue;
2708
2709 switch (pdev->device) {
2710 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2711 pvt->pci_sad0 = pdev;
2712 break;
2713 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2714 pvt->pci_sad1 = pdev;
2715 break;
2716 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2717 pvt->pci_ha0 = pdev;
2718 break;
2719 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2720 pvt->pci_ta = pdev;
2721 break;
2722 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
2723 pvt->pci_ras = pdev;
2724 break;
2725 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
2726 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
2727 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
2728 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
2729 {
2730 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
2731 pvt->pci_tad[id] = pdev;
2732 saw_chan_mask |= 1 << id;
2733 }
2734 break;
2735 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2736 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2737 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2738 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2739 {
2740 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
2741 pvt->pci_tad[id] = pdev;
2742 saw_chan_mask |= 1 << id;
2743 }
2744 break;
2745 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2746 pvt->pci_ddrio = pdev;
2747 break;
2748 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2749 pvt->pci_ha1 = pdev;
2750 break;
2751 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2752 pvt->pci_ha1_ta = pdev;
2753 break;
2754 default:
2755 break;
2756 }
2757
2758 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2759 sbridge_dev->bus,
2760 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2761 pdev);
2762 }
2763
2764 /* Check if everything were registered */
2765 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2766 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2767 goto enodev;
2768
2769 if (saw_chan_mask != 0x0f && /* -EN */
2770 saw_chan_mask != 0x33 && /* -EP */
2771 saw_chan_mask != 0xff) /* -EX */
2772 goto enodev;
2773 return 0;
2774
2775 enodev:
2776 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2777 return -ENODEV;
2778 }
2779
2780 static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2781 struct sbridge_dev *sbridge_dev)
2782 {
2783 struct sbridge_pvt *pvt = mci->pvt_info;
2784 struct pci_dev *pdev;
2785 int dev, func;
2786
2787 int i;
2788 int devidx;
2789
2790 for (i = 0; i < sbridge_dev->n_devs; i++) {
2791 pdev = sbridge_dev->pdev[i];
2792 if (!pdev)
2793 continue;
2794
2795 /* Extract PCI device and function. */
2796 dev = (pdev->devfn >> 3) & 0x1f;
2797 func = pdev->devfn & 0x7;
2798
2799 switch (pdev->device) {
2800 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2801 if (dev == 8)
2802 pvt->knl.pci_mc0 = pdev;
2803 else if (dev == 9)
2804 pvt->knl.pci_mc1 = pdev;
2805 else {
2806 sbridge_printk(KERN_ERR,
2807 "Memory controller in unexpected place! (dev %d, fn %d)\n",
2808 dev, func);
2809 continue;
2810 }
2811 break;
2812
2813 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2814 pvt->pci_sad0 = pdev;
2815 break;
2816
2817 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2818 pvt->pci_sad1 = pdev;
2819 break;
2820
2821 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2822 /* There are one of these per tile, and range from
2823 * 1.14.0 to 1.18.5.
2824 */
2825 devidx = ((dev-14)*8)+func;
2826
2827 if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2828 sbridge_printk(KERN_ERR,
2829 "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2830 dev, func);
2831 continue;
2832 }
2833
2834 WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2835
2836 pvt->knl.pci_cha[devidx] = pdev;
2837 break;
2838
2839 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL:
2840 devidx = -1;
2841
2842 /*
2843 * MC0 channels 0-2 are device 9 function 2-4,
2844 * MC1 channels 3-5 are device 8 function 2-4.
2845 */
2846
2847 if (dev == 9)
2848 devidx = func-2;
2849 else if (dev == 8)
2850 devidx = 3 + (func-2);
2851
2852 if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2853 sbridge_printk(KERN_ERR,
2854 "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2855 dev, func);
2856 continue;
2857 }
2858
2859 WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2860 pvt->knl.pci_channel[devidx] = pdev;
2861 break;
2862
2863 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2864 pvt->knl.pci_mc_info = pdev;
2865 break;
2866
2867 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2868 pvt->pci_ta = pdev;
2869 break;
2870
2871 default:
2872 sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2873 pdev->device);
2874 break;
2875 }
2876 }
2877
2878 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 ||
2879 !pvt->pci_sad0 || !pvt->pci_sad1 ||
2880 !pvt->pci_ta) {
2881 goto enodev;
2882 }
2883
2884 for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2885 if (!pvt->knl.pci_channel[i]) {
2886 sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2887 goto enodev;
2888 }
2889 }
2890
2891 for (i = 0; i < KNL_MAX_CHAS; i++) {
2892 if (!pvt->knl.pci_cha[i]) {
2893 sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2894 goto enodev;
2895 }
2896 }
2897
2898 return 0;
2899
2900 enodev:
2901 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2902 return -ENODEV;
2903 }
2904
2905 /****************************************************************************
2906 Error check routines
2907 ****************************************************************************/
2908
2909 /*
2910 * While Sandy Bridge has error count registers, SMI BIOS read values from
2911 * and resets the counters. So, they are not reliable for the OS to read
2912 * from them. So, we have no option but to just trust on whatever MCE is
2913 * telling us about the errors.
2914 */
2915 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2916 const struct mce *m)
2917 {
2918 struct mem_ctl_info *new_mci;
2919 struct sbridge_pvt *pvt = mci->pvt_info;
2920 enum hw_event_mc_err_type tp_event;
2921 char *type, *optype, msg[256];
2922 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2923 bool overflow = GET_BITFIELD(m->status, 62, 62);
2924 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2925 bool recoverable;
2926 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2927 u32 mscod = GET_BITFIELD(m->status, 16, 31);
2928 u32 errcode = GET_BITFIELD(m->status, 0, 15);
2929 u32 channel = GET_BITFIELD(m->status, 0, 3);
2930 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2931 long channel_mask, first_channel;
2932 u8 rank, socket, ha;
2933 int rc, dimm;
2934 char *area_type = NULL;
2935
2936 if (pvt->info.type != SANDY_BRIDGE)
2937 recoverable = true;
2938 else
2939 recoverable = GET_BITFIELD(m->status, 56, 56);
2940
2941 if (uncorrected_error) {
2942 if (ripv) {
2943 type = "FATAL";
2944 tp_event = HW_EVENT_ERR_FATAL;
2945 } else {
2946 type = "NON_FATAL";
2947 tp_event = HW_EVENT_ERR_UNCORRECTED;
2948 }
2949 } else {
2950 type = "CORRECTED";
2951 tp_event = HW_EVENT_ERR_CORRECTED;
2952 }
2953
2954 /*
2955 * According with Table 15-9 of the Intel Architecture spec vol 3A,
2956 * memory errors should fit in this mask:
2957 * 000f 0000 1mmm cccc (binary)
2958 * where:
2959 * f = Correction Report Filtering Bit. If 1, subsequent errors
2960 * won't be shown
2961 * mmm = error type
2962 * cccc = channel
2963 * If the mask doesn't match, report an error to the parsing logic
2964 */
2965 if (! ((errcode & 0xef80) == 0x80)) {
2966 optype = "Can't parse: it is not a mem";
2967 } else {
2968 switch (optypenum) {
2969 case 0:
2970 optype = "generic undef request error";
2971 break;
2972 case 1:
2973 optype = "memory read error";
2974 break;
2975 case 2:
2976 optype = "memory write error";
2977 break;
2978 case 3:
2979 optype = "addr/cmd error";
2980 break;
2981 case 4:
2982 optype = "memory scrubbing error";
2983 break;
2984 default:
2985 optype = "reserved";
2986 break;
2987 }
2988 }
2989
2990 /* Only decode errors with an valid address (ADDRV) */
2991 if (!GET_BITFIELD(m->status, 58, 58))
2992 return;
2993
2994 if (pvt->info.type == KNIGHTS_LANDING) {
2995 if (channel == 14) {
2996 edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
2997 overflow ? " OVERFLOW" : "",
2998 (uncorrected_error && recoverable)
2999 ? " recoverable" : "",
3000 mscod, errcode,
3001 m->bank);
3002 } else {
3003 char A = *("A");
3004
3005 channel = knl_channel_remap(channel);
3006 channel_mask = 1 << channel;
3007 snprintf(msg, sizeof(msg),
3008 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3009 overflow ? " OVERFLOW" : "",
3010 (uncorrected_error && recoverable)
3011 ? " recoverable" : " ",
3012 mscod, errcode, channel, A + channel);
3013 edac_mc_handle_error(tp_event, mci, core_err_cnt,
3014 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3015 channel, 0, -1,
3016 optype, msg);
3017 }
3018 return;
3019 } else {
3020 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
3021 &channel_mask, &rank, &area_type, msg);
3022 }
3023
3024 if (rc < 0)
3025 goto err_parsing;
3026 new_mci = get_mci_for_node_id(socket);
3027 if (!new_mci) {
3028 strcpy(msg, "Error: socket got corrupted!");
3029 goto err_parsing;
3030 }
3031 mci = new_mci;
3032 pvt = mci->pvt_info;
3033
3034 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
3035
3036 if (rank < 4)
3037 dimm = 0;
3038 else if (rank < 8)
3039 dimm = 1;
3040 else
3041 dimm = 2;
3042
3043
3044 /*
3045 * FIXME: On some memory configurations (mirror, lockstep), the
3046 * Memory Controller can't point the error to a single DIMM. The
3047 * EDAC core should be handling the channel mask, in order to point
3048 * to the group of dimm's where the error may be happening.
3049 */
3050 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
3051 channel = first_channel;
3052
3053 snprintf(msg, sizeof(msg),
3054 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
3055 overflow ? " OVERFLOW" : "",
3056 (uncorrected_error && recoverable) ? " recoverable" : "",
3057 area_type,
3058 mscod, errcode,
3059 socket, ha,
3060 channel_mask,
3061 rank);
3062
3063 edac_dbg(0, "%s\n", msg);
3064
3065 /* FIXME: need support for channel mask */
3066
3067 if (channel == CHANNEL_UNSPECIFIED)
3068 channel = -1;
3069
3070 /* Call the helper to output message */
3071 edac_mc_handle_error(tp_event, mci, core_err_cnt,
3072 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3073 4*ha+channel, dimm, -1,
3074 optype, msg);
3075 return;
3076 err_parsing:
3077 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
3078 -1, -1, -1,
3079 msg, "");
3080
3081 }
3082
3083 /*
3084 * sbridge_check_error Retrieve and process errors reported by the
3085 * hardware. Called by the Core module.
3086 */
3087 static void sbridge_check_error(struct mem_ctl_info *mci)
3088 {
3089 struct sbridge_pvt *pvt = mci->pvt_info;
3090 int i;
3091 unsigned count = 0;
3092 struct mce *m;
3093
3094 /*
3095 * MCE first step: Copy all mce errors into a temporary buffer
3096 * We use a double buffering here, to reduce the risk of
3097 * loosing an error.
3098 */
3099 smp_rmb();
3100 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
3101 % MCE_LOG_LEN;
3102 if (!count)
3103 return;
3104
3105 m = pvt->mce_outentry;
3106 if (pvt->mce_in + count > MCE_LOG_LEN) {
3107 unsigned l = MCE_LOG_LEN - pvt->mce_in;
3108
3109 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
3110 smp_wmb();
3111 pvt->mce_in = 0;
3112 count -= l;
3113 m += l;
3114 }
3115 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
3116 smp_wmb();
3117 pvt->mce_in += count;
3118
3119 smp_rmb();
3120 if (pvt->mce_overrun) {
3121 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
3122 pvt->mce_overrun);
3123 smp_wmb();
3124 pvt->mce_overrun = 0;
3125 }
3126
3127 /*
3128 * MCE second step: parse errors and display
3129 */
3130 for (i = 0; i < count; i++)
3131 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
3132 }
3133
3134 /*
3135 * sbridge_mce_check_error Replicates mcelog routine to get errors
3136 * This routine simply queues mcelog errors, and
3137 * return. The error itself should be handled later
3138 * by sbridge_check_error.
3139 * WARNING: As this routine should be called at NMI time, extra care should
3140 * be taken to avoid deadlocks, and to be as fast as possible.
3141 */
3142 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3143 void *data)
3144 {
3145 struct mce *mce = (struct mce *)data;
3146 struct mem_ctl_info *mci;
3147 struct sbridge_pvt *pvt;
3148 char *type;
3149
3150 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3151 return NOTIFY_DONE;
3152
3153 mci = get_mci_for_node_id(mce->socketid);
3154 if (!mci)
3155 return NOTIFY_BAD;
3156 pvt = mci->pvt_info;
3157
3158 /*
3159 * Just let mcelog handle it if the error is
3160 * outside the memory controller. A memory error
3161 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3162 * bit 12 has an special meaning.
3163 */
3164 if ((mce->status & 0xefff) >> 7 != 1)
3165 return NOTIFY_DONE;
3166
3167 if (mce->mcgstatus & MCG_STATUS_MCIP)
3168 type = "Exception";
3169 else
3170 type = "Event";
3171
3172 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
3173
3174 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3175 "Bank %d: %016Lx\n", mce->extcpu, type,
3176 mce->mcgstatus, mce->bank, mce->status);
3177 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3178 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3179 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
3180
3181 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3182 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3183 mce->time, mce->socketid, mce->apicid);
3184
3185 smp_rmb();
3186 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
3187 smp_wmb();
3188 pvt->mce_overrun++;
3189 return NOTIFY_DONE;
3190 }
3191
3192 /* Copy memory error at the ringbuffer */
3193 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
3194 smp_wmb();
3195 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
3196
3197 /* Handle fatal errors immediately */
3198 if (mce->mcgstatus & 1)
3199 sbridge_check_error(mci);
3200
3201 /* Advice mcelog that the error were handled */
3202 return NOTIFY_STOP;
3203 }
3204
3205 static struct notifier_block sbridge_mce_dec = {
3206 .notifier_call = sbridge_mce_check_error,
3207 };
3208
3209 /****************************************************************************
3210 EDAC register/unregister logic
3211 ****************************************************************************/
3212
3213 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3214 {
3215 struct mem_ctl_info *mci = sbridge_dev->mci;
3216 struct sbridge_pvt *pvt;
3217
3218 if (unlikely(!mci || !mci->pvt_info)) {
3219 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
3220
3221 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3222 return;
3223 }
3224
3225 pvt = mci->pvt_info;
3226
3227 edac_dbg(0, "MC: mci = %p, dev = %p\n",
3228 mci, &sbridge_dev->pdev[0]->dev);
3229
3230 /* Remove MC sysfs nodes */
3231 edac_mc_del_mc(mci->pdev);
3232
3233 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
3234 kfree(mci->ctl_name);
3235 edac_mc_free(mci);
3236 sbridge_dev->mci = NULL;
3237 }
3238
3239 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
3240 {
3241 struct mem_ctl_info *mci;
3242 struct edac_mc_layer layers[2];
3243 struct sbridge_pvt *pvt;
3244 struct pci_dev *pdev = sbridge_dev->pdev[0];
3245 int rc;
3246
3247 /* Check the number of active and not disabled channels */
3248 rc = check_if_ecc_is_active(sbridge_dev->bus, type);
3249 if (unlikely(rc < 0))
3250 return rc;
3251
3252 /* allocate a new MC control structure */
3253 layers[0].type = EDAC_MC_LAYER_CHANNEL;
3254 layers[0].size = type == KNIGHTS_LANDING ?
3255 KNL_MAX_CHANNELS : NUM_CHANNELS;
3256 layers[0].is_virt_csrow = false;
3257 layers[1].type = EDAC_MC_LAYER_SLOT;
3258 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3259 layers[1].is_virt_csrow = true;
3260 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3261 sizeof(*pvt));
3262
3263 if (unlikely(!mci))
3264 return -ENOMEM;
3265
3266 edac_dbg(0, "MC: mci = %p, dev = %p\n",
3267 mci, &pdev->dev);
3268
3269 pvt = mci->pvt_info;
3270 memset(pvt, 0, sizeof(*pvt));
3271
3272 /* Associate sbridge_dev and mci for future usage */
3273 pvt->sbridge_dev = sbridge_dev;
3274 sbridge_dev->mci = mci;
3275
3276 mci->mtype_cap = type == KNIGHTS_LANDING ?
3277 MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
3278 mci->edac_ctl_cap = EDAC_FLAG_NONE;
3279 mci->edac_cap = EDAC_FLAG_NONE;
3280 mci->mod_name = "sbridge_edac.c";
3281 mci->mod_ver = SBRIDGE_REVISION;
3282 mci->dev_name = pci_name(pdev);
3283 mci->ctl_page_to_phys = NULL;
3284
3285 /* Set the function pointer to an actual operation function */
3286 mci->edac_check = sbridge_check_error;
3287
3288 pvt->info.type = type;
3289 switch (type) {
3290 case IVY_BRIDGE:
3291 pvt->info.rankcfgr = IB_RANK_CFG_A;
3292 pvt->info.get_tolm = ibridge_get_tolm;
3293 pvt->info.get_tohm = ibridge_get_tohm;
3294 pvt->info.dram_rule = ibridge_dram_rule;
3295 pvt->info.get_memory_type = get_memory_type;
3296 pvt->info.get_node_id = get_node_id;
3297 pvt->info.rir_limit = rir_limit;
3298 pvt->info.sad_limit = sad_limit;
3299 pvt->info.interleave_mode = interleave_mode;
3300 pvt->info.show_interleave_mode = show_interleave_mode;
3301 pvt->info.dram_attr = dram_attr;
3302 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3303 pvt->info.interleave_list = ibridge_interleave_list;
3304 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3305 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3306 pvt->info.get_width = ibridge_get_width;
3307 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
3308
3309 /* Store pci devices at mci for faster access */
3310 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3311 if (unlikely(rc < 0))
3312 goto fail0;
3313 break;
3314 case SANDY_BRIDGE:
3315 pvt->info.rankcfgr = SB_RANK_CFG_A;
3316 pvt->info.get_tolm = sbridge_get_tolm;
3317 pvt->info.get_tohm = sbridge_get_tohm;
3318 pvt->info.dram_rule = sbridge_dram_rule;
3319 pvt->info.get_memory_type = get_memory_type;
3320 pvt->info.get_node_id = get_node_id;
3321 pvt->info.rir_limit = rir_limit;
3322 pvt->info.sad_limit = sad_limit;
3323 pvt->info.interleave_mode = interleave_mode;
3324 pvt->info.show_interleave_mode = show_interleave_mode;
3325 pvt->info.dram_attr = dram_attr;
3326 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3327 pvt->info.interleave_list = sbridge_interleave_list;
3328 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
3329 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3330 pvt->info.get_width = sbridge_get_width;
3331 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
3332
3333 /* Store pci devices at mci for faster access */
3334 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3335 if (unlikely(rc < 0))
3336 goto fail0;
3337 break;
3338 case HASWELL:
3339 /* rankcfgr isn't used */
3340 pvt->info.get_tolm = haswell_get_tolm;
3341 pvt->info.get_tohm = haswell_get_tohm;
3342 pvt->info.dram_rule = ibridge_dram_rule;
3343 pvt->info.get_memory_type = haswell_get_memory_type;
3344 pvt->info.get_node_id = haswell_get_node_id;
3345 pvt->info.rir_limit = haswell_rir_limit;
3346 pvt->info.sad_limit = sad_limit;
3347 pvt->info.interleave_mode = interleave_mode;
3348 pvt->info.show_interleave_mode = show_interleave_mode;
3349 pvt->info.dram_attr = dram_attr;
3350 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3351 pvt->info.interleave_list = ibridge_interleave_list;
3352 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3353 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3354 pvt->info.get_width = ibridge_get_width;
3355 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
3356
3357 /* Store pci devices at mci for faster access */
3358 rc = haswell_mci_bind_devs(mci, sbridge_dev);
3359 if (unlikely(rc < 0))
3360 goto fail0;
3361 break;
3362 case BROADWELL:
3363 /* rankcfgr isn't used */
3364 pvt->info.get_tolm = haswell_get_tolm;
3365 pvt->info.get_tohm = haswell_get_tohm;
3366 pvt->info.dram_rule = ibridge_dram_rule;
3367 pvt->info.get_memory_type = haswell_get_memory_type;
3368 pvt->info.get_node_id = haswell_get_node_id;
3369 pvt->info.rir_limit = haswell_rir_limit;
3370 pvt->info.sad_limit = sad_limit;
3371 pvt->info.interleave_mode = interleave_mode;
3372 pvt->info.show_interleave_mode = show_interleave_mode;
3373 pvt->info.dram_attr = dram_attr;
3374 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3375 pvt->info.interleave_list = ibridge_interleave_list;
3376 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3377 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3378 pvt->info.get_width = broadwell_get_width;
3379 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
3380
3381 /* Store pci devices at mci for faster access */
3382 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3383 if (unlikely(rc < 0))
3384 goto fail0;
3385 break;
3386 case KNIGHTS_LANDING:
3387 /* pvt->info.rankcfgr == ??? */
3388 pvt->info.get_tolm = knl_get_tolm;
3389 pvt->info.get_tohm = knl_get_tohm;
3390 pvt->info.dram_rule = knl_dram_rule;
3391 pvt->info.get_memory_type = knl_get_memory_type;
3392 pvt->info.get_node_id = knl_get_node_id;
3393 pvt->info.rir_limit = NULL;
3394 pvt->info.sad_limit = knl_sad_limit;
3395 pvt->info.interleave_mode = knl_interleave_mode;
3396 pvt->info.show_interleave_mode = knl_show_interleave_mode;
3397 pvt->info.dram_attr = dram_attr_knl;
3398 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3399 pvt->info.interleave_list = knl_interleave_list;
3400 pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list);
3401 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3402 pvt->info.get_width = knl_get_width;
3403 mci->ctl_name = kasprintf(GFP_KERNEL,
3404 "Knights Landing Socket#%d", mci->mc_idx);
3405
3406 rc = knl_mci_bind_devs(mci, sbridge_dev);
3407 if (unlikely(rc < 0))
3408 goto fail0;
3409 break;
3410 }
3411
3412 /* Get dimm basic config and the memory layout */
3413 get_dimm_config(mci);
3414 get_memory_layout(mci);
3415
3416 /* record ptr to the generic device */
3417 mci->pdev = &pdev->dev;
3418
3419 /* add this new MC control structure to EDAC's list of MCs */
3420 if (unlikely(edac_mc_add_mc(mci))) {
3421 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
3422 rc = -EINVAL;
3423 goto fail0;
3424 }
3425
3426 return 0;
3427
3428 fail0:
3429 kfree(mci->ctl_name);
3430 edac_mc_free(mci);
3431 sbridge_dev->mci = NULL;
3432 return rc;
3433 }
3434
3435 /*
3436 * sbridge_probe Probe for ONE instance of device to see if it is
3437 * present.
3438 * return:
3439 * 0 for FOUND a device
3440 * < 0 for error code
3441 */
3442
3443 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3444 {
3445 int rc = -ENODEV;
3446 u8 mc, num_mc = 0;
3447 struct sbridge_dev *sbridge_dev;
3448 enum type type = SANDY_BRIDGE;
3449
3450 /* get the pci devices we want to reserve for our use */
3451 mutex_lock(&sbridge_edac_lock);
3452
3453 /*
3454 * All memory controllers are allocated at the first pass.
3455 */
3456 if (unlikely(probed >= 1)) {
3457 mutex_unlock(&sbridge_edac_lock);
3458 return -ENODEV;
3459 }
3460 probed++;
3461
3462 switch (pdev->device) {
3463 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
3464 rc = sbridge_get_all_devices(&num_mc,
3465 pci_dev_descr_ibridge_table);
3466 type = IVY_BRIDGE;
3467 break;
3468 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
3469 rc = sbridge_get_all_devices(&num_mc,
3470 pci_dev_descr_sbridge_table);
3471 type = SANDY_BRIDGE;
3472 break;
3473 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
3474 rc = sbridge_get_all_devices(&num_mc,
3475 pci_dev_descr_haswell_table);
3476 type = HASWELL;
3477 break;
3478 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
3479 rc = sbridge_get_all_devices(&num_mc,
3480 pci_dev_descr_broadwell_table);
3481 type = BROADWELL;
3482 break;
3483 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
3484 rc = sbridge_get_all_devices_knl(&num_mc,
3485 pci_dev_descr_knl_table);
3486 type = KNIGHTS_LANDING;
3487 break;
3488 }
3489 if (unlikely(rc < 0)) {
3490 edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
3491 goto fail0;
3492 }
3493
3494 mc = 0;
3495
3496 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
3497 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3498 mc, mc + 1, num_mc);
3499
3500 sbridge_dev->mc = mc++;
3501 rc = sbridge_register_mci(sbridge_dev, type);
3502 if (unlikely(rc < 0))
3503 goto fail1;
3504 }
3505
3506 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
3507
3508 mutex_unlock(&sbridge_edac_lock);
3509 return 0;
3510
3511 fail1:
3512 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3513 sbridge_unregister_mci(sbridge_dev);
3514
3515 sbridge_put_all_devices();
3516 fail0:
3517 mutex_unlock(&sbridge_edac_lock);
3518 return rc;
3519 }
3520
3521 /*
3522 * sbridge_remove destructor for one instance of device
3523 *
3524 */
3525 static void sbridge_remove(struct pci_dev *pdev)
3526 {
3527 struct sbridge_dev *sbridge_dev;
3528
3529 edac_dbg(0, "\n");
3530
3531 /*
3532 * we have a trouble here: pdev value for removal will be wrong, since
3533 * it will point to the X58 register used to detect that the machine
3534 * is a Nehalem or upper design. However, due to the way several PCI
3535 * devices are grouped together to provide MC functionality, we need
3536 * to use a different method for releasing the devices
3537 */
3538
3539 mutex_lock(&sbridge_edac_lock);
3540
3541 if (unlikely(!probed)) {
3542 mutex_unlock(&sbridge_edac_lock);
3543 return;
3544 }
3545
3546 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3547 sbridge_unregister_mci(sbridge_dev);
3548
3549 /* Release PCI resources */
3550 sbridge_put_all_devices();
3551
3552 probed--;
3553
3554 mutex_unlock(&sbridge_edac_lock);
3555 }
3556
3557 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
3558
3559 /*
3560 * sbridge_driver pci_driver structure for this module
3561 *
3562 */
3563 static struct pci_driver sbridge_driver = {
3564 .name = "sbridge_edac",
3565 .probe = sbridge_probe,
3566 .remove = sbridge_remove,
3567 .id_table = sbridge_pci_tbl,
3568 };
3569
3570 /*
3571 * sbridge_init Module entry function
3572 * Try to initialize this module for its devices
3573 */
3574 static int __init sbridge_init(void)
3575 {
3576 int pci_rc;
3577
3578 edac_dbg(2, "\n");
3579
3580 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
3581 opstate_init();
3582
3583 pci_rc = pci_register_driver(&sbridge_driver);
3584 if (pci_rc >= 0) {
3585 mce_register_decode_chain(&sbridge_mce_dec);
3586 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3587 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
3588 return 0;
3589 }
3590
3591 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
3592 pci_rc);
3593
3594 return pci_rc;
3595 }
3596
3597 /*
3598 * sbridge_exit() Module exit function
3599 * Unregister the driver
3600 */
3601 static void __exit sbridge_exit(void)
3602 {
3603 edac_dbg(2, "\n");
3604 pci_unregister_driver(&sbridge_driver);
3605 mce_unregister_decode_chain(&sbridge_mce_dec);
3606 }
3607
3608 module_init(sbridge_init);
3609 module_exit(sbridge_exit);
3610
3611 module_param(edac_op_state, int, 0444);
3612 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3613
3614 MODULE_LICENSE("GPL");
3615 MODULE_AUTHOR("Mauro Carvalho Chehab");
3616 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
3617 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
3618 SBRIDGE_REVISION);
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