2 * Cavium ThunderX memory controller kernel module
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/edac.h>
15 #include <linux/interrupt.h>
16 #include <linux/string.h>
17 #include <linux/stop_machine.h>
18 #include <linux/delay.h>
19 #include <linux/sizes.h>
20 #include <linux/atomic.h>
21 #include <linux/bitfield.h>
22 #include <linux/circ_buf.h>
26 #include "edac_module.h"
28 #define phys_to_pfn(phys) (PFN_DOWN(phys))
30 #define THUNDERX_NODE GENMASK(45, 44)
38 #define MAX_SYNDROME_REGS 4
40 struct error_syndrome
{
41 u64 reg
[MAX_SYNDROME_REGS
];
50 static void decode_register(char *str
, size_t size
,
51 const struct error_descr
*descr
,
56 while (descr
->type
&& descr
->mask
&& descr
->descr
) {
57 if (reg
& descr
->mask
) {
58 ret
= snprintf(str
, size
, "\n\t%s, %s",
59 descr
->type
== ERR_CORRECTED
?
60 "Corrected" : "Uncorrected",
69 static unsigned long get_bits(unsigned long data
, int pos
, int width
)
71 return (data
>> pos
) & ((1 << width
) - 1);
74 #define L2C_CTL 0x87E080800000
75 #define L2C_CTL_DISIDXALIAS BIT(0)
77 #define PCI_DEVICE_ID_THUNDER_LMC 0xa022
80 #define LMC_FADR_FDIMM(x) ((x >> 37) & 0x1)
81 #define LMC_FADR_FBUNK(x) ((x >> 36) & 0x1)
82 #define LMC_FADR_FBANK(x) ((x >> 32) & 0xf)
83 #define LMC_FADR_FROW(x) ((x >> 14) & 0xffff)
84 #define LMC_FADR_FCOL(x) ((x >> 0) & 0x1fff)
86 #define LMC_NXM_FADR 0x28
87 #define LMC_ECC_SYND 0x38
89 #define LMC_ECC_PARITY_TEST 0x108
91 #define LMC_INT_W1S 0x150
93 #define LMC_INT_ENA_W1C 0x158
94 #define LMC_INT_ENA_W1S 0x160
96 #define LMC_CONFIG 0x188
98 #define LMC_CONFIG_BG2 BIT(62)
99 #define LMC_CONFIG_RANK_ENA BIT(42)
100 #define LMC_CONFIG_PBANK_LSB(x) (((x) >> 5) & 0xF)
101 #define LMC_CONFIG_ROW_LSB(x) (((x) >> 2) & 0x7)
103 #define LMC_CONTROL 0x190
104 #define LMC_CONTROL_XOR_BANK BIT(16)
106 #define LMC_INT 0x1F0
108 #define LMC_INT_DDR_ERR BIT(11)
109 #define LMC_INT_DED_ERR (0xFUL << 5)
110 #define LMC_INT_SEC_ERR (0xFUL << 1)
111 #define LMC_INT_NXM_WR_MASK BIT(0)
113 #define LMC_DDR_PLL_CTL 0x258
114 #define LMC_DDR_PLL_CTL_DDR4 BIT(29)
116 #define LMC_FADR_SCRAMBLED 0x330
118 #define LMC_INT_UE (LMC_INT_DDR_ERR | LMC_INT_DED_ERR | \
121 #define LMC_INT_CE (LMC_INT_SEC_ERR)
123 static const struct error_descr lmc_errors
[] = {
125 .type
= ERR_CORRECTED
,
126 .mask
= LMC_INT_SEC_ERR
,
127 .descr
= "Single-bit ECC error",
130 .type
= ERR_UNCORRECTED
,
131 .mask
= LMC_INT_DDR_ERR
,
132 .descr
= "DDR chip error",
135 .type
= ERR_UNCORRECTED
,
136 .mask
= LMC_INT_DED_ERR
,
137 .descr
= "Double-bit ECC error",
140 .type
= ERR_UNCORRECTED
,
141 .mask
= LMC_INT_NXM_WR_MASK
,
142 .descr
= "Non-existent memory write",
147 #define LMC_INT_EN_DDR_ERROR_ALERT_ENA BIT(5)
148 #define LMC_INT_EN_DLCRAM_DED_ERR BIT(4)
149 #define LMC_INT_EN_DLCRAM_SEC_ERR BIT(3)
150 #define LMC_INT_INTR_DED_ENA BIT(2)
151 #define LMC_INT_INTR_SEC_ENA BIT(1)
152 #define LMC_INT_INTR_NXM_WR_ENA BIT(0)
154 #define LMC_INT_ENA_ALL GENMASK(5, 0)
156 #define LMC_DDR_PLL_CTL 0x258
157 #define LMC_DDR_PLL_CTL_DDR4 BIT(29)
159 #define LMC_CONTROL 0x190
160 #define LMC_CONTROL_RDIMM BIT(0)
162 #define LMC_SCRAM_FADR 0x330
164 #define LMC_CHAR_MASK0 0x228
165 #define LMC_CHAR_MASK2 0x238
167 #define RING_ENTRIES 8
169 struct debugfs_entry
{
172 const struct file_operations fops
;
183 struct thunderx_lmc
{
185 struct pci_dev
*pdev
;
186 struct msix_entry msix_ent
;
209 struct lmc_err_ctx err_ctx
[RING_ENTRIES
];
210 unsigned long ring_head
;
211 unsigned long ring_tail
;
214 #define ring_pos(pos, size) ((pos) & (size - 1))
216 #define DEBUGFS_STRUCT(_name, _mode, _write, _read) \
217 static struct debugfs_entry debugfs_##_name = { \
218 .name = __stringify(_name), \
219 .mode = VERIFY_OCTAL_PERMISSIONS(_mode), \
221 .open = simple_open, \
224 .llseek = generic_file_llseek, \
228 #define DEBUGFS_FIELD_ATTR(_type, _field) \
229 static ssize_t thunderx_##_type##_##_field##_read(struct file *file, \
231 size_t count, loff_t *ppos) \
233 struct thunderx_##_type *pdata = file->private_data; \
236 snprintf(buf, count, "0x%016llx", pdata->_field); \
237 return simple_read_from_buffer(data, count, ppos, \
241 static ssize_t thunderx_##_type##_##_field##_write(struct file *file, \
242 const char __user *data, \
243 size_t count, loff_t *ppos) \
245 struct thunderx_##_type *pdata = file->private_data; \
248 res = kstrtoull_from_user(data, count, 0, &pdata->_field); \
250 return res ? res : count; \
253 DEBUGFS_STRUCT(_field, 0600, \
254 thunderx_##_type##_##_field##_write, \
255 thunderx_##_type##_##_field##_read) \
257 #define DEBUGFS_REG_ATTR(_type, _name, _reg) \
258 static ssize_t thunderx_##_type##_##_name##_read(struct file *file, \
260 size_t count, loff_t *ppos) \
262 struct thunderx_##_type *pdata = file->private_data; \
265 sprintf(buf, "0x%016llx", readq(pdata->regs + _reg)); \
266 return simple_read_from_buffer(data, count, ppos, \
270 static ssize_t thunderx_##_type##_##_name##_write(struct file *file, \
271 const char __user *data, \
272 size_t count, loff_t *ppos) \
274 struct thunderx_##_type *pdata = file->private_data; \
278 res = kstrtoull_from_user(data, count, 0, &val); \
281 writeq(val, pdata->regs + _reg); \
288 DEBUGFS_STRUCT(_name, 0600, \
289 thunderx_##_type##_##_name##_write, \
290 thunderx_##_type##_##_name##_read)
292 #define LMC_DEBUGFS_ENT(_field) DEBUGFS_FIELD_ATTR(lmc, _field)
295 * To get an ECC error injected, the following steps are needed:
296 * - Setup the ECC injection by writing the appropriate parameters:
297 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask0
298 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask2
299 * echo 0x802 > /sys/kernel/debug/<device number>/ecc_parity_test
300 * - Do the actual injection:
301 * echo 1 > /sys/kernel/debug/<device number>/inject_ecc
303 static ssize_t
thunderx_lmc_inject_int_write(struct file
*file
,
304 const char __user
*data
,
305 size_t count
, loff_t
*ppos
)
307 struct thunderx_lmc
*lmc
= file
->private_data
;
311 res
= kstrtoull_from_user(data
, count
, 0, &val
);
314 /* Trigger the interrupt */
315 writeq(val
, lmc
->regs
+ LMC_INT_W1S
);
322 static ssize_t
thunderx_lmc_int_read(struct file
*file
,
324 size_t count
, loff_t
*ppos
)
326 struct thunderx_lmc
*lmc
= file
->private_data
;
328 u64 lmc_int
= readq(lmc
->regs
+ LMC_INT
);
330 snprintf(buf
, sizeof(buf
), "0x%016llx", lmc_int
);
331 return simple_read_from_buffer(data
, count
, ppos
, buf
, sizeof(buf
));
334 #define TEST_PATTERN 0xa5
336 static int inject_ecc_fn(void *arg
)
338 struct thunderx_lmc
*lmc
= arg
;
339 uintptr_t addr
, phys
;
340 unsigned int cline_size
= cache_line_size();
341 const unsigned int lines
= PAGE_SIZE
/ cline_size
;
342 unsigned int i
, cl_idx
;
344 addr
= (uintptr_t)page_address(lmc
->mem
);
345 phys
= (uintptr_t)page_to_phys(lmc
->mem
);
347 cl_idx
= (phys
& 0x7f) >> 4;
348 lmc
->parity_test
&= ~(7ULL << 8);
349 lmc
->parity_test
|= (cl_idx
<< 8);
351 writeq(lmc
->mask0
, lmc
->regs
+ LMC_CHAR_MASK0
);
352 writeq(lmc
->mask2
, lmc
->regs
+ LMC_CHAR_MASK2
);
353 writeq(lmc
->parity_test
, lmc
->regs
+ LMC_ECC_PARITY_TEST
);
355 readq(lmc
->regs
+ LMC_CHAR_MASK0
);
356 readq(lmc
->regs
+ LMC_CHAR_MASK2
);
357 readq(lmc
->regs
+ LMC_ECC_PARITY_TEST
);
359 for (i
= 0; i
< lines
; i
++) {
360 memset((void *)addr
, TEST_PATTERN
, cline_size
);
364 * Flush L1 cachelines to the PoC (L2).
365 * This will cause cacheline eviction to the L2.
367 asm volatile("dc civac, %0\n"
369 : : "r"(addr
+ i
* cline_size
));
372 for (i
= 0; i
< lines
; i
++) {
374 * Flush L2 cachelines to the DRAM.
375 * This will cause cacheline eviction to the DRAM
376 * and ECC corruption according to the masks set.
378 __asm__
volatile("sys #0,c11,C1,#2, %0\n"
379 : : "r"(phys
+ i
* cline_size
));
382 for (i
= 0; i
< lines
; i
++) {
384 * Invalidate L2 cachelines.
385 * The subsequent load will cause cacheline fetch
386 * from the DRAM and an error interrupt
388 __asm__
volatile("sys #0,c11,C1,#1, %0"
389 : : "r"(phys
+ i
* cline_size
));
392 for (i
= 0; i
< lines
; i
++) {
394 * Invalidate L1 cachelines.
395 * The subsequent load will cause cacheline fetch
396 * from the L2 and/or DRAM
398 asm volatile("dc ivac, %0\n"
400 : : "r"(addr
+ i
* cline_size
));
406 static ssize_t
thunderx_lmc_inject_ecc_write(struct file
*file
,
407 const char __user
*data
,
408 size_t count
, loff_t
*ppos
)
410 struct thunderx_lmc
*lmc
= file
->private_data
;
412 unsigned int cline_size
= cache_line_size();
416 unsigned int offs
, timeout
= 100000;
418 atomic_set(&lmc
->ecc_int
, 0);
420 lmc
->mem
= alloc_pages_node(lmc
->node
, GFP_KERNEL
, 0);
425 addr
= page_address(lmc
->mem
);
427 while (!atomic_read(&lmc
->ecc_int
) && timeout
--) {
428 stop_machine(inject_ecc_fn
, lmc
, NULL
);
430 for (offs
= 0; offs
< PAGE_SIZE
; offs
+= sizeof(tmp
)) {
432 * Do a load from the previously rigged location
433 * This should generate an error interrupt.
435 memcpy(tmp
, addr
+ offs
, cline_size
);
436 asm volatile("dsb ld\n");
440 __free_pages(lmc
->mem
, 0);
445 LMC_DEBUGFS_ENT(mask0
);
446 LMC_DEBUGFS_ENT(mask2
);
447 LMC_DEBUGFS_ENT(parity_test
);
449 DEBUGFS_STRUCT(inject_int
, 0200, thunderx_lmc_inject_int_write
, NULL
);
450 DEBUGFS_STRUCT(inject_ecc
, 0200, thunderx_lmc_inject_ecc_write
, NULL
);
451 DEBUGFS_STRUCT(int_w1c
, 0400, NULL
, thunderx_lmc_int_read
);
453 struct debugfs_entry
*lmc_dfs_ents
[] = {
456 &debugfs_parity_test
,
462 static int thunderx_create_debugfs_nodes(struct dentry
*parent
,
463 struct debugfs_entry
*attrs
[],
470 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
476 for (i
= 0; i
< num
; i
++) {
477 ent
= edac_debugfs_create_file(attrs
[i
]->name
, attrs
[i
]->mode
,
478 parent
, data
, &attrs
[i
]->fops
);
487 static phys_addr_t
thunderx_faddr_to_phys(u64 faddr
, struct thunderx_lmc
*lmc
)
489 phys_addr_t addr
= 0;
492 addr
|= lmc
->node
<< 40;
493 addr
|= LMC_FADR_FDIMM(faddr
) << lmc
->dimm_lsb
;
494 addr
|= LMC_FADR_FBUNK(faddr
) << lmc
->rank_lsb
;
495 addr
|= LMC_FADR_FROW(faddr
) << lmc
->row_lsb
;
496 addr
|= (LMC_FADR_FCOL(faddr
) >> 4) << lmc
->col_hi_lsb
;
498 bank
= LMC_FADR_FBANK(faddr
) << lmc
->bank_lsb
;
501 bank
^= get_bits(addr
, 12 + lmc
->xbits
, lmc
->bank_width
);
503 addr
|= bank
<< lmc
->bank_lsb
;
505 xbits
= PCI_FUNC(lmc
->pdev
->devfn
);
508 xbits
^= get_bits(addr
, 20, lmc
->xbits
) ^
509 get_bits(addr
, 12, lmc
->xbits
);
516 static unsigned int thunderx_get_num_lmcs(unsigned int node
)
518 unsigned int number
= 0;
519 struct pci_dev
*pdev
= NULL
;
522 pdev
= pci_get_device(PCI_VENDOR_ID_CAVIUM
,
523 PCI_DEVICE_ID_THUNDER_LMC
,
527 if (pdev
->dev
.numa_node
== node
)
538 #define LMC_MESSAGE_SIZE 120
539 #define LMC_OTHER_SIZE (50 * ARRAY_SIZE(lmc_errors))
541 static irqreturn_t
thunderx_lmc_err_isr(int irq
, void *dev_id
)
543 struct mem_ctl_info
*mci
= dev_id
;
544 struct thunderx_lmc
*lmc
= mci
->pvt_info
;
546 unsigned long head
= ring_pos(lmc
->ring_head
, ARRAY_SIZE(lmc
->err_ctx
));
547 struct lmc_err_ctx
*ctx
= &lmc
->err_ctx
[head
];
549 writeq(0, lmc
->regs
+ LMC_CHAR_MASK0
);
550 writeq(0, lmc
->regs
+ LMC_CHAR_MASK2
);
551 writeq(0x2, lmc
->regs
+ LMC_ECC_PARITY_TEST
);
553 ctx
->reg_int
= readq(lmc
->regs
+ LMC_INT
);
554 ctx
->reg_fadr
= readq(lmc
->regs
+ LMC_FADR
);
555 ctx
->reg_nxm_fadr
= readq(lmc
->regs
+ LMC_NXM_FADR
);
556 ctx
->reg_scram_fadr
= readq(lmc
->regs
+ LMC_SCRAM_FADR
);
557 ctx
->reg_ecc_synd
= readq(lmc
->regs
+ LMC_ECC_SYND
);
561 atomic_set(&lmc
->ecc_int
, 1);
563 /* Clear the interrupt */
564 writeq(ctx
->reg_int
, lmc
->regs
+ LMC_INT
);
566 return IRQ_WAKE_THREAD
;
569 static irqreturn_t
thunderx_lmc_threaded_isr(int irq
, void *dev_id
)
571 struct mem_ctl_info
*mci
= dev_id
;
572 struct thunderx_lmc
*lmc
= mci
->pvt_info
;
573 phys_addr_t phys_addr
;
576 struct lmc_err_ctx
*ctx
;
578 irqreturn_t ret
= IRQ_NONE
;
583 msg
= kmalloc(LMC_MESSAGE_SIZE
, GFP_KERNEL
);
584 other
= kmalloc(LMC_OTHER_SIZE
, GFP_KERNEL
);
589 while (CIRC_CNT(lmc
->ring_head
, lmc
->ring_tail
,
590 ARRAY_SIZE(lmc
->err_ctx
))) {
591 tail
= ring_pos(lmc
->ring_tail
, ARRAY_SIZE(lmc
->err_ctx
));
593 ctx
= &lmc
->err_ctx
[tail
];
595 dev_dbg(&lmc
->pdev
->dev
, "LMC_INT: %016llx\n",
597 dev_dbg(&lmc
->pdev
->dev
, "LMC_FADR: %016llx\n",
599 dev_dbg(&lmc
->pdev
->dev
, "LMC_NXM_FADR: %016llx\n",
601 dev_dbg(&lmc
->pdev
->dev
, "LMC_SCRAM_FADR: %016llx\n",
602 ctx
->reg_scram_fadr
);
603 dev_dbg(&lmc
->pdev
->dev
, "LMC_ECC_SYND: %016llx\n",
606 snprintf(msg
, LMC_MESSAGE_SIZE
,
607 "DIMM %lld rank %lld bank %lld row %lld col %lld",
608 LMC_FADR_FDIMM(ctx
->reg_scram_fadr
),
609 LMC_FADR_FBUNK(ctx
->reg_scram_fadr
),
610 LMC_FADR_FBANK(ctx
->reg_scram_fadr
),
611 LMC_FADR_FROW(ctx
->reg_scram_fadr
),
612 LMC_FADR_FCOL(ctx
->reg_scram_fadr
));
614 decode_register(other
, LMC_OTHER_SIZE
, lmc_errors
,
617 phys_addr
= thunderx_faddr_to_phys(ctx
->reg_fadr
, lmc
);
619 if (ctx
->reg_int
& LMC_INT_UE
)
620 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED
, mci
, 1,
621 phys_to_pfn(phys_addr
),
622 offset_in_page(phys_addr
),
623 0, -1, -1, -1, msg
, other
);
624 else if (ctx
->reg_int
& LMC_INT_CE
)
625 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, 1,
626 phys_to_pfn(phys_addr
),
627 offset_in_page(phys_addr
),
628 0, -1, -1, -1, msg
, other
);
643 static int thunderx_lmc_suspend(struct pci_dev
*pdev
, pm_message_t state
)
645 pci_save_state(pdev
);
646 pci_disable_device(pdev
);
648 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
653 static int thunderx_lmc_resume(struct pci_dev
*pdev
)
655 pci_set_power_state(pdev
, PCI_D0
);
656 pci_enable_wake(pdev
, PCI_D0
, 0);
657 pci_restore_state(pdev
);
663 static const struct pci_device_id thunderx_lmc_pci_tbl
[] = {
664 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_LMC
) },
668 static inline int pci_dev_to_mc_idx(struct pci_dev
*pdev
)
670 int node
= dev_to_node(&pdev
->dev
);
671 int ret
= PCI_FUNC(pdev
->devfn
);
673 ret
+= max(node
, 0) << 3;
678 static int thunderx_lmc_probe(struct pci_dev
*pdev
,
679 const struct pci_device_id
*id
)
681 struct thunderx_lmc
*lmc
;
682 struct edac_mc_layer layer
;
683 struct mem_ctl_info
*mci
;
684 u64 lmc_control
, lmc_ddr_pll_ctl
, lmc_config
;
689 layer
.type
= EDAC_MC_LAYER_SLOT
;
691 layer
.is_virt_csrow
= false;
693 ret
= pcim_enable_device(pdev
);
695 dev_err(&pdev
->dev
, "Cannot enable PCI device: %d\n", ret
);
699 ret
= pcim_iomap_regions(pdev
, BIT(0), "thunderx_lmc");
701 dev_err(&pdev
->dev
, "Cannot map PCI resources: %d\n", ret
);
705 mci
= edac_mc_alloc(pci_dev_to_mc_idx(pdev
), 1, &layer
,
706 sizeof(struct thunderx_lmc
));
710 mci
->pdev
= &pdev
->dev
;
713 pci_set_drvdata(pdev
, mci
);
715 lmc
->regs
= pcim_iomap_table(pdev
)[0];
717 lmc_control
= readq(lmc
->regs
+ LMC_CONTROL
);
718 lmc_ddr_pll_ctl
= readq(lmc
->regs
+ LMC_DDR_PLL_CTL
);
719 lmc_config
= readq(lmc
->regs
+ LMC_CONFIG
);
721 if (lmc_control
& LMC_CONTROL_RDIMM
) {
722 mci
->mtype_cap
= FIELD_GET(LMC_DDR_PLL_CTL_DDR4
,
724 MEM_RDDR4
: MEM_RDDR3
;
726 mci
->mtype_cap
= FIELD_GET(LMC_DDR_PLL_CTL_DDR4
,
731 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
732 mci
->edac_cap
= EDAC_FLAG_SECDED
;
734 mci
->mod_name
= "thunderx-lmc";
736 mci
->ctl_name
= "thunderx-lmc";
737 mci
->dev_name
= dev_name(&pdev
->dev
);
738 mci
->scrub_mode
= SCRUB_NONE
;
741 lmc
->msix_ent
.entry
= 0;
746 ret
= pci_enable_msix_exact(pdev
, &lmc
->msix_ent
, 1);
748 dev_err(&pdev
->dev
, "Cannot enable interrupt: %d\n", ret
);
752 ret
= devm_request_threaded_irq(&pdev
->dev
, lmc
->msix_ent
.vector
,
753 thunderx_lmc_err_isr
,
754 thunderx_lmc_threaded_isr
, 0,
755 "[EDAC] ThunderX LMC", mci
);
757 dev_err(&pdev
->dev
, "Cannot set ISR: %d\n", ret
);
761 lmc
->node
= FIELD_GET(THUNDERX_NODE
, pci_resource_start(pdev
, 0));
763 lmc
->xbits
= thunderx_get_num_lmcs(lmc
->node
) >> 1;
764 lmc
->bank_width
= (FIELD_GET(LMC_DDR_PLL_CTL_DDR4
, lmc_ddr_pll_ctl
) &&
765 FIELD_GET(LMC_CONFIG_BG2
, lmc_config
)) ? 4 : 3;
767 lmc
->pbank_lsb
= (lmc_config
>> 5) & 0xf;
768 lmc
->dimm_lsb
= 28 + lmc
->pbank_lsb
+ lmc
->xbits
;
769 lmc
->rank_lsb
= lmc
->dimm_lsb
;
770 lmc
->rank_lsb
-= FIELD_GET(LMC_CONFIG_RANK_ENA
, lmc_config
) ? 1 : 0;
771 lmc
->bank_lsb
= 7 + lmc
->xbits
;
772 lmc
->row_lsb
= 14 + LMC_CONFIG_ROW_LSB(lmc_config
) + lmc
->xbits
;
774 lmc
->col_hi_lsb
= lmc
->bank_lsb
+ lmc
->bank_width
;
776 lmc
->xor_bank
= lmc_control
& LMC_CONTROL_XOR_BANK
;
778 l2c_ioaddr
= ioremap(L2C_CTL
| FIELD_PREP(THUNDERX_NODE
, lmc
->node
),
782 dev_err(&pdev
->dev
, "Cannot map L2C_CTL\n");
786 lmc
->l2c_alias
= !(readq(l2c_ioaddr
) & L2C_CTL_DISIDXALIAS
);
790 ret
= edac_mc_add_mc(mci
);
792 dev_err(&pdev
->dev
, "Cannot add the MC: %d\n", ret
);
796 lmc_int
= readq(lmc
->regs
+ LMC_INT
);
797 writeq(lmc_int
, lmc
->regs
+ LMC_INT
);
799 writeq(LMC_INT_ENA_ALL
, lmc
->regs
+ LMC_INT_ENA_W1S
);
801 if (IS_ENABLED(CONFIG_EDAC_DEBUG
)) {
802 ret
= thunderx_create_debugfs_nodes(mci
->debugfs
,
805 ARRAY_SIZE(lmc_dfs_ents
));
807 if (ret
!= ARRAY_SIZE(lmc_dfs_ents
)) {
808 dev_warn(&pdev
->dev
, "Error creating debugfs entries: %d%s\n",
809 ret
, ret
>= 0 ? " created" : "");
816 pci_set_drvdata(pdev
, NULL
);
822 static void thunderx_lmc_remove(struct pci_dev
*pdev
)
824 struct mem_ctl_info
*mci
= pci_get_drvdata(pdev
);
825 struct thunderx_lmc
*lmc
= mci
->pvt_info
;
827 writeq(LMC_INT_ENA_ALL
, lmc
->regs
+ LMC_INT_ENA_W1C
);
829 edac_mc_del_mc(&pdev
->dev
);
833 MODULE_DEVICE_TABLE(pci
, thunderx_lmc_pci_tbl
);
835 static struct pci_driver thunderx_lmc_driver
= {
836 .name
= "thunderx_lmc_edac",
837 .probe
= thunderx_lmc_probe
,
838 .remove
= thunderx_lmc_remove
,
840 .suspend
= thunderx_lmc_suspend
,
841 .resume
= thunderx_lmc_resume
,
843 .id_table
= thunderx_lmc_pci_tbl
,
846 /*---------------------- OCX driver ---------------------------------*/
848 #define PCI_DEVICE_ID_THUNDER_OCX 0xa013
850 #define OCX_LINK_INTS 3
851 #define OCX_INTS (OCX_LINK_INTS + 1)
852 #define OCX_RX_LANES 24
853 #define OCX_RX_LANE_STATS 15
855 #define OCX_COM_INT 0x100
856 #define OCX_COM_INT_W1S 0x108
857 #define OCX_COM_INT_ENA_W1S 0x110
858 #define OCX_COM_INT_ENA_W1C 0x118
860 #define OCX_COM_IO_BADID BIT(54)
861 #define OCX_COM_MEM_BADID BIT(53)
862 #define OCX_COM_COPR_BADID BIT(52)
863 #define OCX_COM_WIN_REQ_BADID BIT(51)
864 #define OCX_COM_WIN_REQ_TOUT BIT(50)
865 #define OCX_COM_RX_LANE GENMASK(23, 0)
867 #define OCX_COM_INT_CE (OCX_COM_IO_BADID | \
868 OCX_COM_MEM_BADID | \
869 OCX_COM_COPR_BADID | \
870 OCX_COM_WIN_REQ_BADID | \
871 OCX_COM_WIN_REQ_TOUT)
873 static const struct error_descr ocx_com_errors
[] = {
875 .type
= ERR_CORRECTED
,
876 .mask
= OCX_COM_IO_BADID
,
877 .descr
= "Invalid IO transaction node ID",
880 .type
= ERR_CORRECTED
,
881 .mask
= OCX_COM_MEM_BADID
,
882 .descr
= "Invalid memory transaction node ID",
885 .type
= ERR_CORRECTED
,
886 .mask
= OCX_COM_COPR_BADID
,
887 .descr
= "Invalid coprocessor transaction node ID",
890 .type
= ERR_CORRECTED
,
891 .mask
= OCX_COM_WIN_REQ_BADID
,
892 .descr
= "Invalid SLI transaction node ID",
895 .type
= ERR_CORRECTED
,
896 .mask
= OCX_COM_WIN_REQ_TOUT
,
897 .descr
= "Window/core request timeout",
902 #define OCX_COM_LINKX_INT(x) (0x120 + (x) * 8)
903 #define OCX_COM_LINKX_INT_W1S(x) (0x140 + (x) * 8)
904 #define OCX_COM_LINKX_INT_ENA_W1S(x) (0x160 + (x) * 8)
905 #define OCX_COM_LINKX_INT_ENA_W1C(x) (0x180 + (x) * 8)
907 #define OCX_COM_LINK_BAD_WORD BIT(13)
908 #define OCX_COM_LINK_ALIGN_FAIL BIT(12)
909 #define OCX_COM_LINK_ALIGN_DONE BIT(11)
910 #define OCX_COM_LINK_UP BIT(10)
911 #define OCX_COM_LINK_STOP BIT(9)
912 #define OCX_COM_LINK_BLK_ERR BIT(8)
913 #define OCX_COM_LINK_REINIT BIT(7)
914 #define OCX_COM_LINK_LNK_DATA BIT(6)
915 #define OCX_COM_LINK_RXFIFO_DBE BIT(5)
916 #define OCX_COM_LINK_RXFIFO_SBE BIT(4)
917 #define OCX_COM_LINK_TXFIFO_DBE BIT(3)
918 #define OCX_COM_LINK_TXFIFO_SBE BIT(2)
919 #define OCX_COM_LINK_REPLAY_DBE BIT(1)
920 #define OCX_COM_LINK_REPLAY_SBE BIT(0)
922 static const struct error_descr ocx_com_link_errors
[] = {
924 .type
= ERR_CORRECTED
,
925 .mask
= OCX_COM_LINK_REPLAY_SBE
,
926 .descr
= "Replay buffer single-bit error",
929 .type
= ERR_CORRECTED
,
930 .mask
= OCX_COM_LINK_TXFIFO_SBE
,
931 .descr
= "TX FIFO single-bit error",
934 .type
= ERR_CORRECTED
,
935 .mask
= OCX_COM_LINK_RXFIFO_SBE
,
936 .descr
= "RX FIFO single-bit error",
939 .type
= ERR_CORRECTED
,
940 .mask
= OCX_COM_LINK_BLK_ERR
,
941 .descr
= "Block code error",
944 .type
= ERR_CORRECTED
,
945 .mask
= OCX_COM_LINK_ALIGN_FAIL
,
946 .descr
= "Link alignment failure",
949 .type
= ERR_CORRECTED
,
950 .mask
= OCX_COM_LINK_BAD_WORD
,
951 .descr
= "Bad code word",
954 .type
= ERR_UNCORRECTED
,
955 .mask
= OCX_COM_LINK_REPLAY_DBE
,
956 .descr
= "Replay buffer double-bit error",
959 .type
= ERR_UNCORRECTED
,
960 .mask
= OCX_COM_LINK_TXFIFO_DBE
,
961 .descr
= "TX FIFO double-bit error",
964 .type
= ERR_UNCORRECTED
,
965 .mask
= OCX_COM_LINK_RXFIFO_DBE
,
966 .descr
= "RX FIFO double-bit error",
969 .type
= ERR_UNCORRECTED
,
970 .mask
= OCX_COM_LINK_STOP
,
971 .descr
= "Link stopped",
976 #define OCX_COM_LINK_INT_UE (OCX_COM_LINK_REPLAY_DBE | \
977 OCX_COM_LINK_TXFIFO_DBE | \
978 OCX_COM_LINK_RXFIFO_DBE | \
981 #define OCX_COM_LINK_INT_CE (OCX_COM_LINK_REPLAY_SBE | \
982 OCX_COM_LINK_TXFIFO_SBE | \
983 OCX_COM_LINK_RXFIFO_SBE | \
984 OCX_COM_LINK_BLK_ERR | \
985 OCX_COM_LINK_ALIGN_FAIL | \
986 OCX_COM_LINK_BAD_WORD)
988 #define OCX_LNE_INT(x) (0x8018 + (x) * 0x100)
989 #define OCX_LNE_INT_EN(x) (0x8020 + (x) * 0x100)
990 #define OCX_LNE_BAD_CNT(x) (0x8028 + (x) * 0x100)
991 #define OCX_LNE_CFG(x) (0x8000 + (x) * 0x100)
992 #define OCX_LNE_STAT(x, y) (0x8040 + (x) * 0x100 + (y) * 8)
994 #define OCX_LNE_CFG_RX_BDRY_LOCK_DIS BIT(8)
995 #define OCX_LNE_CFG_RX_STAT_WRAP_DIS BIT(2)
996 #define OCX_LNE_CFG_RX_STAT_RDCLR BIT(1)
997 #define OCX_LNE_CFG_RX_STAT_ENA BIT(0)
1000 #define OCX_LANE_BAD_64B67B BIT(8)
1001 #define OCX_LANE_DSKEW_FIFO_OVFL BIT(5)
1002 #define OCX_LANE_SCRM_SYNC_LOSS BIT(4)
1003 #define OCX_LANE_UKWN_CNTL_WORD BIT(3)
1004 #define OCX_LANE_CRC32_ERR BIT(2)
1005 #define OCX_LANE_BDRY_SYNC_LOSS BIT(1)
1006 #define OCX_LANE_SERDES_LOCK_LOSS BIT(0)
1008 #define OCX_COM_LANE_INT_UE (0)
1009 #define OCX_COM_LANE_INT_CE (OCX_LANE_SERDES_LOCK_LOSS | \
1010 OCX_LANE_BDRY_SYNC_LOSS | \
1011 OCX_LANE_CRC32_ERR | \
1012 OCX_LANE_UKWN_CNTL_WORD | \
1013 OCX_LANE_SCRM_SYNC_LOSS | \
1014 OCX_LANE_DSKEW_FIFO_OVFL | \
1015 OCX_LANE_BAD_64B67B)
1017 static const struct error_descr ocx_lane_errors
[] = {
1019 .type
= ERR_CORRECTED
,
1020 .mask
= OCX_LANE_SERDES_LOCK_LOSS
,
1021 .descr
= "RX SerDes lock lost",
1024 .type
= ERR_CORRECTED
,
1025 .mask
= OCX_LANE_BDRY_SYNC_LOSS
,
1026 .descr
= "RX word boundary lost",
1029 .type
= ERR_CORRECTED
,
1030 .mask
= OCX_LANE_CRC32_ERR
,
1031 .descr
= "CRC32 error",
1034 .type
= ERR_CORRECTED
,
1035 .mask
= OCX_LANE_UKWN_CNTL_WORD
,
1036 .descr
= "Unknown control word",
1039 .type
= ERR_CORRECTED
,
1040 .mask
= OCX_LANE_SCRM_SYNC_LOSS
,
1041 .descr
= "Scrambler synchronization lost",
1044 .type
= ERR_CORRECTED
,
1045 .mask
= OCX_LANE_DSKEW_FIFO_OVFL
,
1046 .descr
= "RX deskew FIFO overflow",
1049 .type
= ERR_CORRECTED
,
1050 .mask
= OCX_LANE_BAD_64B67B
,
1051 .descr
= "Bad 64B/67B codeword",
1056 #define OCX_LNE_INT_ENA_ALL (GENMASK(9, 8) | GENMASK(6, 0))
1057 #define OCX_COM_INT_ENA_ALL (GENMASK(54, 50) | GENMASK(23, 0))
1058 #define OCX_COM_LINKX_INT_ENA_ALL (GENMASK(13, 12) | \
1059 GENMASK(9, 7) | GENMASK(5, 0))
1061 #define OCX_TLKX_ECC_CTL(x) (0x10018 + (x) * 0x2000)
1062 #define OCX_RLKX_ECC_CTL(x) (0x18018 + (x) * 0x2000)
1064 struct ocx_com_err_ctx
{
1066 u64 reg_lane_int
[OCX_RX_LANES
];
1067 u64 reg_lane_stat11
[OCX_RX_LANES
];
1070 struct ocx_link_err_ctx
{
1071 u64 reg_com_link_int
;
1075 struct thunderx_ocx
{
1078 struct pci_dev
*pdev
;
1079 struct edac_device_ctl_info
*edac_dev
;
1081 struct dentry
*debugfs
;
1082 struct msix_entry msix_ent
[OCX_INTS
];
1084 struct ocx_com_err_ctx com_err_ctx
[RING_ENTRIES
];
1085 struct ocx_link_err_ctx link_err_ctx
[RING_ENTRIES
];
1087 unsigned long com_ring_head
;
1088 unsigned long com_ring_tail
;
1090 unsigned long link_ring_head
;
1091 unsigned long link_ring_tail
;
1094 #define OCX_MESSAGE_SIZE SZ_1K
1095 #define OCX_OTHER_SIZE (50 * ARRAY_SIZE(ocx_com_link_errors))
1097 /* This handler is threaded */
1098 static irqreturn_t
thunderx_ocx_com_isr(int irq
, void *irq_id
)
1100 struct msix_entry
*msix
= irq_id
;
1101 struct thunderx_ocx
*ocx
= container_of(msix
, struct thunderx_ocx
,
1102 msix_ent
[msix
->entry
]);
1105 unsigned long head
= ring_pos(ocx
->com_ring_head
,
1106 ARRAY_SIZE(ocx
->com_err_ctx
));
1107 struct ocx_com_err_ctx
*ctx
= &ocx
->com_err_ctx
[head
];
1109 ctx
->reg_com_int
= readq(ocx
->regs
+ OCX_COM_INT
);
1111 for (lane
= 0; lane
< OCX_RX_LANES
; lane
++) {
1112 ctx
->reg_lane_int
[lane
] =
1113 readq(ocx
->regs
+ OCX_LNE_INT(lane
));
1114 ctx
->reg_lane_stat11
[lane
] =
1115 readq(ocx
->regs
+ OCX_LNE_STAT(lane
, 11));
1117 writeq(ctx
->reg_lane_int
[lane
], ocx
->regs
+ OCX_LNE_INT(lane
));
1120 writeq(ctx
->reg_com_int
, ocx
->regs
+ OCX_COM_INT
);
1122 ocx
->com_ring_head
++;
1124 return IRQ_WAKE_THREAD
;
1127 static irqreturn_t
thunderx_ocx_com_threaded_isr(int irq
, void *irq_id
)
1129 struct msix_entry
*msix
= irq_id
;
1130 struct thunderx_ocx
*ocx
= container_of(msix
, struct thunderx_ocx
,
1131 msix_ent
[msix
->entry
]);
1133 irqreturn_t ret
= IRQ_NONE
;
1136 struct ocx_com_err_ctx
*ctx
;
1141 msg
= kmalloc(OCX_MESSAGE_SIZE
, GFP_KERNEL
);
1142 other
= kmalloc(OCX_OTHER_SIZE
, GFP_KERNEL
);
1147 while (CIRC_CNT(ocx
->com_ring_head
, ocx
->com_ring_tail
,
1148 ARRAY_SIZE(ocx
->com_err_ctx
))) {
1149 tail
= ring_pos(ocx
->com_ring_tail
,
1150 ARRAY_SIZE(ocx
->com_err_ctx
));
1151 ctx
= &ocx
->com_err_ctx
[tail
];
1153 snprintf(msg
, OCX_MESSAGE_SIZE
, "%s: OCX_COM_INT: %016llx",
1154 ocx
->edac_dev
->ctl_name
, ctx
->reg_com_int
);
1156 decode_register(other
, OCX_OTHER_SIZE
,
1157 ocx_com_errors
, ctx
->reg_com_int
);
1159 strncat(msg
, other
, OCX_MESSAGE_SIZE
);
1161 for (lane
= 0; lane
< OCX_RX_LANES
; lane
++)
1162 if (ctx
->reg_com_int
& BIT(lane
)) {
1163 snprintf(other
, OCX_OTHER_SIZE
,
1164 "\n\tOCX_LNE_INT[%02d]: %016llx OCX_LNE_STAT11[%02d]: %016llx",
1165 lane
, ctx
->reg_lane_int
[lane
],
1166 lane
, ctx
->reg_lane_stat11
[lane
]);
1168 strncat(msg
, other
, OCX_MESSAGE_SIZE
);
1170 decode_register(other
, OCX_OTHER_SIZE
,
1172 ctx
->reg_lane_int
[lane
]);
1173 strncat(msg
, other
, OCX_MESSAGE_SIZE
);
1176 if (ctx
->reg_com_int
& OCX_COM_INT_CE
)
1177 edac_device_handle_ce(ocx
->edac_dev
, 0, 0, msg
);
1179 ocx
->com_ring_tail
++;
1191 static irqreturn_t
thunderx_ocx_lnk_isr(int irq
, void *irq_id
)
1193 struct msix_entry
*msix
= irq_id
;
1194 struct thunderx_ocx
*ocx
= container_of(msix
, struct thunderx_ocx
,
1195 msix_ent
[msix
->entry
]);
1196 unsigned long head
= ring_pos(ocx
->link_ring_head
,
1197 ARRAY_SIZE(ocx
->link_err_ctx
));
1198 struct ocx_link_err_ctx
*ctx
= &ocx
->link_err_ctx
[head
];
1200 ctx
->link
= msix
->entry
;
1201 ctx
->reg_com_link_int
= readq(ocx
->regs
+ OCX_COM_LINKX_INT(ctx
->link
));
1203 writeq(ctx
->reg_com_link_int
, ocx
->regs
+ OCX_COM_LINKX_INT(ctx
->link
));
1205 ocx
->link_ring_head
++;
1207 return IRQ_WAKE_THREAD
;
1210 static irqreturn_t
thunderx_ocx_lnk_threaded_isr(int irq
, void *irq_id
)
1212 struct msix_entry
*msix
= irq_id
;
1213 struct thunderx_ocx
*ocx
= container_of(msix
, struct thunderx_ocx
,
1214 msix_ent
[msix
->entry
]);
1215 irqreturn_t ret
= IRQ_NONE
;
1217 struct ocx_link_err_ctx
*ctx
;
1222 msg
= kmalloc(OCX_MESSAGE_SIZE
, GFP_KERNEL
);
1223 other
= kmalloc(OCX_OTHER_SIZE
, GFP_KERNEL
);
1228 while (CIRC_CNT(ocx
->link_ring_head
, ocx
->link_ring_tail
,
1229 ARRAY_SIZE(ocx
->link_err_ctx
))) {
1230 tail
= ring_pos(ocx
->link_ring_head
,
1231 ARRAY_SIZE(ocx
->link_err_ctx
));
1233 ctx
= &ocx
->link_err_ctx
[tail
];
1235 snprintf(msg
, OCX_MESSAGE_SIZE
,
1236 "%s: OCX_COM_LINK_INT[%d]: %016llx",
1237 ocx
->edac_dev
->ctl_name
,
1238 ctx
->link
, ctx
->reg_com_link_int
);
1240 decode_register(other
, OCX_OTHER_SIZE
,
1241 ocx_com_link_errors
, ctx
->reg_com_link_int
);
1243 strncat(msg
, other
, OCX_MESSAGE_SIZE
);
1245 if (ctx
->reg_com_link_int
& OCX_COM_LINK_INT_UE
)
1246 edac_device_handle_ue(ocx
->edac_dev
, 0, 0, msg
);
1247 else if (ctx
->reg_com_link_int
& OCX_COM_LINK_INT_CE
)
1248 edac_device_handle_ce(ocx
->edac_dev
, 0, 0, msg
);
1250 ocx
->link_ring_tail
++;
1261 #define OCX_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(ocx, _name, _reg)
1263 OCX_DEBUGFS_ATTR(tlk0_ecc_ctl
, OCX_TLKX_ECC_CTL(0));
1264 OCX_DEBUGFS_ATTR(tlk1_ecc_ctl
, OCX_TLKX_ECC_CTL(1));
1265 OCX_DEBUGFS_ATTR(tlk2_ecc_ctl
, OCX_TLKX_ECC_CTL(2));
1267 OCX_DEBUGFS_ATTR(rlk0_ecc_ctl
, OCX_RLKX_ECC_CTL(0));
1268 OCX_DEBUGFS_ATTR(rlk1_ecc_ctl
, OCX_RLKX_ECC_CTL(1));
1269 OCX_DEBUGFS_ATTR(rlk2_ecc_ctl
, OCX_RLKX_ECC_CTL(2));
1271 OCX_DEBUGFS_ATTR(com_link0_int
, OCX_COM_LINKX_INT_W1S(0));
1272 OCX_DEBUGFS_ATTR(com_link1_int
, OCX_COM_LINKX_INT_W1S(1));
1273 OCX_DEBUGFS_ATTR(com_link2_int
, OCX_COM_LINKX_INT_W1S(2));
1275 OCX_DEBUGFS_ATTR(lne00_badcnt
, OCX_LNE_BAD_CNT(0));
1276 OCX_DEBUGFS_ATTR(lne01_badcnt
, OCX_LNE_BAD_CNT(1));
1277 OCX_DEBUGFS_ATTR(lne02_badcnt
, OCX_LNE_BAD_CNT(2));
1278 OCX_DEBUGFS_ATTR(lne03_badcnt
, OCX_LNE_BAD_CNT(3));
1279 OCX_DEBUGFS_ATTR(lne04_badcnt
, OCX_LNE_BAD_CNT(4));
1280 OCX_DEBUGFS_ATTR(lne05_badcnt
, OCX_LNE_BAD_CNT(5));
1281 OCX_DEBUGFS_ATTR(lne06_badcnt
, OCX_LNE_BAD_CNT(6));
1282 OCX_DEBUGFS_ATTR(lne07_badcnt
, OCX_LNE_BAD_CNT(7));
1284 OCX_DEBUGFS_ATTR(lne08_badcnt
, OCX_LNE_BAD_CNT(8));
1285 OCX_DEBUGFS_ATTR(lne09_badcnt
, OCX_LNE_BAD_CNT(9));
1286 OCX_DEBUGFS_ATTR(lne10_badcnt
, OCX_LNE_BAD_CNT(10));
1287 OCX_DEBUGFS_ATTR(lne11_badcnt
, OCX_LNE_BAD_CNT(11));
1288 OCX_DEBUGFS_ATTR(lne12_badcnt
, OCX_LNE_BAD_CNT(12));
1289 OCX_DEBUGFS_ATTR(lne13_badcnt
, OCX_LNE_BAD_CNT(13));
1290 OCX_DEBUGFS_ATTR(lne14_badcnt
, OCX_LNE_BAD_CNT(14));
1291 OCX_DEBUGFS_ATTR(lne15_badcnt
, OCX_LNE_BAD_CNT(15));
1293 OCX_DEBUGFS_ATTR(lne16_badcnt
, OCX_LNE_BAD_CNT(16));
1294 OCX_DEBUGFS_ATTR(lne17_badcnt
, OCX_LNE_BAD_CNT(17));
1295 OCX_DEBUGFS_ATTR(lne18_badcnt
, OCX_LNE_BAD_CNT(18));
1296 OCX_DEBUGFS_ATTR(lne19_badcnt
, OCX_LNE_BAD_CNT(19));
1297 OCX_DEBUGFS_ATTR(lne20_badcnt
, OCX_LNE_BAD_CNT(20));
1298 OCX_DEBUGFS_ATTR(lne21_badcnt
, OCX_LNE_BAD_CNT(21));
1299 OCX_DEBUGFS_ATTR(lne22_badcnt
, OCX_LNE_BAD_CNT(22));
1300 OCX_DEBUGFS_ATTR(lne23_badcnt
, OCX_LNE_BAD_CNT(23));
1302 OCX_DEBUGFS_ATTR(com_int
, OCX_COM_INT_W1S
);
1304 struct debugfs_entry
*ocx_dfs_ents
[] = {
1305 &debugfs_tlk0_ecc_ctl
,
1306 &debugfs_tlk1_ecc_ctl
,
1307 &debugfs_tlk2_ecc_ctl
,
1309 &debugfs_rlk0_ecc_ctl
,
1310 &debugfs_rlk1_ecc_ctl
,
1311 &debugfs_rlk2_ecc_ctl
,
1313 &debugfs_com_link0_int
,
1314 &debugfs_com_link1_int
,
1315 &debugfs_com_link2_int
,
1317 &debugfs_lne00_badcnt
,
1318 &debugfs_lne01_badcnt
,
1319 &debugfs_lne02_badcnt
,
1320 &debugfs_lne03_badcnt
,
1321 &debugfs_lne04_badcnt
,
1322 &debugfs_lne05_badcnt
,
1323 &debugfs_lne06_badcnt
,
1324 &debugfs_lne07_badcnt
,
1325 &debugfs_lne08_badcnt
,
1326 &debugfs_lne09_badcnt
,
1327 &debugfs_lne10_badcnt
,
1328 &debugfs_lne11_badcnt
,
1329 &debugfs_lne12_badcnt
,
1330 &debugfs_lne13_badcnt
,
1331 &debugfs_lne14_badcnt
,
1332 &debugfs_lne15_badcnt
,
1333 &debugfs_lne16_badcnt
,
1334 &debugfs_lne17_badcnt
,
1335 &debugfs_lne18_badcnt
,
1336 &debugfs_lne19_badcnt
,
1337 &debugfs_lne20_badcnt
,
1338 &debugfs_lne21_badcnt
,
1339 &debugfs_lne22_badcnt
,
1340 &debugfs_lne23_badcnt
,
1345 static const struct pci_device_id thunderx_ocx_pci_tbl
[] = {
1346 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_OCX
) },
1350 static void thunderx_ocx_clearstats(struct thunderx_ocx
*ocx
)
1352 int lane
, stat
, cfg
;
1354 for (lane
= 0; lane
< OCX_RX_LANES
; lane
++) {
1355 cfg
= readq(ocx
->regs
+ OCX_LNE_CFG(lane
));
1356 cfg
|= OCX_LNE_CFG_RX_STAT_RDCLR
;
1357 cfg
&= ~OCX_LNE_CFG_RX_STAT_ENA
;
1358 writeq(cfg
, ocx
->regs
+ OCX_LNE_CFG(lane
));
1360 for (stat
= 0; stat
< OCX_RX_LANE_STATS
; stat
++)
1361 readq(ocx
->regs
+ OCX_LNE_STAT(lane
, stat
));
1365 static int thunderx_ocx_probe(struct pci_dev
*pdev
,
1366 const struct pci_device_id
*id
)
1368 struct thunderx_ocx
*ocx
;
1369 struct edac_device_ctl_info
*edac_dev
;
1376 ret
= pcim_enable_device(pdev
);
1378 dev_err(&pdev
->dev
, "Cannot enable PCI device: %d\n", ret
);
1382 ret
= pcim_iomap_regions(pdev
, BIT(0), "thunderx_ocx");
1384 dev_err(&pdev
->dev
, "Cannot map PCI resources: %d\n", ret
);
1388 idx
= edac_device_alloc_index();
1389 snprintf(name
, sizeof(name
), "OCX%d", idx
);
1390 edac_dev
= edac_device_alloc_ctl_info(sizeof(struct thunderx_ocx
),
1394 dev_err(&pdev
->dev
, "Cannot allocate EDAC device: %d\n", ret
);
1397 ocx
= edac_dev
->pvt_info
;
1398 ocx
->edac_dev
= edac_dev
;
1399 ocx
->com_ring_head
= 0;
1400 ocx
->com_ring_tail
= 0;
1401 ocx
->link_ring_head
= 0;
1402 ocx
->link_ring_tail
= 0;
1404 ocx
->regs
= pcim_iomap_table(pdev
)[0];
1406 dev_err(&pdev
->dev
, "Cannot map PCI resources: %d\n", ret
);
1413 for (i
= 0; i
< OCX_INTS
; i
++) {
1414 ocx
->msix_ent
[i
].entry
= i
;
1415 ocx
->msix_ent
[i
].vector
= 0;
1418 ret
= pci_enable_msix_exact(pdev
, ocx
->msix_ent
, OCX_INTS
);
1420 dev_err(&pdev
->dev
, "Cannot enable interrupt: %d\n", ret
);
1424 for (i
= 0; i
< OCX_INTS
; i
++) {
1425 ret
= devm_request_threaded_irq(&pdev
->dev
,
1426 ocx
->msix_ent
[i
].vector
,
1428 thunderx_ocx_com_isr
:
1429 thunderx_ocx_lnk_isr
,
1431 thunderx_ocx_com_threaded_isr
:
1432 thunderx_ocx_lnk_threaded_isr
,
1433 0, "[EDAC] ThunderX OCX",
1439 edac_dev
->dev
= &pdev
->dev
;
1440 edac_dev
->dev_name
= dev_name(&pdev
->dev
);
1441 edac_dev
->mod_name
= "thunderx-ocx";
1442 edac_dev
->ctl_name
= "thunderx-ocx";
1444 ret
= edac_device_add_device(edac_dev
);
1446 dev_err(&pdev
->dev
, "Cannot add EDAC device: %d\n", ret
);
1450 if (IS_ENABLED(CONFIG_EDAC_DEBUG
)) {
1451 ocx
->debugfs
= edac_debugfs_create_dir(pdev
->dev
.kobj
.name
);
1453 ret
= thunderx_create_debugfs_nodes(ocx
->debugfs
,
1456 ARRAY_SIZE(ocx_dfs_ents
));
1457 if (ret
!= ARRAY_SIZE(ocx_dfs_ents
)) {
1458 dev_warn(&pdev
->dev
, "Error creating debugfs entries: %d%s\n",
1459 ret
, ret
>= 0 ? " created" : "");
1463 pci_set_drvdata(pdev
, edac_dev
);
1465 thunderx_ocx_clearstats(ocx
);
1467 for (i
= 0; i
< OCX_RX_LANES
; i
++) {
1468 writeq(OCX_LNE_INT_ENA_ALL
,
1469 ocx
->regs
+ OCX_LNE_INT_EN(i
));
1471 reg
= readq(ocx
->regs
+ OCX_LNE_INT(i
));
1472 writeq(reg
, ocx
->regs
+ OCX_LNE_INT(i
));
1476 for (i
= 0; i
< OCX_LINK_INTS
; i
++) {
1477 reg
= readq(ocx
->regs
+ OCX_COM_LINKX_INT(i
));
1478 writeq(reg
, ocx
->regs
+ OCX_COM_LINKX_INT(i
));
1480 writeq(OCX_COM_LINKX_INT_ENA_ALL
,
1481 ocx
->regs
+ OCX_COM_LINKX_INT_ENA_W1S(i
));
1484 reg
= readq(ocx
->regs
+ OCX_COM_INT
);
1485 writeq(reg
, ocx
->regs
+ OCX_COM_INT
);
1487 writeq(OCX_COM_INT_ENA_ALL
, ocx
->regs
+ OCX_COM_INT_ENA_W1S
);
1491 edac_device_free_ctl_info(edac_dev
);
1496 static void thunderx_ocx_remove(struct pci_dev
*pdev
)
1498 struct edac_device_ctl_info
*edac_dev
= pci_get_drvdata(pdev
);
1499 struct thunderx_ocx
*ocx
= edac_dev
->pvt_info
;
1502 writeq(OCX_COM_INT_ENA_ALL
, ocx
->regs
+ OCX_COM_INT_ENA_W1C
);
1504 for (i
= 0; i
< OCX_INTS
; i
++) {
1505 writeq(OCX_COM_LINKX_INT_ENA_ALL
,
1506 ocx
->regs
+ OCX_COM_LINKX_INT_ENA_W1C(i
));
1509 edac_debugfs_remove_recursive(ocx
->debugfs
);
1511 edac_device_del_device(&pdev
->dev
);
1512 edac_device_free_ctl_info(edac_dev
);
1515 MODULE_DEVICE_TABLE(pci
, thunderx_ocx_pci_tbl
);
1517 static struct pci_driver thunderx_ocx_driver
= {
1518 .name
= "thunderx_ocx_edac",
1519 .probe
= thunderx_ocx_probe
,
1520 .remove
= thunderx_ocx_remove
,
1521 .id_table
= thunderx_ocx_pci_tbl
,
1524 /*---------------------- L2C driver ---------------------------------*/
1526 #define PCI_DEVICE_ID_THUNDER_L2C_TAD 0xa02e
1527 #define PCI_DEVICE_ID_THUNDER_L2C_CBC 0xa02f
1528 #define PCI_DEVICE_ID_THUNDER_L2C_MCI 0xa030
1530 #define L2C_TAD_INT_W1C 0x40000
1531 #define L2C_TAD_INT_W1S 0x40008
1533 #define L2C_TAD_INT_ENA_W1C 0x40020
1534 #define L2C_TAD_INT_ENA_W1S 0x40028
1537 #define L2C_TAD_INT_L2DDBE BIT(1)
1538 #define L2C_TAD_INT_SBFSBE BIT(2)
1539 #define L2C_TAD_INT_SBFDBE BIT(3)
1540 #define L2C_TAD_INT_FBFSBE BIT(4)
1541 #define L2C_TAD_INT_FBFDBE BIT(5)
1542 #define L2C_TAD_INT_TAGDBE BIT(9)
1543 #define L2C_TAD_INT_RDDISLMC BIT(15)
1544 #define L2C_TAD_INT_WRDISLMC BIT(16)
1545 #define L2C_TAD_INT_LFBTO BIT(17)
1546 #define L2C_TAD_INT_GSYNCTO BIT(18)
1547 #define L2C_TAD_INT_RTGSBE BIT(32)
1548 #define L2C_TAD_INT_RTGDBE BIT(33)
1549 #define L2C_TAD_INT_RDDISOCI BIT(34)
1550 #define L2C_TAD_INT_WRDISOCI BIT(35)
1552 #define L2C_TAD_INT_ECC (L2C_TAD_INT_L2DDBE | \
1553 L2C_TAD_INT_SBFSBE | L2C_TAD_INT_SBFDBE | \
1554 L2C_TAD_INT_FBFSBE | L2C_TAD_INT_FBFDBE)
1556 #define L2C_TAD_INT_CE (L2C_TAD_INT_SBFSBE | \
1559 #define L2C_TAD_INT_UE (L2C_TAD_INT_L2DDBE | \
1560 L2C_TAD_INT_SBFDBE | \
1561 L2C_TAD_INT_FBFDBE | \
1562 L2C_TAD_INT_TAGDBE | \
1563 L2C_TAD_INT_RTGDBE | \
1564 L2C_TAD_INT_WRDISOCI | \
1565 L2C_TAD_INT_RDDISOCI | \
1566 L2C_TAD_INT_WRDISLMC | \
1567 L2C_TAD_INT_RDDISLMC | \
1568 L2C_TAD_INT_LFBTO | \
1569 L2C_TAD_INT_GSYNCTO)
1571 static const struct error_descr l2_tad_errors
[] = {
1573 .type
= ERR_CORRECTED
,
1574 .mask
= L2C_TAD_INT_SBFSBE
,
1575 .descr
= "SBF single-bit error",
1578 .type
= ERR_CORRECTED
,
1579 .mask
= L2C_TAD_INT_FBFSBE
,
1580 .descr
= "FBF single-bit error",
1583 .type
= ERR_UNCORRECTED
,
1584 .mask
= L2C_TAD_INT_L2DDBE
,
1585 .descr
= "L2D double-bit error",
1588 .type
= ERR_UNCORRECTED
,
1589 .mask
= L2C_TAD_INT_SBFDBE
,
1590 .descr
= "SBF double-bit error",
1593 .type
= ERR_UNCORRECTED
,
1594 .mask
= L2C_TAD_INT_FBFDBE
,
1595 .descr
= "FBF double-bit error",
1598 .type
= ERR_UNCORRECTED
,
1599 .mask
= L2C_TAD_INT_TAGDBE
,
1600 .descr
= "TAG double-bit error",
1603 .type
= ERR_UNCORRECTED
,
1604 .mask
= L2C_TAD_INT_RTGDBE
,
1605 .descr
= "RTG double-bit error",
1608 .type
= ERR_UNCORRECTED
,
1609 .mask
= L2C_TAD_INT_WRDISOCI
,
1610 .descr
= "Write to a disabled CCPI",
1613 .type
= ERR_UNCORRECTED
,
1614 .mask
= L2C_TAD_INT_RDDISOCI
,
1615 .descr
= "Read from a disabled CCPI",
1618 .type
= ERR_UNCORRECTED
,
1619 .mask
= L2C_TAD_INT_WRDISLMC
,
1620 .descr
= "Write to a disabled LMC",
1623 .type
= ERR_UNCORRECTED
,
1624 .mask
= L2C_TAD_INT_RDDISLMC
,
1625 .descr
= "Read from a disabled LMC",
1628 .type
= ERR_UNCORRECTED
,
1629 .mask
= L2C_TAD_INT_LFBTO
,
1630 .descr
= "LFB entry timeout",
1633 .type
= ERR_UNCORRECTED
,
1634 .mask
= L2C_TAD_INT_GSYNCTO
,
1635 .descr
= "Global sync CCPI timeout",
1640 #define L2C_TAD_INT_TAG (L2C_TAD_INT_TAGDBE)
1642 #define L2C_TAD_INT_RTG (L2C_TAD_INT_RTGDBE)
1644 #define L2C_TAD_INT_DISLMC (L2C_TAD_INT_WRDISLMC | L2C_TAD_INT_RDDISLMC)
1646 #define L2C_TAD_INT_DISOCI (L2C_TAD_INT_WRDISOCI | L2C_TAD_INT_RDDISOCI)
1648 #define L2C_TAD_INT_ENA_ALL (L2C_TAD_INT_ECC | L2C_TAD_INT_TAG | \
1650 L2C_TAD_INT_DISLMC | L2C_TAD_INT_DISOCI | \
1653 #define L2C_TAD_TIMETWO 0x50000
1654 #define L2C_TAD_TIMEOUT 0x50100
1655 #define L2C_TAD_ERR 0x60000
1656 #define L2C_TAD_TQD_ERR 0x60100
1657 #define L2C_TAD_TTG_ERR 0x60200
1660 #define L2C_CBC_INT_W1C 0x60000
1662 #define L2C_CBC_INT_RSDSBE BIT(0)
1663 #define L2C_CBC_INT_RSDDBE BIT(1)
1665 #define L2C_CBC_INT_RSD (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_RSDDBE)
1667 #define L2C_CBC_INT_MIBSBE BIT(4)
1668 #define L2C_CBC_INT_MIBDBE BIT(5)
1670 #define L2C_CBC_INT_MIB (L2C_CBC_INT_MIBSBE | L2C_CBC_INT_MIBDBE)
1672 #define L2C_CBC_INT_IORDDISOCI BIT(6)
1673 #define L2C_CBC_INT_IOWRDISOCI BIT(7)
1675 #define L2C_CBC_INT_IODISOCI (L2C_CBC_INT_IORDDISOCI | \
1676 L2C_CBC_INT_IOWRDISOCI)
1678 #define L2C_CBC_INT_CE (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_MIBSBE)
1679 #define L2C_CBC_INT_UE (L2C_CBC_INT_RSDDBE | L2C_CBC_INT_MIBDBE)
1682 static const struct error_descr l2_cbc_errors
[] = {
1684 .type
= ERR_CORRECTED
,
1685 .mask
= L2C_CBC_INT_RSDSBE
,
1686 .descr
= "RSD single-bit error",
1689 .type
= ERR_CORRECTED
,
1690 .mask
= L2C_CBC_INT_MIBSBE
,
1691 .descr
= "MIB single-bit error",
1694 .type
= ERR_UNCORRECTED
,
1695 .mask
= L2C_CBC_INT_RSDDBE
,
1696 .descr
= "RSD double-bit error",
1699 .type
= ERR_UNCORRECTED
,
1700 .mask
= L2C_CBC_INT_MIBDBE
,
1701 .descr
= "MIB double-bit error",
1704 .type
= ERR_UNCORRECTED
,
1705 .mask
= L2C_CBC_INT_IORDDISOCI
,
1706 .descr
= "Read from a disabled CCPI",
1709 .type
= ERR_UNCORRECTED
,
1710 .mask
= L2C_CBC_INT_IOWRDISOCI
,
1711 .descr
= "Write to a disabled CCPI",
1716 #define L2C_CBC_INT_W1S 0x60008
1717 #define L2C_CBC_INT_ENA_W1C 0x60020
1719 #define L2C_CBC_INT_ENA_ALL (L2C_CBC_INT_RSD | L2C_CBC_INT_MIB | \
1720 L2C_CBC_INT_IODISOCI)
1722 #define L2C_CBC_INT_ENA_W1S 0x60028
1724 #define L2C_CBC_IODISOCIERR 0x80008
1725 #define L2C_CBC_IOCERR 0x80010
1726 #define L2C_CBC_RSDERR 0x80018
1727 #define L2C_CBC_MIBERR 0x80020
1730 #define L2C_MCI_INT_W1C 0x0
1732 #define L2C_MCI_INT_VBFSBE BIT(0)
1733 #define L2C_MCI_INT_VBFDBE BIT(1)
1735 static const struct error_descr l2_mci_errors
[] = {
1737 .type
= ERR_CORRECTED
,
1738 .mask
= L2C_MCI_INT_VBFSBE
,
1739 .descr
= "VBF single-bit error",
1742 .type
= ERR_UNCORRECTED
,
1743 .mask
= L2C_MCI_INT_VBFDBE
,
1744 .descr
= "VBF double-bit error",
1749 #define L2C_MCI_INT_W1S 0x8
1750 #define L2C_MCI_INT_ENA_W1C 0x20
1752 #define L2C_MCI_INT_ENA_ALL (L2C_MCI_INT_VBFSBE | L2C_MCI_INT_VBFDBE)
1754 #define L2C_MCI_INT_ENA_W1S 0x28
1756 #define L2C_MCI_ERR 0x10000
1758 #define L2C_MESSAGE_SIZE SZ_1K
1759 #define L2C_OTHER_SIZE (50 * ARRAY_SIZE(l2_tad_errors))
1761 struct l2c_err_ctx
{
1767 struct thunderx_l2c
{
1769 struct pci_dev
*pdev
;
1770 struct edac_device_ctl_info
*edac_dev
;
1772 struct dentry
*debugfs
;
1776 struct msix_entry msix_ent
;
1778 struct l2c_err_ctx err_ctx
[RING_ENTRIES
];
1779 unsigned long ring_head
;
1780 unsigned long ring_tail
;
1783 static irqreturn_t
thunderx_l2c_tad_isr(int irq
, void *irq_id
)
1785 struct msix_entry
*msix
= irq_id
;
1786 struct thunderx_l2c
*tad
= container_of(msix
, struct thunderx_l2c
,
1789 unsigned long head
= ring_pos(tad
->ring_head
, ARRAY_SIZE(tad
->err_ctx
));
1790 struct l2c_err_ctx
*ctx
= &tad
->err_ctx
[head
];
1792 ctx
->reg_int
= readq(tad
->regs
+ L2C_TAD_INT_W1C
);
1794 if (ctx
->reg_int
& L2C_TAD_INT_ECC
) {
1795 ctx
->reg_ext_name
= "TQD_ERR";
1796 ctx
->reg_ext
= readq(tad
->regs
+ L2C_TAD_TQD_ERR
);
1797 } else if (ctx
->reg_int
& L2C_TAD_INT_TAG
) {
1798 ctx
->reg_ext_name
= "TTG_ERR";
1799 ctx
->reg_ext
= readq(tad
->regs
+ L2C_TAD_TTG_ERR
);
1800 } else if (ctx
->reg_int
& L2C_TAD_INT_LFBTO
) {
1801 ctx
->reg_ext_name
= "TIMEOUT";
1802 ctx
->reg_ext
= readq(tad
->regs
+ L2C_TAD_TIMEOUT
);
1803 } else if (ctx
->reg_int
& L2C_TAD_INT_DISOCI
) {
1804 ctx
->reg_ext_name
= "ERR";
1805 ctx
->reg_ext
= readq(tad
->regs
+ L2C_TAD_ERR
);
1808 writeq(ctx
->reg_int
, tad
->regs
+ L2C_TAD_INT_W1C
);
1812 return IRQ_WAKE_THREAD
;
1815 static irqreturn_t
thunderx_l2c_cbc_isr(int irq
, void *irq_id
)
1817 struct msix_entry
*msix
= irq_id
;
1818 struct thunderx_l2c
*cbc
= container_of(msix
, struct thunderx_l2c
,
1821 unsigned long head
= ring_pos(cbc
->ring_head
, ARRAY_SIZE(cbc
->err_ctx
));
1822 struct l2c_err_ctx
*ctx
= &cbc
->err_ctx
[head
];
1824 ctx
->reg_int
= readq(cbc
->regs
+ L2C_CBC_INT_W1C
);
1826 if (ctx
->reg_int
& L2C_CBC_INT_RSD
) {
1827 ctx
->reg_ext_name
= "RSDERR";
1828 ctx
->reg_ext
= readq(cbc
->regs
+ L2C_CBC_RSDERR
);
1829 } else if (ctx
->reg_int
& L2C_CBC_INT_MIB
) {
1830 ctx
->reg_ext_name
= "MIBERR";
1831 ctx
->reg_ext
= readq(cbc
->regs
+ L2C_CBC_MIBERR
);
1832 } else if (ctx
->reg_int
& L2C_CBC_INT_IODISOCI
) {
1833 ctx
->reg_ext_name
= "IODISOCIERR";
1834 ctx
->reg_ext
= readq(cbc
->regs
+ L2C_CBC_IODISOCIERR
);
1837 writeq(ctx
->reg_int
, cbc
->regs
+ L2C_CBC_INT_W1C
);
1841 return IRQ_WAKE_THREAD
;
1844 static irqreturn_t
thunderx_l2c_mci_isr(int irq
, void *irq_id
)
1846 struct msix_entry
*msix
= irq_id
;
1847 struct thunderx_l2c
*mci
= container_of(msix
, struct thunderx_l2c
,
1850 unsigned long head
= ring_pos(mci
->ring_head
, ARRAY_SIZE(mci
->err_ctx
));
1851 struct l2c_err_ctx
*ctx
= &mci
->err_ctx
[head
];
1853 ctx
->reg_int
= readq(mci
->regs
+ L2C_MCI_INT_W1C
);
1854 ctx
->reg_ext
= readq(mci
->regs
+ L2C_MCI_ERR
);
1856 writeq(ctx
->reg_int
, mci
->regs
+ L2C_MCI_INT_W1C
);
1858 ctx
->reg_ext_name
= "ERR";
1862 return IRQ_WAKE_THREAD
;
1865 static irqreturn_t
thunderx_l2c_threaded_isr(int irq
, void *irq_id
)
1867 struct msix_entry
*msix
= irq_id
;
1868 struct thunderx_l2c
*l2c
= container_of(msix
, struct thunderx_l2c
,
1871 unsigned long tail
= ring_pos(l2c
->ring_tail
, ARRAY_SIZE(l2c
->err_ctx
));
1872 struct l2c_err_ctx
*ctx
= &l2c
->err_ctx
[tail
];
1873 irqreturn_t ret
= IRQ_NONE
;
1875 u64 mask_ue
, mask_ce
;
1876 const struct error_descr
*l2_errors
;
1882 msg
= kmalloc(OCX_MESSAGE_SIZE
, GFP_KERNEL
);
1883 other
= kmalloc(OCX_OTHER_SIZE
, GFP_KERNEL
);
1888 switch (l2c
->pdev
->device
) {
1889 case PCI_DEVICE_ID_THUNDER_L2C_TAD
:
1890 reg_int_name
= "L2C_TAD_INT";
1891 mask_ue
= L2C_TAD_INT_UE
;
1892 mask_ce
= L2C_TAD_INT_CE
;
1893 l2_errors
= l2_tad_errors
;
1895 case PCI_DEVICE_ID_THUNDER_L2C_CBC
:
1896 reg_int_name
= "L2C_CBC_INT";
1897 mask_ue
= L2C_CBC_INT_UE
;
1898 mask_ce
= L2C_CBC_INT_CE
;
1899 l2_errors
= l2_cbc_errors
;
1901 case PCI_DEVICE_ID_THUNDER_L2C_MCI
:
1902 reg_int_name
= "L2C_MCI_INT";
1903 mask_ue
= L2C_MCI_INT_VBFDBE
;
1904 mask_ce
= L2C_MCI_INT_VBFSBE
;
1905 l2_errors
= l2_mci_errors
;
1908 dev_err(&l2c
->pdev
->dev
, "Unsupported device: %04x\n",
1913 while (CIRC_CNT(l2c
->ring_head
, l2c
->ring_tail
,
1914 ARRAY_SIZE(l2c
->err_ctx
))) {
1915 snprintf(msg
, L2C_MESSAGE_SIZE
,
1916 "%s: %s: %016llx, %s: %016llx",
1917 l2c
->edac_dev
->ctl_name
, reg_int_name
, ctx
->reg_int
,
1918 ctx
->reg_ext_name
, ctx
->reg_ext
);
1920 decode_register(other
, L2C_OTHER_SIZE
, l2_errors
, ctx
->reg_int
);
1922 strncat(msg
, other
, L2C_MESSAGE_SIZE
);
1924 if (ctx
->reg_int
& mask_ue
)
1925 edac_device_handle_ue(l2c
->edac_dev
, 0, 0, msg
);
1926 else if (ctx
->reg_int
& mask_ce
)
1927 edac_device_handle_ce(l2c
->edac_dev
, 0, 0, msg
);
1941 #define L2C_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(l2c, _name, _reg)
1943 L2C_DEBUGFS_ATTR(tad_int
, L2C_TAD_INT_W1S
);
1945 struct debugfs_entry
*l2c_tad_dfs_ents
[] = {
1949 L2C_DEBUGFS_ATTR(cbc_int
, L2C_CBC_INT_W1S
);
1951 struct debugfs_entry
*l2c_cbc_dfs_ents
[] = {
1955 L2C_DEBUGFS_ATTR(mci_int
, L2C_MCI_INT_W1S
);
1957 struct debugfs_entry
*l2c_mci_dfs_ents
[] = {
1961 static const struct pci_device_id thunderx_l2c_pci_tbl
[] = {
1962 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_L2C_TAD
), },
1963 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_L2C_CBC
), },
1964 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_L2C_MCI
), },
1968 static int thunderx_l2c_probe(struct pci_dev
*pdev
,
1969 const struct pci_device_id
*id
)
1971 struct thunderx_l2c
*l2c
;
1972 struct edac_device_ctl_info
*edac_dev
;
1973 struct debugfs_entry
**l2c_devattr
;
1975 irqreturn_t (*thunderx_l2c_isr
)(int, void *) = NULL
;
1978 u64 reg_en_offs
, reg_en_mask
;
1982 ret
= pcim_enable_device(pdev
);
1984 dev_err(&pdev
->dev
, "Cannot enable PCI device: %d\n", ret
);
1988 ret
= pcim_iomap_regions(pdev
, BIT(0), "thunderx_l2c");
1990 dev_err(&pdev
->dev
, "Cannot map PCI resources: %d\n", ret
);
1994 switch (pdev
->device
) {
1995 case PCI_DEVICE_ID_THUNDER_L2C_TAD
:
1996 thunderx_l2c_isr
= thunderx_l2c_tad_isr
;
1997 l2c_devattr
= l2c_tad_dfs_ents
;
1998 dfs_entries
= ARRAY_SIZE(l2c_tad_dfs_ents
);
2000 reg_en_offs
= L2C_TAD_INT_ENA_W1S
;
2001 reg_en_mask
= L2C_TAD_INT_ENA_ALL
;
2003 case PCI_DEVICE_ID_THUNDER_L2C_CBC
:
2004 thunderx_l2c_isr
= thunderx_l2c_cbc_isr
;
2005 l2c_devattr
= l2c_cbc_dfs_ents
;
2006 dfs_entries
= ARRAY_SIZE(l2c_cbc_dfs_ents
);
2008 reg_en_offs
= L2C_CBC_INT_ENA_W1S
;
2009 reg_en_mask
= L2C_CBC_INT_ENA_ALL
;
2011 case PCI_DEVICE_ID_THUNDER_L2C_MCI
:
2012 thunderx_l2c_isr
= thunderx_l2c_mci_isr
;
2013 l2c_devattr
= l2c_mci_dfs_ents
;
2014 dfs_entries
= ARRAY_SIZE(l2c_mci_dfs_ents
);
2016 reg_en_offs
= L2C_MCI_INT_ENA_W1S
;
2017 reg_en_mask
= L2C_MCI_INT_ENA_ALL
;
2020 //Should never ever get here
2021 dev_err(&pdev
->dev
, "Unsupported PCI device: %04x\n",
2026 idx
= edac_device_alloc_index();
2027 snprintf(name
, sizeof(name
), fmt
, idx
);
2029 edac_dev
= edac_device_alloc_ctl_info(sizeof(struct thunderx_l2c
),
2030 name
, 1, "L2C", 1, 0,
2033 dev_err(&pdev
->dev
, "Cannot allocate EDAC device\n");
2037 l2c
= edac_dev
->pvt_info
;
2038 l2c
->edac_dev
= edac_dev
;
2040 l2c
->regs
= pcim_iomap_table(pdev
)[0];
2042 dev_err(&pdev
->dev
, "Cannot map PCI resources\n");
2052 l2c
->msix_ent
.entry
= 0;
2053 l2c
->msix_ent
.vector
= 0;
2055 ret
= pci_enable_msix_exact(pdev
, &l2c
->msix_ent
, 1);
2057 dev_err(&pdev
->dev
, "Cannot enable interrupt: %d\n", ret
);
2061 ret
= devm_request_threaded_irq(&pdev
->dev
, l2c
->msix_ent
.vector
,
2063 thunderx_l2c_threaded_isr
,
2064 0, "[EDAC] ThunderX L2C",
2069 edac_dev
->dev
= &pdev
->dev
;
2070 edac_dev
->dev_name
= dev_name(&pdev
->dev
);
2071 edac_dev
->mod_name
= "thunderx-l2c";
2072 edac_dev
->ctl_name
= "thunderx-l2c";
2074 ret
= edac_device_add_device(edac_dev
);
2076 dev_err(&pdev
->dev
, "Cannot add EDAC device: %d\n", ret
);
2080 if (IS_ENABLED(CONFIG_EDAC_DEBUG
)) {
2081 l2c
->debugfs
= edac_debugfs_create_dir(pdev
->dev
.kobj
.name
);
2083 ret
= thunderx_create_debugfs_nodes(l2c
->debugfs
, l2c_devattr
,
2086 if (ret
!= dfs_entries
) {
2087 dev_warn(&pdev
->dev
, "Error creating debugfs entries: %d%s\n",
2088 ret
, ret
>= 0 ? " created" : "");
2092 pci_set_drvdata(pdev
, edac_dev
);
2094 writeq(reg_en_mask
, l2c
->regs
+ reg_en_offs
);
2099 edac_device_free_ctl_info(edac_dev
);
2104 static void thunderx_l2c_remove(struct pci_dev
*pdev
)
2106 struct edac_device_ctl_info
*edac_dev
= pci_get_drvdata(pdev
);
2107 struct thunderx_l2c
*l2c
= edac_dev
->pvt_info
;
2109 switch (pdev
->device
) {
2110 case PCI_DEVICE_ID_THUNDER_L2C_TAD
:
2111 writeq(L2C_TAD_INT_ENA_ALL
, l2c
->regs
+ L2C_TAD_INT_ENA_W1C
);
2113 case PCI_DEVICE_ID_THUNDER_L2C_CBC
:
2114 writeq(L2C_CBC_INT_ENA_ALL
, l2c
->regs
+ L2C_CBC_INT_ENA_W1C
);
2116 case PCI_DEVICE_ID_THUNDER_L2C_MCI
:
2117 writeq(L2C_MCI_INT_ENA_ALL
, l2c
->regs
+ L2C_MCI_INT_ENA_W1C
);
2121 edac_debugfs_remove_recursive(l2c
->debugfs
);
2123 edac_device_del_device(&pdev
->dev
);
2124 edac_device_free_ctl_info(edac_dev
);
2127 MODULE_DEVICE_TABLE(pci
, thunderx_l2c_pci_tbl
);
2129 static struct pci_driver thunderx_l2c_driver
= {
2130 .name
= "thunderx_l2c_edac",
2131 .probe
= thunderx_l2c_probe
,
2132 .remove
= thunderx_l2c_remove
,
2133 .id_table
= thunderx_l2c_pci_tbl
,
2136 static int __init
thunderx_edac_init(void)
2140 rc
= pci_register_driver(&thunderx_lmc_driver
);
2144 rc
= pci_register_driver(&thunderx_ocx_driver
);
2148 rc
= pci_register_driver(&thunderx_l2c_driver
);
2154 pci_unregister_driver(&thunderx_ocx_driver
);
2156 pci_unregister_driver(&thunderx_lmc_driver
);
2161 static void __exit
thunderx_edac_exit(void)
2163 pci_unregister_driver(&thunderx_l2c_driver
);
2164 pci_unregister_driver(&thunderx_ocx_driver
);
2165 pci_unregister_driver(&thunderx_lmc_driver
);
2169 module_init(thunderx_edac_init
);
2170 module_exit(thunderx_edac_exit
);
2172 MODULE_LICENSE("GPL v2");
2173 MODULE_AUTHOR("Cavium, Inc.");
2174 MODULE_DESCRIPTION("EDAC Driver for Cavium ThunderX");