2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/spinlock.h>
34 #include <asm/system.h>
36 #ifdef CONFIG_PPC_PMAC
37 #include <asm/pmac_feature.h>
41 #include "fw-transaction.h"
43 #define DESCRIPTOR_OUTPUT_MORE 0
44 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
45 #define DESCRIPTOR_INPUT_MORE (2 << 12)
46 #define DESCRIPTOR_INPUT_LAST (3 << 12)
47 #define DESCRIPTOR_STATUS (1 << 11)
48 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
49 #define DESCRIPTOR_PING (1 << 7)
50 #define DESCRIPTOR_YY (1 << 6)
51 #define DESCRIPTOR_NO_IRQ (0 << 4)
52 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
53 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
54 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
55 #define DESCRIPTOR_WAIT (3 << 0)
61 __le32 branch_address
;
63 __le16 transfer_status
;
64 } __attribute__((aligned(16)));
66 struct db_descriptor
{
69 __le16 second_req_count
;
70 __le16 first_req_count
;
71 __le32 branch_address
;
72 __le16 second_res_count
;
73 __le16 first_res_count
;
78 } __attribute__((aligned(16)));
80 #define CONTROL_SET(regs) (regs)
81 #define CONTROL_CLEAR(regs) ((regs) + 4)
82 #define COMMAND_PTR(regs) ((regs) + 12)
83 #define CONTEXT_MATCH(regs) ((regs) + 16)
86 struct descriptor descriptor
;
87 struct ar_buffer
*next
;
93 struct ar_buffer
*current_buffer
;
94 struct ar_buffer
*last_buffer
;
97 struct tasklet_struct tasklet
;
102 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
103 struct descriptor
*d
,
104 struct descriptor
*last
);
107 * A buffer that contains a block of DMA-able coherent memory used for
108 * storing a portion of a DMA descriptor program.
110 struct descriptor_buffer
{
111 struct list_head list
;
112 dma_addr_t buffer_bus
;
115 struct descriptor buffer
[0];
119 struct fw_ohci
*ohci
;
121 int total_allocation
;
124 * List of page-sized buffers for storing DMA descriptors.
125 * Head of list contains buffers in use and tail of list contains
128 struct list_head buffer_list
;
131 * Pointer to a buffer inside buffer_list that contains the tail
132 * end of the current DMA program.
134 struct descriptor_buffer
*buffer_tail
;
137 * The descriptor containing the branch address of the first
138 * descriptor that has not yet been filled by the device.
140 struct descriptor
*last
;
143 * The last descriptor in the DMA program. It contains the branch
144 * address that must be updated upon appending a new descriptor.
146 struct descriptor
*prev
;
148 descriptor_callback_t callback
;
150 struct tasklet_struct tasklet
;
153 #define IT_HEADER_SY(v) ((v) << 0)
154 #define IT_HEADER_TCODE(v) ((v) << 4)
155 #define IT_HEADER_CHANNEL(v) ((v) << 8)
156 #define IT_HEADER_TAG(v) ((v) << 14)
157 #define IT_HEADER_SPEED(v) ((v) << 16)
158 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
161 struct fw_iso_context base
;
162 struct context context
;
165 size_t header_length
;
168 #define CONFIG_ROM_SIZE 1024
174 __iomem
char *registers
;
175 dma_addr_t self_id_bus
;
177 struct tasklet_struct bus_reset_tasklet
;
180 int request_generation
;
185 * Spinlock for accessing fw_ohci data. Never call out of
186 * this driver with this lock held.
189 u32 self_id_buffer
[512];
191 /* Config rom buffers */
193 dma_addr_t config_rom_bus
;
194 __be32
*next_config_rom
;
195 dma_addr_t next_config_rom_bus
;
198 struct ar_context ar_request_ctx
;
199 struct ar_context ar_response_ctx
;
200 struct context at_request_ctx
;
201 struct context at_response_ctx
;
204 struct iso_context
*it_context_list
;
206 struct iso_context
*ir_context_list
;
209 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
211 return container_of(card
, struct fw_ohci
, card
);
214 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
215 #define IR_CONTEXT_BUFFER_FILL 0x80000000
216 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
217 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
218 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
219 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
221 #define CONTEXT_RUN 0x8000
222 #define CONTEXT_WAKE 0x1000
223 #define CONTEXT_DEAD 0x0800
224 #define CONTEXT_ACTIVE 0x0400
226 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
227 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
228 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
230 #define FW_OHCI_MAJOR 240
231 #define OHCI1394_REGISTER_SIZE 0x800
232 #define OHCI_LOOP_COUNT 500
233 #define OHCI1394_PCI_HCI_Control 0x40
234 #define SELF_ID_BUF_SIZE 0x800
235 #define OHCI_TCODE_PHY_PACKET 0x0e
236 #define OHCI_VERSION_1_1 0x010010
238 static char ohci_driver_name
[] = KBUILD_MODNAME
;
240 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
242 writel(data
, ohci
->registers
+ offset
);
245 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
247 return readl(ohci
->registers
+ offset
);
250 static inline void flush_writes(const struct fw_ohci
*ohci
)
252 /* Do a dummy read to flush writes. */
253 reg_read(ohci
, OHCI1394_Version
);
257 ohci_update_phy_reg(struct fw_card
*card
, int addr
,
258 int clear_bits
, int set_bits
)
260 struct fw_ohci
*ohci
= fw_ohci(card
);
263 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
266 val
= reg_read(ohci
, OHCI1394_PhyControl
);
267 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
268 fw_error("failed to set phy reg bits.\n");
272 old
= OHCI1394_PhyControl_ReadData(val
);
273 old
= (old
& ~clear_bits
) | set_bits
;
274 reg_write(ohci
, OHCI1394_PhyControl
,
275 OHCI1394_PhyControl_Write(addr
, old
));
280 static int ar_context_add_page(struct ar_context
*ctx
)
282 struct device
*dev
= ctx
->ohci
->card
.device
;
283 struct ar_buffer
*ab
;
284 dma_addr_t
uninitialized_var(ab_bus
);
287 ab
= dma_alloc_coherent(dev
, PAGE_SIZE
, &ab_bus
, GFP_ATOMIC
);
291 memset(&ab
->descriptor
, 0, sizeof(ab
->descriptor
));
292 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
294 DESCRIPTOR_BRANCH_ALWAYS
);
295 offset
= offsetof(struct ar_buffer
, data
);
296 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
297 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
298 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
299 ab
->descriptor
.branch_address
= 0;
301 ctx
->last_buffer
->descriptor
.branch_address
= cpu_to_le32(ab_bus
| 1);
302 ctx
->last_buffer
->next
= ab
;
303 ctx
->last_buffer
= ab
;
305 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
306 flush_writes(ctx
->ohci
);
311 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
312 #define cond_le32_to_cpu(v) \
313 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
315 #define cond_le32_to_cpu(v) le32_to_cpu(v)
318 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
320 struct fw_ohci
*ohci
= ctx
->ohci
;
322 u32 status
, length
, tcode
;
324 p
.header
[0] = cond_le32_to_cpu(buffer
[0]);
325 p
.header
[1] = cond_le32_to_cpu(buffer
[1]);
326 p
.header
[2] = cond_le32_to_cpu(buffer
[2]);
328 tcode
= (p
.header
[0] >> 4) & 0x0f;
330 case TCODE_WRITE_QUADLET_REQUEST
:
331 case TCODE_READ_QUADLET_RESPONSE
:
332 p
.header
[3] = (__force __u32
) buffer
[3];
333 p
.header_length
= 16;
334 p
.payload_length
= 0;
337 case TCODE_READ_BLOCK_REQUEST
:
338 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
339 p
.header_length
= 16;
340 p
.payload_length
= 0;
343 case TCODE_WRITE_BLOCK_REQUEST
:
344 case TCODE_READ_BLOCK_RESPONSE
:
345 case TCODE_LOCK_REQUEST
:
346 case TCODE_LOCK_RESPONSE
:
347 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
348 p
.header_length
= 16;
349 p
.payload_length
= p
.header
[3] >> 16;
352 case TCODE_WRITE_RESPONSE
:
353 case TCODE_READ_QUADLET_REQUEST
:
354 case OHCI_TCODE_PHY_PACKET
:
355 p
.header_length
= 12;
356 p
.payload_length
= 0;
360 p
.payload
= (void *) buffer
+ p
.header_length
;
362 /* FIXME: What to do about evt_* errors? */
363 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
364 status
= cond_le32_to_cpu(buffer
[length
]);
366 p
.ack
= ((status
>> 16) & 0x1f) - 16;
367 p
.speed
= (status
>> 21) & 0x7;
368 p
.timestamp
= status
& 0xffff;
369 p
.generation
= ohci
->request_generation
;
372 * The OHCI bus reset handler synthesizes a phy packet with
373 * the new generation number when a bus reset happens (see
374 * section 8.4.2.3). This helps us determine when a request
375 * was received and make sure we send the response in the same
376 * generation. We only need this for requests; for responses
377 * we use the unique tlabel for finding the matching
381 if (p
.ack
+ 16 == 0x09)
382 ohci
->request_generation
= (p
.header
[2] >> 16) & 0xff;
383 else if (ctx
== &ohci
->ar_request_ctx
)
384 fw_core_handle_request(&ohci
->card
, &p
);
386 fw_core_handle_response(&ohci
->card
, &p
);
388 return buffer
+ length
+ 1;
391 static void ar_context_tasklet(unsigned long data
)
393 struct ar_context
*ctx
= (struct ar_context
*)data
;
394 struct fw_ohci
*ohci
= ctx
->ohci
;
395 struct ar_buffer
*ab
;
396 struct descriptor
*d
;
399 ab
= ctx
->current_buffer
;
402 if (d
->res_count
== 0) {
403 size_t size
, rest
, offset
;
404 dma_addr_t start_bus
;
408 * This descriptor is finished and we may have a
409 * packet split across this and the next buffer. We
410 * reuse the page for reassembling the split packet.
413 offset
= offsetof(struct ar_buffer
, data
);
415 start_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
419 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
420 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
421 memmove(buffer
, ctx
->pointer
, size
);
422 memcpy(buffer
+ size
, ab
->data
, rest
);
423 ctx
->current_buffer
= ab
;
424 ctx
->pointer
= (void *) ab
->data
+ rest
;
425 end
= buffer
+ size
+ rest
;
428 buffer
= handle_ar_packet(ctx
, buffer
);
430 dma_free_coherent(ohci
->card
.device
, PAGE_SIZE
,
432 ar_context_add_page(ctx
);
434 buffer
= ctx
->pointer
;
436 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
439 buffer
= handle_ar_packet(ctx
, buffer
);
444 ar_context_init(struct ar_context
*ctx
, struct fw_ohci
*ohci
, u32 regs
)
450 ctx
->last_buffer
= &ab
;
451 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
453 ar_context_add_page(ctx
);
454 ar_context_add_page(ctx
);
455 ctx
->current_buffer
= ab
.next
;
456 ctx
->pointer
= ctx
->current_buffer
->data
;
461 static void ar_context_run(struct ar_context
*ctx
)
463 struct ar_buffer
*ab
= ctx
->current_buffer
;
467 offset
= offsetof(struct ar_buffer
, data
);
468 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
470 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab_bus
| 1);
471 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
472 flush_writes(ctx
->ohci
);
475 static struct descriptor
*
476 find_branch_descriptor(struct descriptor
*d
, int z
)
480 b
= (le16_to_cpu(d
->control
) & DESCRIPTOR_BRANCH_ALWAYS
) >> 2;
481 key
= (le16_to_cpu(d
->control
) & DESCRIPTOR_KEY_IMMEDIATE
) >> 8;
483 /* figure out which descriptor the branch address goes in */
484 if (z
== 2 && (b
== 3 || key
== 2))
490 static void context_tasklet(unsigned long data
)
492 struct context
*ctx
= (struct context
*) data
;
493 struct descriptor
*d
, *last
;
496 struct descriptor_buffer
*desc
;
498 desc
= list_entry(ctx
->buffer_list
.next
,
499 struct descriptor_buffer
, list
);
501 while (last
->branch_address
!= 0) {
502 struct descriptor_buffer
*old_desc
= desc
;
503 address
= le32_to_cpu(last
->branch_address
);
507 /* If the branch address points to a buffer outside of the
508 * current buffer, advance to the next buffer. */
509 if (address
< desc
->buffer_bus
||
510 address
>= desc
->buffer_bus
+ desc
->used
)
511 desc
= list_entry(desc
->list
.next
,
512 struct descriptor_buffer
, list
);
513 d
= desc
->buffer
+ (address
- desc
->buffer_bus
) / sizeof(*d
);
514 last
= find_branch_descriptor(d
, z
);
516 if (!ctx
->callback(ctx
, d
, last
))
519 if (old_desc
!= desc
) {
520 /* If we've advanced to the next buffer, move the
521 * previous buffer to the free list. */
524 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
525 list_move_tail(&old_desc
->list
, &ctx
->buffer_list
);
526 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
533 * Allocate a new buffer and add it to the list of free buffers for this
534 * context. Must be called with ohci->lock held.
537 context_add_buffer(struct context
*ctx
)
539 struct descriptor_buffer
*desc
;
540 dma_addr_t
uninitialized_var(bus_addr
);
544 * 16MB of descriptors should be far more than enough for any DMA
545 * program. This will catch run-away userspace or DoS attacks.
547 if (ctx
->total_allocation
>= 16*1024*1024)
550 desc
= dma_alloc_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
551 &bus_addr
, GFP_ATOMIC
);
555 offset
= (void *)&desc
->buffer
- (void *)desc
;
556 desc
->buffer_size
= PAGE_SIZE
- offset
;
557 desc
->buffer_bus
= bus_addr
+ offset
;
560 list_add_tail(&desc
->list
, &ctx
->buffer_list
);
561 ctx
->total_allocation
+= PAGE_SIZE
;
567 context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
568 u32 regs
, descriptor_callback_t callback
)
572 ctx
->total_allocation
= 0;
574 INIT_LIST_HEAD(&ctx
->buffer_list
);
575 if (context_add_buffer(ctx
) < 0)
578 ctx
->buffer_tail
= list_entry(ctx
->buffer_list
.next
,
579 struct descriptor_buffer
, list
);
581 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
582 ctx
->callback
= callback
;
585 * We put a dummy descriptor in the buffer that has a NULL
586 * branch address and looks like it's been sent. That way we
587 * have a descriptor to append DMA programs to.
589 memset(ctx
->buffer_tail
->buffer
, 0, sizeof(*ctx
->buffer_tail
->buffer
));
590 ctx
->buffer_tail
->buffer
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
591 ctx
->buffer_tail
->buffer
->transfer_status
= cpu_to_le16(0x8011);
592 ctx
->buffer_tail
->used
+= sizeof(*ctx
->buffer_tail
->buffer
);
593 ctx
->last
= ctx
->buffer_tail
->buffer
;
594 ctx
->prev
= ctx
->buffer_tail
->buffer
;
600 context_release(struct context
*ctx
)
602 struct fw_card
*card
= &ctx
->ohci
->card
;
603 struct descriptor_buffer
*desc
, *tmp
;
605 list_for_each_entry_safe(desc
, tmp
, &ctx
->buffer_list
, list
)
606 dma_free_coherent(card
->device
, PAGE_SIZE
, desc
,
608 ((void *)&desc
->buffer
- (void *)desc
));
611 /* Must be called with ohci->lock held */
612 static struct descriptor
*
613 context_get_descriptors(struct context
*ctx
, int z
, dma_addr_t
*d_bus
)
615 struct descriptor
*d
= NULL
;
616 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
618 if (z
* sizeof(*d
) > desc
->buffer_size
)
621 if (z
* sizeof(*d
) > desc
->buffer_size
- desc
->used
) {
622 /* No room for the descriptor in this buffer, so advance to the
625 if (desc
->list
.next
== &ctx
->buffer_list
) {
626 /* If there is no free buffer next in the list,
628 if (context_add_buffer(ctx
) < 0)
631 desc
= list_entry(desc
->list
.next
,
632 struct descriptor_buffer
, list
);
633 ctx
->buffer_tail
= desc
;
636 d
= desc
->buffer
+ desc
->used
/ sizeof(*d
);
637 memset(d
, 0, z
* sizeof(*d
));
638 *d_bus
= desc
->buffer_bus
+ desc
->used
;
643 static void context_run(struct context
*ctx
, u32 extra
)
645 struct fw_ohci
*ohci
= ctx
->ohci
;
647 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
648 le32_to_cpu(ctx
->last
->branch_address
));
649 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
650 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
654 static void context_append(struct context
*ctx
,
655 struct descriptor
*d
, int z
, int extra
)
658 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
660 d_bus
= desc
->buffer_bus
+ (d
- desc
->buffer
) * sizeof(*d
);
662 desc
->used
+= (z
+ extra
) * sizeof(*d
);
663 ctx
->prev
->branch_address
= cpu_to_le32(d_bus
| z
);
664 ctx
->prev
= find_branch_descriptor(d
, z
);
666 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
667 flush_writes(ctx
->ohci
);
670 static void context_stop(struct context
*ctx
)
675 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
676 flush_writes(ctx
->ohci
);
678 for (i
= 0; i
< 10; i
++) {
679 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
680 if ((reg
& CONTEXT_ACTIVE
) == 0)
683 fw_notify("context_stop: still active (0x%08x)\n", reg
);
689 struct fw_packet
*packet
;
693 * This function apppends a packet to the DMA queue for transmission.
694 * Must always be called with the ochi->lock held to ensure proper
695 * generation handling and locking around packet queue manipulation.
698 at_context_queue_packet(struct context
*ctx
, struct fw_packet
*packet
)
700 struct fw_ohci
*ohci
= ctx
->ohci
;
701 dma_addr_t d_bus
, uninitialized_var(payload_bus
);
702 struct driver_data
*driver_data
;
703 struct descriptor
*d
, *last
;
708 d
= context_get_descriptors(ctx
, 4, &d_bus
);
710 packet
->ack
= RCODE_SEND_ERROR
;
714 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
715 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
718 * The DMA format for asyncronous link packets is different
719 * from the IEEE1394 layout, so shift the fields around
720 * accordingly. If header_length is 8, it's a PHY packet, to
721 * which we need to prepend an extra quadlet.
724 header
= (__le32
*) &d
[1];
725 if (packet
->header_length
> 8) {
726 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
727 (packet
->speed
<< 16));
728 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
729 (packet
->header
[0] & 0xffff0000));
730 header
[2] = cpu_to_le32(packet
->header
[2]);
732 tcode
= (packet
->header
[0] >> 4) & 0x0f;
733 if (TCODE_IS_BLOCK_PACKET(tcode
))
734 header
[3] = cpu_to_le32(packet
->header
[3]);
736 header
[3] = (__force __le32
) packet
->header
[3];
738 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
740 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
741 (packet
->speed
<< 16));
742 header
[1] = cpu_to_le32(packet
->header
[0]);
743 header
[2] = cpu_to_le32(packet
->header
[1]);
744 d
[0].req_count
= cpu_to_le16(12);
747 driver_data
= (struct driver_data
*) &d
[3];
748 driver_data
->packet
= packet
;
749 packet
->driver_data
= driver_data
;
751 if (packet
->payload_length
> 0) {
753 dma_map_single(ohci
->card
.device
, packet
->payload
,
754 packet
->payload_length
, DMA_TO_DEVICE
);
755 if (dma_mapping_error(payload_bus
)) {
756 packet
->ack
= RCODE_SEND_ERROR
;
760 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
761 d
[2].data_address
= cpu_to_le32(payload_bus
);
769 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
770 DESCRIPTOR_IRQ_ALWAYS
|
771 DESCRIPTOR_BRANCH_ALWAYS
);
773 /* FIXME: Document how the locking works. */
774 if (ohci
->generation
!= packet
->generation
) {
775 if (packet
->payload_length
> 0)
776 dma_unmap_single(ohci
->card
.device
, payload_bus
,
777 packet
->payload_length
, DMA_TO_DEVICE
);
778 packet
->ack
= RCODE_GENERATION
;
782 context_append(ctx
, d
, z
, 4 - z
);
784 /* If the context isn't already running, start it up. */
785 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
786 if ((reg
& CONTEXT_RUN
) == 0)
792 static int handle_at_packet(struct context
*context
,
793 struct descriptor
*d
,
794 struct descriptor
*last
)
796 struct driver_data
*driver_data
;
797 struct fw_packet
*packet
;
798 struct fw_ohci
*ohci
= context
->ohci
;
799 dma_addr_t payload_bus
;
802 if (last
->transfer_status
== 0)
803 /* This descriptor isn't done yet, stop iteration. */
806 driver_data
= (struct driver_data
*) &d
[3];
807 packet
= driver_data
->packet
;
809 /* This packet was cancelled, just continue. */
812 payload_bus
= le32_to_cpu(last
->data_address
);
813 if (payload_bus
!= 0)
814 dma_unmap_single(ohci
->card
.device
, payload_bus
,
815 packet
->payload_length
, DMA_TO_DEVICE
);
817 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
818 packet
->timestamp
= le16_to_cpu(last
->res_count
);
821 case OHCI1394_evt_timeout
:
822 /* Async response transmit timed out. */
823 packet
->ack
= RCODE_CANCELLED
;
826 case OHCI1394_evt_flushed
:
828 * The packet was flushed should give same error as
829 * when we try to use a stale generation count.
831 packet
->ack
= RCODE_GENERATION
;
834 case OHCI1394_evt_missing_ack
:
836 * Using a valid (current) generation count, but the
837 * node is not on the bus or not sending acks.
839 packet
->ack
= RCODE_NO_ACK
;
842 case ACK_COMPLETE
+ 0x10:
843 case ACK_PENDING
+ 0x10:
844 case ACK_BUSY_X
+ 0x10:
845 case ACK_BUSY_A
+ 0x10:
846 case ACK_BUSY_B
+ 0x10:
847 case ACK_DATA_ERROR
+ 0x10:
848 case ACK_TYPE_ERROR
+ 0x10:
849 packet
->ack
= evt
- 0x10;
853 packet
->ack
= RCODE_SEND_ERROR
;
857 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
862 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
863 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
864 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
865 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
866 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
869 handle_local_rom(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
871 struct fw_packet response
;
872 int tcode
, length
, i
;
874 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
875 if (TCODE_IS_BLOCK_PACKET(tcode
))
876 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
880 i
= csr
- CSR_CONFIG_ROM
;
881 if (i
+ length
> CONFIG_ROM_SIZE
) {
882 fw_fill_response(&response
, packet
->header
,
883 RCODE_ADDRESS_ERROR
, NULL
, 0);
884 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
885 fw_fill_response(&response
, packet
->header
,
886 RCODE_TYPE_ERROR
, NULL
, 0);
888 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
889 (void *) ohci
->config_rom
+ i
, length
);
892 fw_core_handle_response(&ohci
->card
, &response
);
896 handle_local_lock(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
898 struct fw_packet response
;
899 int tcode
, length
, ext_tcode
, sel
;
900 __be32
*payload
, lock_old
;
901 u32 lock_arg
, lock_data
;
903 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
904 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
905 payload
= packet
->payload
;
906 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
908 if (tcode
== TCODE_LOCK_REQUEST
&&
909 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
910 lock_arg
= be32_to_cpu(payload
[0]);
911 lock_data
= be32_to_cpu(payload
[1]);
912 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
916 fw_fill_response(&response
, packet
->header
,
917 RCODE_TYPE_ERROR
, NULL
, 0);
921 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
922 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
923 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
924 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
926 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
927 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
929 fw_notify("swap not done yet\n");
931 fw_fill_response(&response
, packet
->header
,
932 RCODE_COMPLETE
, &lock_old
, sizeof(lock_old
));
934 fw_core_handle_response(&ohci
->card
, &response
);
938 handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
943 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
944 packet
->ack
= ACK_PENDING
;
945 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
949 ((unsigned long long)
950 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
952 csr
= offset
- CSR_REGISTER_BASE
;
954 /* Handle config rom reads. */
955 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
956 handle_local_rom(ctx
->ohci
, packet
, csr
);
958 case CSR_BUS_MANAGER_ID
:
959 case CSR_BANDWIDTH_AVAILABLE
:
960 case CSR_CHANNELS_AVAILABLE_HI
:
961 case CSR_CHANNELS_AVAILABLE_LO
:
962 handle_local_lock(ctx
->ohci
, packet
, csr
);
965 if (ctx
== &ctx
->ohci
->at_request_ctx
)
966 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
968 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
972 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
973 packet
->ack
= ACK_COMPLETE
;
974 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
979 at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
984 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
986 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
987 ctx
->ohci
->generation
== packet
->generation
) {
988 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
989 handle_local_request(ctx
, packet
);
993 retval
= at_context_queue_packet(ctx
, packet
);
994 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
997 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1001 static void bus_reset_tasklet(unsigned long data
)
1003 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
1004 int self_id_count
, i
, j
, reg
;
1005 int generation
, new_generation
;
1006 unsigned long flags
;
1007 void *free_rom
= NULL
;
1008 dma_addr_t free_rom_bus
= 0;
1010 reg
= reg_read(ohci
, OHCI1394_NodeID
);
1011 if (!(reg
& OHCI1394_NodeID_idValid
)) {
1012 fw_notify("node ID not valid, new bus reset in progress\n");
1015 if ((reg
& OHCI1394_NodeID_nodeNumber
) == 63) {
1016 fw_notify("malconfigured bus\n");
1019 ohci
->node_id
= reg
& (OHCI1394_NodeID_busNumber
|
1020 OHCI1394_NodeID_nodeNumber
);
1022 reg
= reg_read(ohci
, OHCI1394_SelfIDCount
);
1023 if (reg
& OHCI1394_SelfIDCount_selfIDError
) {
1024 fw_notify("inconsistent self IDs\n");
1028 * The count in the SelfIDCount register is the number of
1029 * bytes in the self ID receive buffer. Since we also receive
1030 * the inverted quadlets and a header quadlet, we shift one
1031 * bit extra to get the actual number of self IDs.
1033 self_id_count
= (reg
>> 3) & 0x3ff;
1034 if (self_id_count
== 0) {
1035 fw_notify("inconsistent self IDs\n");
1038 generation
= (cond_le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
1041 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
1042 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1]) {
1043 fw_notify("inconsistent self IDs\n");
1046 ohci
->self_id_buffer
[j
] =
1047 cond_le32_to_cpu(ohci
->self_id_cpu
[i
]);
1052 * Check the consistency of the self IDs we just read. The
1053 * problem we face is that a new bus reset can start while we
1054 * read out the self IDs from the DMA buffer. If this happens,
1055 * the DMA buffer will be overwritten with new self IDs and we
1056 * will read out inconsistent data. The OHCI specification
1057 * (section 11.2) recommends a technique similar to
1058 * linux/seqlock.h, where we remember the generation of the
1059 * self IDs in the buffer before reading them out and compare
1060 * it to the current generation after reading them out. If
1061 * the two generations match we know we have a consistent set
1065 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
1066 if (new_generation
!= generation
) {
1067 fw_notify("recursive bus reset detected, "
1068 "discarding self ids\n");
1072 /* FIXME: Document how the locking works. */
1073 spin_lock_irqsave(&ohci
->lock
, flags
);
1075 ohci
->generation
= generation
;
1076 context_stop(&ohci
->at_request_ctx
);
1077 context_stop(&ohci
->at_response_ctx
);
1078 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
1081 * This next bit is unrelated to the AT context stuff but we
1082 * have to do it under the spinlock also. If a new config rom
1083 * was set up before this reset, the old one is now no longer
1084 * in use and we can free it. Update the config rom pointers
1085 * to point to the current config rom and clear the
1086 * next_config_rom pointer so a new udpate can take place.
1089 if (ohci
->next_config_rom
!= NULL
) {
1090 if (ohci
->next_config_rom
!= ohci
->config_rom
) {
1091 free_rom
= ohci
->config_rom
;
1092 free_rom_bus
= ohci
->config_rom_bus
;
1094 ohci
->config_rom
= ohci
->next_config_rom
;
1095 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
1096 ohci
->next_config_rom
= NULL
;
1099 * Restore config_rom image and manually update
1100 * config_rom registers. Writing the header quadlet
1101 * will indicate that the config rom is ready, so we
1104 reg_write(ohci
, OHCI1394_BusOptions
,
1105 be32_to_cpu(ohci
->config_rom
[2]));
1106 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
1107 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
1110 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1111 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, ~0);
1112 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, ~0);
1115 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1118 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1119 free_rom
, free_rom_bus
);
1121 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
1122 self_id_count
, ohci
->self_id_buffer
);
1125 static irqreturn_t
irq_handler(int irq
, void *data
)
1127 struct fw_ohci
*ohci
= data
;
1128 u32 event
, iso_event
, cycle_time
;
1131 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
1133 if (!event
|| !~event
)
1136 reg_write(ohci
, OHCI1394_IntEventClear
, event
);
1138 if (event
& OHCI1394_selfIDComplete
)
1139 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1141 if (event
& OHCI1394_RQPkt
)
1142 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1144 if (event
& OHCI1394_RSPkt
)
1145 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1147 if (event
& OHCI1394_reqTxComplete
)
1148 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1150 if (event
& OHCI1394_respTxComplete
)
1151 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1153 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1154 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1157 i
= ffs(iso_event
) - 1;
1158 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1159 iso_event
&= ~(1 << i
);
1162 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1163 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1166 i
= ffs(iso_event
) - 1;
1167 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1168 iso_event
&= ~(1 << i
);
1171 if (unlikely(event
& OHCI1394_postedWriteErr
))
1172 fw_error("PCI posted write error\n");
1174 if (unlikely(event
& OHCI1394_cycleTooLong
)) {
1175 if (printk_ratelimit())
1176 fw_notify("isochronous cycle too long\n");
1177 reg_write(ohci
, OHCI1394_LinkControlSet
,
1178 OHCI1394_LinkControl_cycleMaster
);
1181 if (event
& OHCI1394_cycle64Seconds
) {
1182 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1183 if ((cycle_time
& 0x80000000) == 0)
1184 ohci
->bus_seconds
++;
1190 static int software_reset(struct fw_ohci
*ohci
)
1194 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1196 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1197 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1198 OHCI1394_HCControl_softReset
) == 0)
1206 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1208 struct fw_ohci
*ohci
= fw_ohci(card
);
1209 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1211 if (software_reset(ohci
)) {
1212 fw_error("Failed to reset ohci card.\n");
1217 * Now enable LPS, which we need in order to start accessing
1218 * most of the registers. In fact, on some cards (ALI M5251),
1219 * accessing registers in the SClk domain without LPS enabled
1220 * will lock up the machine. Wait 50msec to make sure we have
1221 * full link enabled.
1223 reg_write(ohci
, OHCI1394_HCControlSet
,
1224 OHCI1394_HCControl_LPS
|
1225 OHCI1394_HCControl_postedWriteEnable
);
1229 reg_write(ohci
, OHCI1394_HCControlClear
,
1230 OHCI1394_HCControl_noByteSwapData
);
1232 reg_write(ohci
, OHCI1394_LinkControlSet
,
1233 OHCI1394_LinkControl_rcvSelfID
|
1234 OHCI1394_LinkControl_cycleTimerEnable
|
1235 OHCI1394_LinkControl_cycleMaster
);
1237 reg_write(ohci
, OHCI1394_ATRetries
,
1238 OHCI1394_MAX_AT_REQ_RETRIES
|
1239 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1240 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1242 ar_context_run(&ohci
->ar_request_ctx
);
1243 ar_context_run(&ohci
->ar_response_ctx
);
1245 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1246 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1247 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1248 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1249 reg_write(ohci
, OHCI1394_IntMaskSet
,
1250 OHCI1394_selfIDComplete
|
1251 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1252 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1253 OHCI1394_isochRx
| OHCI1394_isochTx
|
1254 OHCI1394_postedWriteErr
| OHCI1394_cycleTooLong
|
1255 OHCI1394_cycle64Seconds
| OHCI1394_masterIntEnable
);
1257 /* Activate link_on bit and contender bit in our self ID packets.*/
1258 if (ohci_update_phy_reg(card
, 4, 0,
1259 PHY_LINK_ACTIVE
| PHY_CONTENDER
) < 0)
1263 * When the link is not yet enabled, the atomic config rom
1264 * update mechanism described below in ohci_set_config_rom()
1265 * is not active. We have to update ConfigRomHeader and
1266 * BusOptions manually, and the write to ConfigROMmap takes
1267 * effect immediately. We tie this to the enabling of the
1268 * link, so we have a valid config rom before enabling - the
1269 * OHCI requires that ConfigROMhdr and BusOptions have valid
1270 * values before enabling.
1272 * However, when the ConfigROMmap is written, some controllers
1273 * always read back quadlets 0 and 2 from the config rom to
1274 * the ConfigRomHeader and BusOptions registers on bus reset.
1275 * They shouldn't do that in this initial case where the link
1276 * isn't enabled. This means we have to use the same
1277 * workaround here, setting the bus header to 0 and then write
1278 * the right values in the bus reset tasklet.
1282 ohci
->next_config_rom
=
1283 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1284 &ohci
->next_config_rom_bus
,
1286 if (ohci
->next_config_rom
== NULL
)
1289 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1290 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
1293 * In the suspend case, config_rom is NULL, which
1294 * means that we just reuse the old config rom.
1296 ohci
->next_config_rom
= ohci
->config_rom
;
1297 ohci
->next_config_rom_bus
= ohci
->config_rom_bus
;
1300 ohci
->next_header
= be32_to_cpu(ohci
->next_config_rom
[0]);
1301 ohci
->next_config_rom
[0] = 0;
1302 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1303 reg_write(ohci
, OHCI1394_BusOptions
,
1304 be32_to_cpu(ohci
->next_config_rom
[2]));
1305 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1307 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1309 if (request_irq(dev
->irq
, irq_handler
,
1310 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1311 fw_error("Failed to allocate shared interrupt %d.\n",
1313 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1314 ohci
->config_rom
, ohci
->config_rom_bus
);
1318 reg_write(ohci
, OHCI1394_HCControlSet
,
1319 OHCI1394_HCControl_linkEnable
|
1320 OHCI1394_HCControl_BIBimageValid
);
1324 * We are ready to go, initiate bus reset to finish the
1328 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1334 ohci_set_config_rom(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1336 struct fw_ohci
*ohci
;
1337 unsigned long flags
;
1338 int retval
= -EBUSY
;
1339 __be32
*next_config_rom
;
1340 dma_addr_t
uninitialized_var(next_config_rom_bus
);
1342 ohci
= fw_ohci(card
);
1345 * When the OHCI controller is enabled, the config rom update
1346 * mechanism is a bit tricky, but easy enough to use. See
1347 * section 5.5.6 in the OHCI specification.
1349 * The OHCI controller caches the new config rom address in a
1350 * shadow register (ConfigROMmapNext) and needs a bus reset
1351 * for the changes to take place. When the bus reset is
1352 * detected, the controller loads the new values for the
1353 * ConfigRomHeader and BusOptions registers from the specified
1354 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1355 * shadow register. All automatically and atomically.
1357 * Now, there's a twist to this story. The automatic load of
1358 * ConfigRomHeader and BusOptions doesn't honor the
1359 * noByteSwapData bit, so with a be32 config rom, the
1360 * controller will load be32 values in to these registers
1361 * during the atomic update, even on litte endian
1362 * architectures. The workaround we use is to put a 0 in the
1363 * header quadlet; 0 is endian agnostic and means that the
1364 * config rom isn't ready yet. In the bus reset tasklet we
1365 * then set up the real values for the two registers.
1367 * We use ohci->lock to avoid racing with the code that sets
1368 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1372 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1373 &next_config_rom_bus
, GFP_KERNEL
);
1374 if (next_config_rom
== NULL
)
1377 spin_lock_irqsave(&ohci
->lock
, flags
);
1379 if (ohci
->next_config_rom
== NULL
) {
1380 ohci
->next_config_rom
= next_config_rom
;
1381 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1383 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1384 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
1387 ohci
->next_header
= config_rom
[0];
1388 ohci
->next_config_rom
[0] = 0;
1390 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1391 ohci
->next_config_rom_bus
);
1395 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1398 * Now initiate a bus reset to have the changes take
1399 * effect. We clean up the old config rom memory and DMA
1400 * mappings in the bus reset tasklet, since the OHCI
1401 * controller could need to access it before the bus reset
1405 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1407 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1408 next_config_rom
, next_config_rom_bus
);
1413 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1415 struct fw_ohci
*ohci
= fw_ohci(card
);
1417 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1420 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1422 struct fw_ohci
*ohci
= fw_ohci(card
);
1424 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1427 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1429 struct fw_ohci
*ohci
= fw_ohci(card
);
1430 struct context
*ctx
= &ohci
->at_request_ctx
;
1431 struct driver_data
*driver_data
= packet
->driver_data
;
1432 int retval
= -ENOENT
;
1434 tasklet_disable(&ctx
->tasklet
);
1436 if (packet
->ack
!= 0)
1439 driver_data
->packet
= NULL
;
1440 packet
->ack
= RCODE_CANCELLED
;
1441 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1445 tasklet_enable(&ctx
->tasklet
);
1451 ohci_enable_phys_dma(struct fw_card
*card
, int node_id
, int generation
)
1453 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1456 struct fw_ohci
*ohci
= fw_ohci(card
);
1457 unsigned long flags
;
1461 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1462 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1465 spin_lock_irqsave(&ohci
->lock
, flags
);
1467 if (ohci
->generation
!= generation
) {
1473 * Note, if the node ID contains a non-local bus ID, physical DMA is
1474 * enabled for _all_ nodes on remote buses.
1477 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1479 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1481 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1485 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1487 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1491 ohci_get_bus_time(struct fw_card
*card
)
1493 struct fw_ohci
*ohci
= fw_ohci(card
);
1497 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1498 bus_time
= ((u64
) ohci
->bus_seconds
<< 32) | cycle_time
;
1503 static int handle_ir_dualbuffer_packet(struct context
*context
,
1504 struct descriptor
*d
,
1505 struct descriptor
*last
)
1507 struct iso_context
*ctx
=
1508 container_of(context
, struct iso_context
, context
);
1509 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1511 size_t header_length
;
1515 if (db
->first_res_count
!= 0 && db
->second_res_count
!= 0) {
1516 if (ctx
->excess_bytes
<= le16_to_cpu(db
->second_req_count
)) {
1517 /* This descriptor isn't done yet, stop iteration. */
1520 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
);
1523 header_length
= le16_to_cpu(db
->first_req_count
) -
1524 le16_to_cpu(db
->first_res_count
);
1526 i
= ctx
->header_length
;
1528 end
= p
+ header_length
;
1529 while (p
< end
&& i
+ ctx
->base
.header_size
<= PAGE_SIZE
) {
1531 * The iso header is byteswapped to little endian by
1532 * the controller, but the remaining header quadlets
1533 * are big endian. We want to present all the headers
1534 * as big endian, so we have to swap the first
1537 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1538 memcpy(ctx
->header
+ i
+ 4, p
+ 8, ctx
->base
.header_size
- 4);
1539 i
+= ctx
->base
.header_size
;
1540 ctx
->excess_bytes
+=
1541 (le32_to_cpu(*(__le32
*)(p
+ 4)) >> 16) & 0xffff;
1542 p
+= ctx
->base
.header_size
+ 4;
1544 ctx
->header_length
= i
;
1546 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
) -
1547 le16_to_cpu(db
->second_res_count
);
1549 if (le16_to_cpu(db
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1550 ir_header
= (__le32
*) (db
+ 1);
1551 ctx
->base
.callback(&ctx
->base
,
1552 le32_to_cpu(ir_header
[0]) & 0xffff,
1553 ctx
->header_length
, ctx
->header
,
1554 ctx
->base
.callback_data
);
1555 ctx
->header_length
= 0;
1561 static int handle_ir_packet_per_buffer(struct context
*context
,
1562 struct descriptor
*d
,
1563 struct descriptor
*last
)
1565 struct iso_context
*ctx
=
1566 container_of(context
, struct iso_context
, context
);
1567 struct descriptor
*pd
;
1572 for (pd
= d
; pd
<= last
; pd
++) {
1573 if (pd
->transfer_status
)
1577 /* Descriptor(s) not done yet, stop iteration */
1580 i
= ctx
->header_length
;
1583 if (ctx
->base
.header_size
> 0 &&
1584 i
+ ctx
->base
.header_size
<= PAGE_SIZE
) {
1586 * The iso header is byteswapped to little endian by
1587 * the controller, but the remaining header quadlets
1588 * are big endian. We want to present all the headers
1589 * as big endian, so we have to swap the first quadlet.
1591 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1592 memcpy(ctx
->header
+ i
+ 4, p
+ 8, ctx
->base
.header_size
- 4);
1593 ctx
->header_length
+= ctx
->base
.header_size
;
1596 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1597 ir_header
= (__le32
*) p
;
1598 ctx
->base
.callback(&ctx
->base
,
1599 le32_to_cpu(ir_header
[0]) & 0xffff,
1600 ctx
->header_length
, ctx
->header
,
1601 ctx
->base
.callback_data
);
1602 ctx
->header_length
= 0;
1608 static int handle_it_packet(struct context
*context
,
1609 struct descriptor
*d
,
1610 struct descriptor
*last
)
1612 struct iso_context
*ctx
=
1613 container_of(context
, struct iso_context
, context
);
1615 if (last
->transfer_status
== 0)
1616 /* This descriptor isn't done yet, stop iteration. */
1619 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
)
1620 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1621 0, NULL
, ctx
->base
.callback_data
);
1626 static struct fw_iso_context
*
1627 ohci_allocate_iso_context(struct fw_card
*card
, int type
, size_t header_size
)
1629 struct fw_ohci
*ohci
= fw_ohci(card
);
1630 struct iso_context
*ctx
, *list
;
1631 descriptor_callback_t callback
;
1633 unsigned long flags
;
1634 int index
, retval
= -ENOMEM
;
1636 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1637 mask
= &ohci
->it_context_mask
;
1638 list
= ohci
->it_context_list
;
1639 callback
= handle_it_packet
;
1641 mask
= &ohci
->ir_context_mask
;
1642 list
= ohci
->ir_context_list
;
1643 if (ohci
->version
>= OHCI_VERSION_1_1
)
1644 callback
= handle_ir_dualbuffer_packet
;
1646 callback
= handle_ir_packet_per_buffer
;
1649 spin_lock_irqsave(&ohci
->lock
, flags
);
1650 index
= ffs(*mask
) - 1;
1652 *mask
&= ~(1 << index
);
1653 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1656 return ERR_PTR(-EBUSY
);
1658 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
1659 regs
= OHCI1394_IsoXmitContextBase(index
);
1661 regs
= OHCI1394_IsoRcvContextBase(index
);
1664 memset(ctx
, 0, sizeof(*ctx
));
1665 ctx
->header_length
= 0;
1666 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
1667 if (ctx
->header
== NULL
)
1670 retval
= context_init(&ctx
->context
, ohci
, regs
, callback
);
1672 goto out_with_header
;
1677 free_page((unsigned long)ctx
->header
);
1679 spin_lock_irqsave(&ohci
->lock
, flags
);
1680 *mask
|= 1 << index
;
1681 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1683 return ERR_PTR(retval
);
1686 static int ohci_start_iso(struct fw_iso_context
*base
,
1687 s32 cycle
, u32 sync
, u32 tags
)
1689 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1690 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
1694 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1695 index
= ctx
- ohci
->it_context_list
;
1698 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
1699 (cycle
& 0x7fff) << 16;
1701 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
1702 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
1703 context_run(&ctx
->context
, match
);
1705 index
= ctx
- ohci
->ir_context_list
;
1706 control
= IR_CONTEXT_ISOCH_HEADER
;
1707 if (ohci
->version
>= OHCI_VERSION_1_1
)
1708 control
|= IR_CONTEXT_DUAL_BUFFER_MODE
;
1709 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
1711 match
|= (cycle
& 0x07fff) << 12;
1712 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
1715 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
1716 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
1717 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
1718 context_run(&ctx
->context
, control
);
1724 static int ohci_stop_iso(struct fw_iso_context
*base
)
1726 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1727 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1730 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1731 index
= ctx
- ohci
->it_context_list
;
1732 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
1734 index
= ctx
- ohci
->ir_context_list
;
1735 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
1738 context_stop(&ctx
->context
);
1743 static void ohci_free_iso_context(struct fw_iso_context
*base
)
1745 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1746 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1747 unsigned long flags
;
1750 ohci_stop_iso(base
);
1751 context_release(&ctx
->context
);
1752 free_page((unsigned long)ctx
->header
);
1754 spin_lock_irqsave(&ohci
->lock
, flags
);
1756 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1757 index
= ctx
- ohci
->it_context_list
;
1758 ohci
->it_context_mask
|= 1 << index
;
1760 index
= ctx
- ohci
->ir_context_list
;
1761 ohci
->ir_context_mask
|= 1 << index
;
1764 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1768 ohci_queue_iso_transmit(struct fw_iso_context
*base
,
1769 struct fw_iso_packet
*packet
,
1770 struct fw_iso_buffer
*buffer
,
1771 unsigned long payload
)
1773 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1774 struct descriptor
*d
, *last
, *pd
;
1775 struct fw_iso_packet
*p
;
1777 dma_addr_t d_bus
, page_bus
;
1778 u32 z
, header_z
, payload_z
, irq
;
1779 u32 payload_index
, payload_end_index
, next_page_index
;
1780 int page
, end_page
, i
, length
, offset
;
1783 * FIXME: Cycle lost behavior should be configurable: lose
1784 * packet, retransmit or terminate..
1788 payload_index
= payload
;
1794 if (p
->header_length
> 0)
1797 /* Determine the first page the payload isn't contained in. */
1798 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
1799 if (p
->payload_length
> 0)
1800 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
1806 /* Get header size in number of descriptors. */
1807 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof(*d
));
1809 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
1814 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
1815 d
[0].req_count
= cpu_to_le16(8);
1817 header
= (__le32
*) &d
[1];
1818 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
1819 IT_HEADER_TAG(p
->tag
) |
1820 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
1821 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
1822 IT_HEADER_SPEED(ctx
->base
.speed
));
1824 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
1825 p
->payload_length
));
1828 if (p
->header_length
> 0) {
1829 d
[2].req_count
= cpu_to_le16(p
->header_length
);
1830 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof(*d
));
1831 memcpy(&d
[z
], p
->header
, p
->header_length
);
1834 pd
= d
+ z
- payload_z
;
1835 payload_end_index
= payload_index
+ p
->payload_length
;
1836 for (i
= 0; i
< payload_z
; i
++) {
1837 page
= payload_index
>> PAGE_SHIFT
;
1838 offset
= payload_index
& ~PAGE_MASK
;
1839 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
1841 min(next_page_index
, payload_end_index
) - payload_index
;
1842 pd
[i
].req_count
= cpu_to_le16(length
);
1844 page_bus
= page_private(buffer
->pages
[page
]);
1845 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
1847 payload_index
+= length
;
1851 irq
= DESCRIPTOR_IRQ_ALWAYS
;
1853 irq
= DESCRIPTOR_NO_IRQ
;
1855 last
= z
== 2 ? d
: d
+ z
- 1;
1856 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
1858 DESCRIPTOR_BRANCH_ALWAYS
|
1861 context_append(&ctx
->context
, d
, z
, header_z
);
1867 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
1868 struct fw_iso_packet
*packet
,
1869 struct fw_iso_buffer
*buffer
,
1870 unsigned long payload
)
1872 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1873 struct db_descriptor
*db
= NULL
;
1874 struct descriptor
*d
;
1875 struct fw_iso_packet
*p
;
1876 dma_addr_t d_bus
, page_bus
;
1877 u32 z
, header_z
, length
, rest
;
1878 int page
, offset
, packet_count
, header_size
;
1881 * FIXME: Cycle lost behavior should be configurable: lose
1882 * packet, retransmit or terminate..
1889 * The OHCI controller puts the status word in the header
1890 * buffer too, so we need 4 extra bytes per packet.
1892 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
1893 header_size
= packet_count
* (ctx
->base
.header_size
+ 4);
1895 /* Get header size in number of descriptors. */
1896 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
1897 page
= payload
>> PAGE_SHIFT
;
1898 offset
= payload
& ~PAGE_MASK
;
1899 rest
= p
->payload_length
;
1901 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1903 d
= context_get_descriptors(&ctx
->context
,
1904 z
+ header_z
, &d_bus
);
1908 db
= (struct db_descriptor
*) d
;
1909 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1910 DESCRIPTOR_BRANCH_ALWAYS
);
1911 db
->first_size
= cpu_to_le16(ctx
->base
.header_size
+ 4);
1912 if (p
->skip
&& rest
== p
->payload_length
) {
1913 db
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
1914 db
->first_req_count
= db
->first_size
;
1916 db
->first_req_count
= cpu_to_le16(header_size
);
1918 db
->first_res_count
= db
->first_req_count
;
1919 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof(*db
));
1921 if (p
->skip
&& rest
== p
->payload_length
)
1923 else if (offset
+ rest
< PAGE_SIZE
)
1926 length
= PAGE_SIZE
- offset
;
1928 db
->second_req_count
= cpu_to_le16(length
);
1929 db
->second_res_count
= db
->second_req_count
;
1930 page_bus
= page_private(buffer
->pages
[page
]);
1931 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
1933 if (p
->interrupt
&& length
== rest
)
1934 db
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
1936 context_append(&ctx
->context
, d
, z
, header_z
);
1937 offset
= (offset
+ length
) & ~PAGE_MASK
;
1947 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context
*base
,
1948 struct fw_iso_packet
*packet
,
1949 struct fw_iso_buffer
*buffer
,
1950 unsigned long payload
)
1952 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1953 struct descriptor
*d
= NULL
, *pd
= NULL
;
1954 struct fw_iso_packet
*p
= packet
;
1955 dma_addr_t d_bus
, page_bus
;
1956 u32 z
, header_z
, rest
;
1958 int page
, offset
, packet_count
, header_size
, payload_per_buffer
;
1961 * The OHCI controller puts the status word in the
1962 * buffer too, so we need 4 extra bytes per packet.
1964 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
1965 header_size
= ctx
->base
.header_size
+ 4;
1967 /* Get header size in number of descriptors. */
1968 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
1969 page
= payload
>> PAGE_SHIFT
;
1970 offset
= payload
& ~PAGE_MASK
;
1971 payload_per_buffer
= p
->payload_length
/ packet_count
;
1973 for (i
= 0; i
< packet_count
; i
++) {
1974 /* d points to the header descriptor */
1975 z
= DIV_ROUND_UP(payload_per_buffer
+ offset
, PAGE_SIZE
) + 1;
1976 d
= context_get_descriptors(&ctx
->context
,
1977 z
+ header_z
, &d_bus
);
1981 d
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1982 DESCRIPTOR_INPUT_MORE
);
1983 if (p
->skip
&& i
== 0)
1984 d
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
1985 d
->req_count
= cpu_to_le16(header_size
);
1986 d
->res_count
= d
->req_count
;
1987 d
->transfer_status
= 0;
1988 d
->data_address
= cpu_to_le32(d_bus
+ (z
* sizeof(*d
)));
1990 rest
= payload_per_buffer
;
1991 for (j
= 1; j
< z
; j
++) {
1993 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1994 DESCRIPTOR_INPUT_MORE
);
1996 if (offset
+ rest
< PAGE_SIZE
)
1999 length
= PAGE_SIZE
- offset
;
2000 pd
->req_count
= cpu_to_le16(length
);
2001 pd
->res_count
= pd
->req_count
;
2002 pd
->transfer_status
= 0;
2004 page_bus
= page_private(buffer
->pages
[page
]);
2005 pd
->data_address
= cpu_to_le32(page_bus
+ offset
);
2007 offset
= (offset
+ length
) & ~PAGE_MASK
;
2012 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2013 DESCRIPTOR_INPUT_LAST
|
2014 DESCRIPTOR_BRANCH_ALWAYS
);
2015 if (p
->interrupt
&& i
== packet_count
- 1)
2016 pd
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2018 context_append(&ctx
->context
, d
, z
, header_z
);
2025 ohci_queue_iso(struct fw_iso_context
*base
,
2026 struct fw_iso_packet
*packet
,
2027 struct fw_iso_buffer
*buffer
,
2028 unsigned long payload
)
2030 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2031 unsigned long flags
;
2034 spin_lock_irqsave(&ctx
->context
.ohci
->lock
, flags
);
2035 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
2036 retval
= ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
2037 else if (ctx
->context
.ohci
->version
>= OHCI_VERSION_1_1
)
2038 retval
= ohci_queue_iso_receive_dualbuffer(base
, packet
,
2041 retval
= ohci_queue_iso_receive_packet_per_buffer(base
, packet
,
2044 spin_unlock_irqrestore(&ctx
->context
.ohci
->lock
, flags
);
2049 static const struct fw_card_driver ohci_driver
= {
2050 .name
= ohci_driver_name
,
2051 .enable
= ohci_enable
,
2052 .update_phy_reg
= ohci_update_phy_reg
,
2053 .set_config_rom
= ohci_set_config_rom
,
2054 .send_request
= ohci_send_request
,
2055 .send_response
= ohci_send_response
,
2056 .cancel_packet
= ohci_cancel_packet
,
2057 .enable_phys_dma
= ohci_enable_phys_dma
,
2058 .get_bus_time
= ohci_get_bus_time
,
2060 .allocate_iso_context
= ohci_allocate_iso_context
,
2061 .free_iso_context
= ohci_free_iso_context
,
2062 .queue_iso
= ohci_queue_iso
,
2063 .start_iso
= ohci_start_iso
,
2064 .stop_iso
= ohci_stop_iso
,
2067 #ifdef CONFIG_PPC_PMAC
2068 static void ohci_pmac_on(struct pci_dev
*dev
)
2070 if (machine_is(powermac
)) {
2071 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2074 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 1);
2075 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 1);
2080 static void ohci_pmac_off(struct pci_dev
*dev
)
2082 if (machine_is(powermac
)) {
2083 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2086 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 0);
2087 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 0);
2092 #define ohci_pmac_on(dev)
2093 #define ohci_pmac_off(dev)
2094 #endif /* CONFIG_PPC_PMAC */
2096 static int __devinit
2097 pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
2099 struct fw_ohci
*ohci
;
2100 u32 bus_options
, max_receive
, link_speed
;
2107 ohci
= kzalloc(sizeof(*ohci
), GFP_KERNEL
);
2109 fw_error("Could not malloc fw_ohci data.\n");
2113 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
2115 err
= pci_enable_device(dev
);
2117 fw_error("Failed to enable OHCI hardware.\n");
2121 pci_set_master(dev
);
2122 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
2123 pci_set_drvdata(dev
, ohci
);
2125 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2126 ohci
->old_uninorth
= dev
->vendor
== PCI_VENDOR_ID_APPLE
&&
2127 dev
->device
== PCI_DEVICE_ID_APPLE_UNI_N_FW
;
2129 spin_lock_init(&ohci
->lock
);
2131 tasklet_init(&ohci
->bus_reset_tasklet
,
2132 bus_reset_tasklet
, (unsigned long)ohci
);
2134 err
= pci_request_region(dev
, 0, ohci_driver_name
);
2136 fw_error("MMIO resource unavailable\n");
2140 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
2141 if (ohci
->registers
== NULL
) {
2142 fw_error("Failed to remap registers\n");
2147 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
2148 OHCI1394_AsReqRcvContextControlSet
);
2150 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
2151 OHCI1394_AsRspRcvContextControlSet
);
2153 context_init(&ohci
->at_request_ctx
, ohci
,
2154 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
2156 context_init(&ohci
->at_response_ctx
, ohci
,
2157 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
2159 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
2160 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
2161 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
2162 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
2163 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
2165 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
2166 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
2167 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
2168 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
2169 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
2171 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
2172 fw_error("Out of memory for it/ir contexts.\n");
2174 goto fail_registers
;
2177 /* self-id dma buffer allocation */
2178 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
2182 if (ohci
->self_id_cpu
== NULL
) {
2183 fw_error("Out of memory for self ID buffer.\n");
2185 goto fail_registers
;
2188 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
2189 max_receive
= (bus_options
>> 12) & 0xf;
2190 link_speed
= bus_options
& 0x7;
2191 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
2192 reg_read(ohci
, OHCI1394_GUIDLo
);
2194 err
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
2198 ohci
->version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
2199 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2200 dev
->dev
.bus_id
, ohci
->version
>> 16, ohci
->version
& 0xff);
2204 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2205 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2207 kfree(ohci
->it_context_list
);
2208 kfree(ohci
->ir_context_list
);
2209 pci_iounmap(dev
, ohci
->registers
);
2211 pci_release_region(dev
, 0);
2213 pci_disable_device(dev
);
2220 static void pci_remove(struct pci_dev
*dev
)
2222 struct fw_ohci
*ohci
;
2224 ohci
= pci_get_drvdata(dev
);
2225 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
2227 fw_core_remove_card(&ohci
->card
);
2230 * FIXME: Fail all pending packets here, now that the upper
2231 * layers can't queue any more.
2234 software_reset(ohci
);
2235 free_irq(dev
->irq
, ohci
);
2236 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2237 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2238 kfree(ohci
->it_context_list
);
2239 kfree(ohci
->ir_context_list
);
2240 pci_iounmap(dev
, ohci
->registers
);
2241 pci_release_region(dev
, 0);
2242 pci_disable_device(dev
);
2246 fw_notify("Removed fw-ohci device.\n");
2250 static int pci_suspend(struct pci_dev
*dev
, pm_message_t state
)
2252 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2255 software_reset(ohci
);
2256 free_irq(dev
->irq
, ohci
);
2257 err
= pci_save_state(dev
);
2259 fw_error("pci_save_state failed\n");
2262 err
= pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2264 fw_error("pci_set_power_state failed with %d\n", err
);
2270 static int pci_resume(struct pci_dev
*dev
)
2272 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2276 pci_set_power_state(dev
, PCI_D0
);
2277 pci_restore_state(dev
);
2278 err
= pci_enable_device(dev
);
2280 fw_error("pci_enable_device failed\n");
2284 return ohci_enable(&ohci
->card
, NULL
, 0);
2288 static struct pci_device_id pci_table
[] = {
2289 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
2293 MODULE_DEVICE_TABLE(pci
, pci_table
);
2295 static struct pci_driver fw_ohci_pci_driver
= {
2296 .name
= ohci_driver_name
,
2297 .id_table
= pci_table
,
2299 .remove
= pci_remove
,
2301 .resume
= pci_resume
,
2302 .suspend
= pci_suspend
,
2306 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2307 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2308 MODULE_LICENSE("GPL");
2310 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2311 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2312 MODULE_ALIAS("ohci1394");
2315 static int __init
fw_ohci_init(void)
2317 return pci_register_driver(&fw_ohci_pci_driver
);
2320 static void __exit
fw_ohci_cleanup(void)
2322 pci_unregister_driver(&fw_ohci_pci_driver
);
2325 module_init(fw_ohci_init
);
2326 module_exit(fw_ohci_cleanup
);