1 /* -*- c-basic-offset: 8 -*-
3 * fw-ohci.c - Driver for OHCI 1394 boards
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/poll.h>
28 #include <linux/dma-mapping.h>
30 #include <asm/uaccess.h>
31 #include <asm/semaphore.h>
33 #include "fw-transaction.h"
36 #define descriptor_output_more 0
37 #define descriptor_output_last (1 << 12)
38 #define descriptor_input_more (2 << 12)
39 #define descriptor_input_last (3 << 12)
40 #define descriptor_status (1 << 11)
41 #define descriptor_key_immediate (2 << 8)
42 #define descriptor_ping (1 << 7)
43 #define descriptor_yy (1 << 6)
44 #define descriptor_no_irq (0 << 4)
45 #define descriptor_irq_error (1 << 4)
46 #define descriptor_irq_always (3 << 4)
47 #define descriptor_branch_always (3 << 2)
53 __le32 branch_address
;
55 __le16 transfer_status
;
56 } __attribute__((aligned(16)));
60 struct descriptor descriptor
;
62 dma_addr_t descriptor_bus
;
63 dma_addr_t buffer_bus
;
69 struct tasklet_struct tasklet
;
74 dma_addr_t descriptor_bus
;
75 dma_addr_t buffer_bus
;
77 struct list_head list
;
80 struct descriptor more
;
82 struct descriptor last
;
89 struct tasklet_struct tasklet
;
92 #define it_header_sy(v) ((v) << 0)
93 #define it_header_tcode(v) ((v) << 4)
94 #define it_header_channel(v) ((v) << 8)
95 #define it_header_tag(v) ((v) << 14)
96 #define it_header_speed(v) ((v) << 16)
97 #define it_header_data_length(v) ((v) << 16)
100 struct fw_iso_context base
;
101 struct tasklet_struct tasklet
;
107 struct descriptor
*buffer
;
108 dma_addr_t buffer_bus
;
109 struct descriptor
*head_descriptor
;
110 struct descriptor
*tail_descriptor
;
111 struct descriptor
*tail_descriptor_last
;
112 struct descriptor
*prev_descriptor
;
115 #define CONFIG_ROM_SIZE 1024
120 __iomem
char *registers
;
121 dma_addr_t self_id_bus
;
123 struct tasklet_struct bus_reset_tasklet
;
125 int request_generation
;
127 /* Spinlock for accessing fw_ohci data. Never call out of
128 * this driver with this lock held. */
130 u32 self_id_buffer
[512];
132 /* Config rom buffers */
134 dma_addr_t config_rom_bus
;
135 __be32
*next_config_rom
;
136 dma_addr_t next_config_rom_bus
;
139 struct ar_context ar_request_ctx
;
140 struct ar_context ar_response_ctx
;
141 struct at_context at_request_ctx
;
142 struct at_context at_response_ctx
;
145 struct iso_context
*it_context_list
;
147 struct iso_context
*ir_context_list
;
150 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
152 return container_of(card
, struct fw_ohci
, card
);
155 #define CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
157 #define CONTEXT_RUN 0x8000
158 #define CONTEXT_WAKE 0x1000
159 #define CONTEXT_DEAD 0x0800
160 #define CONTEXT_ACTIVE 0x0400
162 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
163 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
164 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
166 #define FW_OHCI_MAJOR 240
167 #define OHCI1394_REGISTER_SIZE 0x800
168 #define OHCI_LOOP_COUNT 500
169 #define OHCI1394_PCI_HCI_Control 0x40
170 #define SELF_ID_BUF_SIZE 0x800
172 /* FIXME: Move this to linux/pci_ids.h */
173 #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
175 static char ohci_driver_name
[] = KBUILD_MODNAME
;
177 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
179 writel(data
, ohci
->registers
+ offset
);
182 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
184 return readl(ohci
->registers
+ offset
);
187 static inline void flush_writes(const struct fw_ohci
*ohci
)
189 /* Do a dummy read to flush writes. */
190 reg_read(ohci
, OHCI1394_Version
);
194 ohci_update_phy_reg(struct fw_card
*card
, int addr
,
195 int clear_bits
, int set_bits
)
197 struct fw_ohci
*ohci
= fw_ohci(card
);
200 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
202 val
= reg_read(ohci
, OHCI1394_PhyControl
);
203 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
204 fw_error("failed to set phy reg bits.\n");
208 old
= OHCI1394_PhyControl_ReadData(val
);
209 old
= (old
& ~clear_bits
) | set_bits
;
210 reg_write(ohci
, OHCI1394_PhyControl
,
211 OHCI1394_PhyControl_Write(addr
, old
));
216 static void ar_context_run(struct ar_context
*ctx
)
218 reg_write(ctx
->ohci
, ctx
->command_ptr
, ctx
->descriptor_bus
| 1);
219 reg_write(ctx
->ohci
, ctx
->control_set
, CONTEXT_RUN
);
220 flush_writes(ctx
->ohci
);
223 static void ar_context_tasklet(unsigned long data
)
225 struct ar_context
*ctx
= (struct ar_context
*)data
;
226 struct fw_ohci
*ohci
= ctx
->ohci
;
228 int length
, speed
, ack
, timestamp
, tcode
;
230 /* FIXME: What to do about evt_* errors? */
231 length
= le16_to_cpu(ctx
->descriptor
.req_count
) -
232 le16_to_cpu(ctx
->descriptor
.res_count
) - 4;
233 status
= le32_to_cpu(ctx
->buffer
[length
/ 4]);
234 ack
= ((status
>> 16) & 0x1f) - 16;
235 speed
= (status
>> 21) & 0x7;
236 timestamp
= status
& 0xffff;
238 ctx
->buffer
[0] = le32_to_cpu(ctx
->buffer
[0]);
239 ctx
->buffer
[1] = le32_to_cpu(ctx
->buffer
[1]);
240 ctx
->buffer
[2] = le32_to_cpu(ctx
->buffer
[2]);
242 tcode
= (ctx
->buffer
[0] >> 4) & 0x0f;
243 if (TCODE_IS_BLOCK_PACKET(tcode
))
244 ctx
->buffer
[3] = le32_to_cpu(ctx
->buffer
[3]);
246 /* The OHCI bus reset handler synthesizes a phy packet with
247 * the new generation number when a bus reset happens (see
248 * section 8.4.2.3). This helps us determine when a request
249 * was received and make sure we send the response in the same
250 * generation. We only need this for requests; for responses
251 * we use the unique tlabel for finding the matching
254 if (ack
+ 16 == 0x09)
255 ohci
->request_generation
= (ctx
->buffer
[2] >> 16) & 0xff;
256 else if (ctx
== &ohci
->ar_request_ctx
)
257 fw_core_handle_request(&ohci
->card
, speed
, ack
, timestamp
,
258 ohci
->request_generation
,
259 length
, ctx
->buffer
);
261 fw_core_handle_response(&ohci
->card
, speed
, ack
, timestamp
,
262 length
, ctx
->buffer
);
264 ctx
->descriptor
.data_address
= cpu_to_le32(ctx
->buffer_bus
);
265 ctx
->descriptor
.req_count
= cpu_to_le16(sizeof ctx
->buffer
);
266 ctx
->descriptor
.res_count
= cpu_to_le16(sizeof ctx
->buffer
);
268 dma_sync_single_for_device(ohci
->card
.device
, ctx
->descriptor_bus
,
269 sizeof ctx
->descriptor_bus
, DMA_TO_DEVICE
);
271 /* FIXME: We stop and restart the ar context here, what if we
272 * stop while a receive is in progress? Maybe we could just
273 * loop the context back to itself and use it in buffer fill
274 * mode as intended... */
276 reg_write(ctx
->ohci
, ctx
->control_clear
, CONTEXT_RUN
);
281 ar_context_init(struct ar_context
*ctx
, struct fw_ohci
*ohci
, u32 control_set
)
283 ctx
->descriptor_bus
=
284 dma_map_single(ohci
->card
.device
, &ctx
->descriptor
,
285 sizeof ctx
->descriptor
, DMA_TO_DEVICE
);
286 if (ctx
->descriptor_bus
== 0)
289 if (ctx
->descriptor_bus
& 0xf)
290 fw_notify("descriptor not 16-byte aligned: 0x%08lx\n",
291 (unsigned long)ctx
->descriptor_bus
);
294 dma_map_single(ohci
->card
.device
, ctx
->buffer
,
295 sizeof ctx
->buffer
, DMA_FROM_DEVICE
);
297 if (ctx
->buffer_bus
== 0) {
298 dma_unmap_single(ohci
->card
.device
, ctx
->descriptor_bus
,
299 sizeof ctx
->descriptor
, DMA_TO_DEVICE
);
303 memset(&ctx
->descriptor
, 0, sizeof ctx
->descriptor
);
304 ctx
->descriptor
.control
= cpu_to_le16(descriptor_input_more
|
306 descriptor_branch_always
);
307 ctx
->descriptor
.req_count
= cpu_to_le16(sizeof ctx
->buffer
);
308 ctx
->descriptor
.data_address
= cpu_to_le32(ctx
->buffer_bus
);
309 ctx
->descriptor
.res_count
= cpu_to_le16(sizeof ctx
->buffer
);
311 ctx
->control_set
= control_set
;
312 ctx
->control_clear
= control_set
+ 4;
313 ctx
->command_ptr
= control_set
+ 12;
316 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
324 do_packet_callbacks(struct fw_ohci
*ohci
, struct list_head
*list
)
326 struct fw_packet
*p
, *next
;
328 list_for_each_entry_safe(p
, next
, list
, link
)
329 p
->callback(p
, &ohci
->card
, p
->status
);
333 complete_transmission(struct fw_packet
*packet
,
334 int status
, struct list_head
*list
)
336 list_move_tail(&packet
->link
, list
);
337 packet
->status
= status
;
340 /* This function prepares the first packet in the context queue for
341 * transmission. Must always be called with the ochi->lock held to
342 * ensure proper generation handling and locking around packet queue
345 at_context_setup_packet(struct at_context
*ctx
, struct list_head
*list
)
347 struct fw_packet
*packet
;
348 struct fw_ohci
*ohci
= ctx
->ohci
;
351 packet
= fw_packet(ctx
->list
.next
);
353 memset(&ctx
->d
, 0, sizeof ctx
->d
);
354 if (packet
->payload_length
> 0) {
355 packet
->payload_bus
= dma_map_single(ohci
->card
.device
,
357 packet
->payload_length
,
359 if (packet
->payload_bus
== 0) {
360 complete_transmission(packet
, -ENOMEM
, list
);
364 ctx
->d
.more
.control
=
365 cpu_to_le16(descriptor_output_more
|
366 descriptor_key_immediate
);
367 ctx
->d
.more
.req_count
= cpu_to_le16(packet
->header_length
);
368 ctx
->d
.more
.res_count
= cpu_to_le16(packet
->timestamp
);
369 ctx
->d
.last
.control
=
370 cpu_to_le16(descriptor_output_last
|
371 descriptor_irq_always
|
372 descriptor_branch_always
);
373 ctx
->d
.last
.req_count
= cpu_to_le16(packet
->payload_length
);
374 ctx
->d
.last
.data_address
= cpu_to_le32(packet
->payload_bus
);
377 ctx
->d
.more
.control
=
378 cpu_to_le16(descriptor_output_last
|
379 descriptor_key_immediate
|
380 descriptor_irq_always
|
381 descriptor_branch_always
);
382 ctx
->d
.more
.req_count
= cpu_to_le16(packet
->header_length
);
383 ctx
->d
.more
.res_count
= cpu_to_le16(packet
->timestamp
);
387 /* The DMA format for asyncronous link packets is different
388 * from the IEEE1394 layout, so shift the fields around
389 * accordingly. If header_length is 8, it's a PHY packet, to
390 * which we need to prepend an extra quadlet. */
391 if (packet
->header_length
> 8) {
392 ctx
->d
.header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
393 (packet
->speed
<< 16));
394 ctx
->d
.header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
395 (packet
->header
[0] & 0xffff0000));
396 ctx
->d
.header
[2] = cpu_to_le32(packet
->header
[2]);
398 tcode
= (packet
->header
[0] >> 4) & 0x0f;
399 if (TCODE_IS_BLOCK_PACKET(tcode
))
400 ctx
->d
.header
[3] = cpu_to_le32(packet
->header
[3]);
402 ctx
->d
.header
[3] = packet
->header
[3];
405 cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
406 (packet
->speed
<< 16));
407 ctx
->d
.header
[1] = cpu_to_le32(packet
->header
[0]);
408 ctx
->d
.header
[2] = cpu_to_le32(packet
->header
[1]);
409 ctx
->d
.more
.req_count
= cpu_to_le16(12);
412 /* FIXME: Document how the locking works. */
413 if (ohci
->generation
== packet
->generation
) {
414 reg_write(ctx
->ohci
, ctx
->command_ptr
,
415 ctx
->descriptor_bus
| z
);
416 reg_write(ctx
->ohci
, ctx
->control_set
,
417 CONTEXT_RUN
| CONTEXT_WAKE
);
419 /* We dont return error codes from this function; all
420 * transmission errors are reported through the
422 complete_transmission(packet
, -ESTALE
, list
);
426 static void at_context_stop(struct at_context
*ctx
)
430 reg_write(ctx
->ohci
, ctx
->control_clear
, CONTEXT_RUN
);
432 reg
= reg_read(ctx
->ohci
, ctx
->control_set
);
433 if (reg
& CONTEXT_ACTIVE
)
434 fw_notify("Tried to stop context, but it is still active "
438 static void at_context_tasklet(unsigned long data
)
440 struct at_context
*ctx
= (struct at_context
*)data
;
441 struct fw_ohci
*ohci
= ctx
->ohci
;
442 struct fw_packet
*packet
;
447 spin_lock_irqsave(&ohci
->lock
, flags
);
449 packet
= fw_packet(ctx
->list
.next
);
451 at_context_stop(ctx
);
453 if (packet
->payload_length
> 0) {
454 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
455 packet
->payload_length
, DMA_TO_DEVICE
);
456 evt
= le16_to_cpu(ctx
->d
.last
.transfer_status
) & 0x1f;
457 packet
->timestamp
= le16_to_cpu(ctx
->d
.last
.res_count
);
460 evt
= le16_to_cpu(ctx
->d
.more
.transfer_status
) & 0x1f;
461 packet
->timestamp
= le16_to_cpu(ctx
->d
.more
.res_count
);
466 case OHCI1394_evt_timeout
:
467 /* Async response transmit timed out. */
468 complete_transmission(packet
, -ETIMEDOUT
, &list
);
471 case OHCI1394_evt_flushed
:
472 /* The packet was flushed should give same
473 * error as when we try to use a stale
474 * generation count. */
475 complete_transmission(packet
, -ESTALE
, &list
);
478 case OHCI1394_evt_missing_ack
:
479 /* This would be a higher level software
480 * error, it is using a valid (current)
481 * generation count, but the node is not on
483 complete_transmission(packet
, -ENODEV
, &list
);
487 complete_transmission(packet
, -EIO
, &list
);
491 complete_transmission(packet
, evt
- 16, &list
);
493 /* If more packets are queued, set up the next one. */
494 if (!list_empty(&ctx
->list
))
495 at_context_setup_packet(ctx
, &list
);
497 spin_unlock_irqrestore(&ohci
->lock
, flags
);
499 do_packet_callbacks(ohci
, &list
);
503 at_context_init(struct at_context
*ctx
, struct fw_ohci
*ohci
, u32 control_set
)
505 INIT_LIST_HEAD(&ctx
->list
);
507 ctx
->descriptor_bus
=
508 dma_map_single(ohci
->card
.device
, &ctx
->d
,
509 sizeof ctx
->d
, DMA_TO_DEVICE
);
510 if (ctx
->descriptor_bus
== 0)
513 ctx
->control_set
= control_set
;
514 ctx
->control_clear
= control_set
+ 4;
515 ctx
->command_ptr
= control_set
+ 12;
518 tasklet_init(&ctx
->tasklet
, at_context_tasklet
, (unsigned long)ctx
);
524 at_context_transmit(struct at_context
*ctx
, struct fw_packet
*packet
)
530 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
532 was_empty
= list_empty(&ctx
->list
);
533 list_add_tail(&packet
->link
, &ctx
->list
);
535 at_context_setup_packet(ctx
, &list
);
537 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
539 do_packet_callbacks(ctx
->ohci
, &list
);
542 static void bus_reset_tasklet(unsigned long data
)
544 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
545 int self_id_count
, i
, j
, reg
, node_id
;
546 int generation
, new_generation
;
549 reg
= reg_read(ohci
, OHCI1394_NodeID
);
550 if (!(reg
& OHCI1394_NodeID_idValid
)) {
551 fw_error("node ID not valid, new bus reset in progress\n");
554 node_id
= reg
& 0xffff;
556 /* The count in the SelfIDCount register is the number of
557 * bytes in the self ID receive buffer. Since we also receive
558 * the inverted quadlets and a header quadlet, we shift one
559 * bit extra to get the actual number of self IDs. */
561 self_id_count
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 3) & 0x3ff;
562 generation
= (le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
564 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
565 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1])
566 fw_error("inconsistent self IDs\n");
567 ohci
->self_id_buffer
[j
] = le32_to_cpu(ohci
->self_id_cpu
[i
]);
570 /* Check the consistency of the self IDs we just read. The
571 * problem we face is that a new bus reset can start while we
572 * read out the self IDs from the DMA buffer. If this happens,
573 * the DMA buffer will be overwritten with new self IDs and we
574 * will read out inconsistent data. The OHCI specification
575 * (section 11.2) recommends a technique similar to
576 * linux/seqlock.h, where we remember the generation of the
577 * self IDs in the buffer before reading them out and compare
578 * it to the current generation after reading them out. If
579 * the two generations match we know we have a consistent set
582 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
583 if (new_generation
!= generation
) {
584 fw_notify("recursive bus reset detected, "
585 "discarding self ids\n");
589 /* FIXME: Document how the locking works. */
590 spin_lock_irqsave(&ohci
->lock
, flags
);
592 ohci
->generation
= generation
;
593 at_context_stop(&ohci
->at_request_ctx
);
594 at_context_stop(&ohci
->at_response_ctx
);
595 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
597 /* This next bit is unrelated to the AT context stuff but we
598 * have to do it under the spinlock also. If a new config rom
599 * was set up before this reset, the old one is now no longer
600 * in use and we can free it. Update the config rom pointers
601 * to point to the current config rom and clear the
602 * next_config_rom pointer so a new udpate can take place. */
604 if (ohci
->next_config_rom
!= NULL
) {
605 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
606 ohci
->config_rom
, ohci
->config_rom_bus
);
607 ohci
->config_rom
= ohci
->next_config_rom
;
608 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
609 ohci
->next_config_rom
= NULL
;
611 /* Restore config_rom image and manually update
612 * config_rom registers. Writing the header quadlet
613 * will indicate that the config rom is ready, so we
615 reg_write(ohci
, OHCI1394_BusOptions
,
616 be32_to_cpu(ohci
->config_rom
[2]));
617 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
618 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
621 spin_unlock_irqrestore(&ohci
->lock
, flags
);
623 fw_core_handle_bus_reset(&ohci
->card
, node_id
, generation
,
624 self_id_count
, ohci
->self_id_buffer
);
627 static irqreturn_t
irq_handler(int irq
, void *data
)
629 struct fw_ohci
*ohci
= data
;
630 u32 event
, iso_event
;
633 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
638 reg_write(ohci
, OHCI1394_IntEventClear
, event
);
640 if (event
& OHCI1394_selfIDComplete
)
641 tasklet_schedule(&ohci
->bus_reset_tasklet
);
643 if (event
& OHCI1394_RQPkt
)
644 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
646 if (event
& OHCI1394_RSPkt
)
647 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
649 if (event
& OHCI1394_reqTxComplete
)
650 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
652 if (event
& OHCI1394_respTxComplete
)
653 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
655 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventSet
);
656 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
659 i
= ffs(iso_event
) - 1;
660 tasklet_schedule(&ohci
->ir_context_list
[i
].tasklet
);
661 iso_event
&= ~(1 << i
);
664 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventSet
);
665 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
668 i
= ffs(iso_event
) - 1;
669 tasklet_schedule(&ohci
->it_context_list
[i
].tasklet
);
670 iso_event
&= ~(1 << i
);
676 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
678 struct fw_ohci
*ohci
= fw_ohci(card
);
679 struct pci_dev
*dev
= to_pci_dev(card
->device
);
681 /* When the link is not yet enabled, the atomic config rom
682 * update mechanism described below in ohci_set_config_rom()
683 * is not active. We have to update ConfigRomHeader and
684 * BusOptions manually, and the write to ConfigROMmap takes
685 * effect immediately. We tie this to the enabling of the
686 * link, so we have a valid config rom before enabling - the
687 * OHCI requires that ConfigROMhdr and BusOptions have valid
688 * values before enabling.
690 * However, when the ConfigROMmap is written, some controllers
691 * always read back quadlets 0 and 2 from the config rom to
692 * the ConfigRomHeader and BusOptions registers on bus reset.
693 * They shouldn't do that in this initial case where the link
694 * isn't enabled. This means we have to use the same
695 * workaround here, setting the bus header to 0 and then write
696 * the right values in the bus reset tasklet.
699 ohci
->next_config_rom
=
700 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
701 &ohci
->next_config_rom_bus
, GFP_KERNEL
);
702 if (ohci
->next_config_rom
== NULL
)
705 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
706 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
708 ohci
->next_header
= config_rom
[0];
709 ohci
->next_config_rom
[0] = 0;
710 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
711 reg_write(ohci
, OHCI1394_BusOptions
, config_rom
[2]);
712 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
714 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
716 if (request_irq(dev
->irq
, irq_handler
,
717 SA_SHIRQ
, ohci_driver_name
, ohci
)) {
718 fw_error("Failed to allocate shared interrupt %d.\n",
720 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
721 ohci
->config_rom
, ohci
->config_rom_bus
);
725 reg_write(ohci
, OHCI1394_HCControlSet
,
726 OHCI1394_HCControl_linkEnable
|
727 OHCI1394_HCControl_BIBimageValid
);
730 /* We are ready to go, initiate bus reset to finish the
733 fw_core_initiate_bus_reset(&ohci
->card
, 1);
739 ohci_set_config_rom(struct fw_card
*card
, u32
*config_rom
, size_t length
)
741 struct fw_ohci
*ohci
;
744 __be32
*next_config_rom
;
745 dma_addr_t next_config_rom_bus
;
747 ohci
= fw_ohci(card
);
749 /* When the OHCI controller is enabled, the config rom update
750 * mechanism is a bit tricky, but easy enough to use. See
751 * section 5.5.6 in the OHCI specification.
753 * The OHCI controller caches the new config rom address in a
754 * shadow register (ConfigROMmapNext) and needs a bus reset
755 * for the changes to take place. When the bus reset is
756 * detected, the controller loads the new values for the
757 * ConfigRomHeader and BusOptions registers from the specified
758 * config rom and loads ConfigROMmap from the ConfigROMmapNext
759 * shadow register. All automatically and atomically.
761 * Now, there's a twist to this story. The automatic load of
762 * ConfigRomHeader and BusOptions doesn't honor the
763 * noByteSwapData bit, so with a be32 config rom, the
764 * controller will load be32 values in to these registers
765 * during the atomic update, even on litte endian
766 * architectures. The workaround we use is to put a 0 in the
767 * header quadlet; 0 is endian agnostic and means that the
768 * config rom isn't ready yet. In the bus reset tasklet we
769 * then set up the real values for the two registers.
771 * We use ohci->lock to avoid racing with the code that sets
772 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
776 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
777 &next_config_rom_bus
, GFP_KERNEL
);
778 if (next_config_rom
== NULL
)
781 spin_lock_irqsave(&ohci
->lock
, flags
);
783 if (ohci
->next_config_rom
== NULL
) {
784 ohci
->next_config_rom
= next_config_rom
;
785 ohci
->next_config_rom_bus
= next_config_rom_bus
;
787 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
788 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
791 ohci
->next_header
= config_rom
[0];
792 ohci
->next_config_rom
[0] = 0;
794 reg_write(ohci
, OHCI1394_ConfigROMmap
,
795 ohci
->next_config_rom_bus
);
797 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
798 next_config_rom
, next_config_rom_bus
);
802 spin_unlock_irqrestore(&ohci
->lock
, flags
);
804 /* Now initiate a bus reset to have the changes take
805 * effect. We clean up the old config rom memory and DMA
806 * mappings in the bus reset tasklet, since the OHCI
807 * controller could need to access it before the bus reset
810 fw_core_initiate_bus_reset(&ohci
->card
, 1);
815 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
817 struct fw_ohci
*ohci
= fw_ohci(card
);
819 at_context_transmit(&ohci
->at_request_ctx
, packet
);
822 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
824 struct fw_ohci
*ohci
= fw_ohci(card
);
826 at_context_transmit(&ohci
->at_response_ctx
, packet
);
830 ohci_enable_phys_dma(struct fw_card
*card
, int node_id
, int generation
)
832 struct fw_ohci
*ohci
= fw_ohci(card
);
836 /* FIXME: make sure this bitmask is cleared when we clear the
837 * busReset interrupt bit. */
839 spin_lock_irqsave(&ohci
->lock
, flags
);
841 if (ohci
->generation
!= generation
) {
847 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << node_id
);
849 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
,
850 1 << (node_id
- 32));
854 spin_unlock_irqrestore(&ohci
->lock
, flags
);
860 static void ir_context_tasklet(unsigned long data
)
862 struct iso_context
*ctx
= (struct iso_context
*)data
;
867 #define ISO_BUFFER_SIZE (64 * 1024)
869 static void flush_iso_context(struct iso_context
*ctx
)
871 struct fw_ohci
*ohci
= fw_ohci(ctx
->base
.card
);
872 struct descriptor
*d
, *last
;
876 dma_sync_single_for_cpu(ohci
->card
.device
, ctx
->buffer_bus
,
877 ISO_BUFFER_SIZE
, DMA_TO_DEVICE
);
879 d
= ctx
->tail_descriptor
;
880 last
= ctx
->tail_descriptor_last
;
882 while (last
->branch_address
!= 0 && last
->transfer_status
!= 0) {
883 address
= le32_to_cpu(last
->branch_address
);
885 d
= ctx
->buffer
+ (address
- ctx
->buffer_bus
) / sizeof *d
;
892 if (le16_to_cpu(last
->control
) & descriptor_irq_always
)
893 ctx
->base
.callback(&ctx
->base
,
894 0, le16_to_cpu(last
->res_count
),
895 ctx
->base
.callback_data
);
898 ctx
->tail_descriptor
= d
;
899 ctx
->tail_descriptor_last
= last
;
902 static void it_context_tasklet(unsigned long data
)
904 struct iso_context
*ctx
= (struct iso_context
*)data
;
906 flush_iso_context(ctx
);
909 static struct fw_iso_context
*ohci_allocate_iso_context(struct fw_card
*card
,
912 struct fw_ohci
*ohci
= fw_ohci(card
);
913 struct iso_context
*ctx
, *list
;
914 void (*tasklet
) (unsigned long data
);
919 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
920 mask
= &ohci
->it_context_mask
;
921 list
= ohci
->it_context_list
;
922 tasklet
= it_context_tasklet
;
924 mask
= &ohci
->ir_context_mask
;
925 list
= ohci
->ir_context_list
;
926 tasklet
= ir_context_tasklet
;
929 spin_lock_irqsave(&ohci
->lock
, flags
);
930 index
= ffs(*mask
) - 1;
932 *mask
&= ~(1 << index
);
933 spin_unlock_irqrestore(&ohci
->lock
, flags
);
936 return ERR_PTR(-EBUSY
);
939 memset(ctx
, 0, sizeof *ctx
);
940 tasklet_init(&ctx
->tasklet
, tasklet
, (unsigned long)ctx
);
942 ctx
->buffer
= kmalloc(ISO_BUFFER_SIZE
, GFP_KERNEL
);
943 if (ctx
->buffer
== NULL
) {
944 spin_lock_irqsave(&ohci
->lock
, flags
);
946 spin_unlock_irqrestore(&ohci
->lock
, flags
);
947 return ERR_PTR(-ENOMEM
);
951 dma_map_single(card
->device
, ctx
->buffer
,
952 ISO_BUFFER_SIZE
, DMA_TO_DEVICE
);
954 ctx
->head_descriptor
= ctx
->buffer
;
955 ctx
->prev_descriptor
= ctx
->buffer
;
956 ctx
->tail_descriptor
= ctx
->buffer
;
957 ctx
->tail_descriptor_last
= ctx
->buffer
;
959 /* We put a dummy descriptor in the buffer that has a NULL
960 * branch address and looks like it's been sent. That way we
961 * have a descriptor to append DMA programs to. Also, the
962 * ring buffer invariant is that it always has at least one
963 * element so that head == tail means buffer full. */
965 memset(ctx
->head_descriptor
, 0, sizeof *ctx
->head_descriptor
);
966 ctx
->head_descriptor
->control
= cpu_to_le16(descriptor_output_last
);
967 ctx
->head_descriptor
->transfer_status
= cpu_to_le16(0x8011);
968 ctx
->head_descriptor
++;
973 static int ohci_send_iso(struct fw_iso_context
*base
, s32 cycle
)
975 struct iso_context
*ctx
= (struct iso_context
*)base
;
976 struct fw_ohci
*ohci
= fw_ohci(ctx
->base
.card
);
980 index
= ctx
- ohci
->it_context_list
;
982 cycle_match
= CONTEXT_CYCLE_MATCH_ENABLE
|
983 (cycle
& 0x7fff) << 16;
985 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
986 reg_write(ohci
, OHCI1394_IsoXmitCommandPtr(index
),
987 le32_to_cpu(ctx
->tail_descriptor_last
->branch_address
));
988 reg_write(ohci
, OHCI1394_IsoXmitContextControlClear(index
), ~0);
989 reg_write(ohci
, OHCI1394_IsoXmitContextControlSet(index
),
990 CONTEXT_RUN
| cycle_match
);
996 static void ohci_free_iso_context(struct fw_iso_context
*base
)
998 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
999 struct iso_context
*ctx
= (struct iso_context
*)base
;
1000 unsigned long flags
;
1003 flush_iso_context(ctx
);
1005 spin_lock_irqsave(&ohci
->lock
, flags
);
1007 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1008 index
= ctx
- ohci
->it_context_list
;
1009 reg_write(ohci
, OHCI1394_IsoXmitContextControlClear(index
), ~0);
1010 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
1011 ohci
->it_context_mask
|= 1 << index
;
1013 index
= ctx
- ohci
->ir_context_list
;
1014 reg_write(ohci
, OHCI1394_IsoRcvContextControlClear(index
), ~0);
1015 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
1016 ohci
->ir_context_mask
|= 1 << index
;
1020 dma_unmap_single(ohci
->card
.device
, ctx
->buffer_bus
,
1021 ISO_BUFFER_SIZE
, DMA_TO_DEVICE
);
1023 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1027 ohci_queue_iso(struct fw_iso_context
*base
,
1028 struct fw_iso_packet
*packet
, void *payload
)
1030 struct iso_context
*ctx
= (struct iso_context
*)base
;
1031 struct fw_ohci
*ohci
= fw_ohci(ctx
->base
.card
);
1032 struct descriptor
*d
, *end
, *last
, *tail
, *pd
;
1033 struct fw_iso_packet
*p
;
1036 u32 z
, header_z
, payload_z
, irq
;
1037 u32 payload_index
, payload_end_index
, next_page_index
;
1038 int index
, page
, end_page
, i
, length
, offset
;
1040 /* FIXME: Cycle lost behavior should be configurable: lose
1041 * packet, retransmit or terminate.. */
1044 payload_index
= payload
- ctx
->base
.buffer
;
1045 d
= ctx
->head_descriptor
;
1046 tail
= ctx
->tail_descriptor
;
1047 end
= ctx
->buffer
+ ISO_BUFFER_SIZE
/ sizeof(struct descriptor
);
1053 if (p
->header_length
> 0)
1056 /* Determine the first page the payload isn't contained in. */
1057 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
1058 if (p
->payload_length
> 0)
1059 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
1065 /* Get header size in number of descriptors. */
1066 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof *d
);
1068 if (d
+ z
+ header_z
<= tail
) {
1070 } else if (d
> tail
&& d
+ z
+ header_z
<= end
) {
1072 } else if (d
> tail
&& ctx
->buffer
+ z
+ header_z
<= tail
) {
1077 /* No space in buffer */
1081 memset(d
, 0, (z
+ header_z
) * sizeof *d
);
1082 d_bus
= ctx
->buffer_bus
+ (d
- ctx
->buffer
) * sizeof *d
;
1085 d
[0].control
= cpu_to_le16(descriptor_key_immediate
);
1086 d
[0].req_count
= cpu_to_le16(8);
1088 header
= (__le32
*) &d
[1];
1089 header
[0] = cpu_to_le32(it_header_sy(p
->sy
) |
1090 it_header_tag(p
->tag
) |
1091 it_header_tcode(TCODE_STREAM_DATA
) |
1092 it_header_channel(ctx
->base
.channel
) |
1093 it_header_speed(ctx
->base
.speed
));
1095 cpu_to_le32(it_header_data_length(p
->header_length
+
1096 p
->payload_length
));
1099 if (p
->header_length
> 0) {
1100 d
[2].req_count
= cpu_to_le16(p
->header_length
);
1101 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof *d
);
1102 memcpy(&d
[z
], p
->header
, p
->header_length
);
1105 pd
= d
+ z
- payload_z
;
1106 payload_end_index
= payload_index
+ p
->payload_length
;
1107 for (i
= 0; i
< payload_z
; i
++) {
1108 page
= payload_index
>> PAGE_SHIFT
;
1109 offset
= payload_index
& ~PAGE_MASK
;
1110 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
1112 min(next_page_index
, payload_end_index
) - payload_index
;
1113 pd
[i
].req_count
= cpu_to_le16(length
);
1114 pd
[i
].data_address
= cpu_to_le32(ctx
->base
.pages
[page
] + offset
);
1116 payload_index
+= length
;
1125 irq
= descriptor_irq_always
;
1127 irq
= descriptor_no_irq
;
1129 last
->control
= cpu_to_le16(descriptor_output_last
|
1131 descriptor_branch_always
|
1134 dma_sync_single_for_device(ohci
->card
.device
, ctx
->buffer_bus
,
1135 ISO_BUFFER_SIZE
, DMA_TO_DEVICE
);
1137 ctx
->head_descriptor
= d
+ z
+ header_z
;
1138 ctx
->prev_descriptor
->branch_address
= cpu_to_le32(d_bus
| z
);
1139 ctx
->prev_descriptor
= last
;
1141 index
= ctx
- ohci
->it_context_list
;
1142 reg_write(ohci
, OHCI1394_IsoXmitContextControlSet(index
), CONTEXT_WAKE
);
1148 static const struct fw_card_driver ohci_driver
= {
1149 .name
= ohci_driver_name
,
1150 .enable
= ohci_enable
,
1151 .update_phy_reg
= ohci_update_phy_reg
,
1152 .set_config_rom
= ohci_set_config_rom
,
1153 .send_request
= ohci_send_request
,
1154 .send_response
= ohci_send_response
,
1155 .enable_phys_dma
= ohci_enable_phys_dma
,
1157 .allocate_iso_context
= ohci_allocate_iso_context
,
1158 .free_iso_context
= ohci_free_iso_context
,
1159 .queue_iso
= ohci_queue_iso
,
1160 .send_iso
= ohci_send_iso
1163 static int software_reset(struct fw_ohci
*ohci
)
1167 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1169 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1170 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1171 OHCI1394_HCControl_softReset
) == 0)
1179 /* ---------- pci subsystem interface ---------- */
1189 static int cleanup(struct fw_ohci
*ohci
, int stage
, int code
)
1191 struct pci_dev
*dev
= to_pci_dev(ohci
->card
.device
);
1194 case CLEANUP_SELF_ID
:
1195 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
1196 ohci
->self_id_cpu
, ohci
->self_id_bus
);
1197 case CLEANUP_REGISTERS
:
1198 kfree(ohci
->it_context_list
);
1199 kfree(ohci
->ir_context_list
);
1200 pci_iounmap(dev
, ohci
->registers
);
1202 pci_release_region(dev
, 0);
1203 case CLEANUP_DISABLE
:
1204 pci_disable_device(dev
);
1205 case CLEANUP_PUT_CARD
:
1206 fw_card_put(&ohci
->card
);
1212 static int __devinit
1213 pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
1215 struct fw_ohci
*ohci
;
1216 u32 bus_options
, max_receive
, link_speed
;
1221 ohci
= kzalloc(sizeof *ohci
, GFP_KERNEL
);
1223 fw_error("Could not malloc fw_ohci data.\n");
1227 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
1229 if (pci_enable_device(dev
)) {
1230 fw_error("Failed to enable OHCI hardware.\n");
1231 return cleanup(ohci
, CLEANUP_PUT_CARD
, -ENODEV
);
1234 pci_set_master(dev
);
1235 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
1236 pci_set_drvdata(dev
, ohci
);
1238 spin_lock_init(&ohci
->lock
);
1240 tasklet_init(&ohci
->bus_reset_tasklet
,
1241 bus_reset_tasklet
, (unsigned long)ohci
);
1243 if (pci_request_region(dev
, 0, ohci_driver_name
)) {
1244 fw_error("MMIO resource unavailable\n");
1245 return cleanup(ohci
, CLEANUP_DISABLE
, -EBUSY
);
1248 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
1249 if (ohci
->registers
== NULL
) {
1250 fw_error("Failed to remap registers\n");
1251 return cleanup(ohci
, CLEANUP_IOMEM
, -ENXIO
);
1254 if (software_reset(ohci
)) {
1255 fw_error("Failed to reset ohci card.\n");
1256 return cleanup(ohci
, CLEANUP_REGISTERS
, -EBUSY
);
1259 /* Now enable LPS, which we need in order to start accessing
1260 * most of the registers. In fact, on some cards (ALI M5251),
1261 * accessing registers in the SClk domain without LPS enabled
1262 * will lock up the machine. Wait 50msec to make sure we have
1263 * full link enabled. */
1264 reg_write(ohci
, OHCI1394_HCControlSet
,
1265 OHCI1394_HCControl_LPS
|
1266 OHCI1394_HCControl_postedWriteEnable
);
1270 reg_write(ohci
, OHCI1394_HCControlClear
,
1271 OHCI1394_HCControl_noByteSwapData
);
1273 reg_write(ohci
, OHCI1394_LinkControlSet
,
1274 OHCI1394_LinkControl_rcvSelfID
|
1275 OHCI1394_LinkControl_cycleTimerEnable
|
1276 OHCI1394_LinkControl_cycleMaster
);
1278 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
1279 OHCI1394_AsReqRcvContextControlSet
);
1281 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
1282 OHCI1394_AsRspRcvContextControlSet
);
1284 at_context_init(&ohci
->at_request_ctx
, ohci
,
1285 OHCI1394_AsReqTrContextControlSet
);
1287 at_context_init(&ohci
->at_response_ctx
, ohci
,
1288 OHCI1394_AsRspTrContextControlSet
);
1290 reg_write(ohci
, OHCI1394_ATRetries
,
1291 OHCI1394_MAX_AT_REQ_RETRIES
|
1292 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1293 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1295 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
1296 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
1297 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
1298 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
1299 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
1301 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
1302 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
1303 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
1304 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
1305 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
1307 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
1308 fw_error("Out of memory for it/ir contexts.\n");
1309 return cleanup(ohci
, CLEANUP_REGISTERS
, -ENOMEM
);
1312 /* self-id dma buffer allocation */
1313 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
1317 if (ohci
->self_id_cpu
== NULL
) {
1318 fw_error("Out of memory for self ID buffer.\n");
1319 return cleanup(ohci
, CLEANUP_REGISTERS
, -ENOMEM
);
1322 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1323 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1324 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1325 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1326 reg_write(ohci
, OHCI1394_IntMaskSet
,
1327 OHCI1394_selfIDComplete
|
1328 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1329 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1330 OHCI1394_isochRx
| OHCI1394_isochTx
|
1331 OHCI1394_masterIntEnable
);
1333 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
1334 max_receive
= (bus_options
>> 12) & 0xf;
1335 link_speed
= bus_options
& 0x7;
1336 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
1337 reg_read(ohci
, OHCI1394_GUIDLo
);
1339 error_code
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
1341 return cleanup(ohci
, CLEANUP_SELF_ID
, error_code
);
1343 fw_notify("Added fw-ohci device %s.\n", dev
->dev
.bus_id
);
1348 static void pci_remove(struct pci_dev
*dev
)
1350 struct fw_ohci
*ohci
;
1352 ohci
= pci_get_drvdata(dev
);
1353 reg_write(ohci
, OHCI1394_IntMaskClear
, OHCI1394_masterIntEnable
);
1354 fw_core_remove_card(&ohci
->card
);
1356 /* FIXME: Fail all pending packets here, now that the upper
1357 * layers can't queue any more. */
1359 software_reset(ohci
);
1360 free_irq(dev
->irq
, ohci
);
1361 cleanup(ohci
, CLEANUP_SELF_ID
, 0);
1363 fw_notify("Removed fw-ohci device.\n");
1366 static struct pci_device_id pci_table
[] = {
1367 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
1371 MODULE_DEVICE_TABLE(pci
, pci_table
);
1373 static struct pci_driver fw_ohci_pci_driver
= {
1374 .name
= ohci_driver_name
,
1375 .id_table
= pci_table
,
1377 .remove
= pci_remove
,
1380 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1381 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1382 MODULE_LICENSE("GPL");
1384 static int __init
fw_ohci_init(void)
1386 return pci_register_driver(&fw_ohci_pci_driver
);
1389 static void __exit
fw_ohci_cleanup(void)
1391 pci_unregister_driver(&fw_ohci_pci_driver
);
1394 module_init(fw_ohci_init
);
1395 module_exit(fw_ohci_cleanup
);