1 /* -*- c-basic-offset: 8 -*-
3 * fw-ohci.c - Driver for OHCI 1394 boards
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/poll.h>
28 #include <asm/uaccess.h>
29 #include <asm/semaphore.h>
31 #include "fw-transaction.h"
34 #define descriptor_output_more 0
35 #define descriptor_output_last (1 << 12)
36 #define descriptor_input_more (2 << 12)
37 #define descriptor_input_last (3 << 12)
38 #define descriptor_status (1 << 11)
39 #define descriptor_key_immediate (2 << 8)
40 #define descriptor_ping (1 << 7)
41 #define descriptor_yy (1 << 6)
42 #define descriptor_no_irq (0 << 4)
43 #define descriptor_irq_error (1 << 4)
44 #define descriptor_irq_always (3 << 4)
45 #define descriptor_branch_always (3 << 2)
51 __le32 branch_address
;
53 __le16 transfer_status
;
54 } __attribute__((aligned(16)));
58 struct descriptor descriptor
;
60 dma_addr_t descriptor_bus
;
61 dma_addr_t buffer_bus
;
67 struct tasklet_struct tasklet
;
72 dma_addr_t descriptor_bus
;
73 dma_addr_t buffer_bus
;
75 struct list_head list
;
78 struct descriptor more
;
80 struct descriptor last
;
87 struct tasklet_struct tasklet
;
90 #define it_header_sy(v) ((v) << 0)
91 #define it_header_tcode(v) ((v) << 4)
92 #define it_header_channel(v) ((v) << 8)
93 #define it_header_tag(v) ((v) << 14)
94 #define it_header_speed(v) ((v) << 16)
95 #define it_header_data_length(v) ((v) << 16)
98 struct fw_iso_context base
;
99 struct tasklet_struct tasklet
;
105 struct descriptor
*buffer
;
106 dma_addr_t buffer_bus
;
107 struct descriptor
*head_descriptor
;
108 struct descriptor
*tail_descriptor
;
109 struct descriptor
*tail_descriptor_last
;
110 struct descriptor
*prev_descriptor
;
113 #define CONFIG_ROM_SIZE 1024
118 __iomem
char *registers
;
119 dma_addr_t self_id_bus
;
121 struct tasklet_struct bus_reset_tasklet
;
123 int request_generation
;
125 /* Spinlock for accessing fw_ohci data. Never call out of
126 * this driver with this lock held. */
128 u32 self_id_buffer
[512];
130 /* Config rom buffers */
132 dma_addr_t config_rom_bus
;
133 __be32
*next_config_rom
;
134 dma_addr_t next_config_rom_bus
;
137 struct ar_context ar_request_ctx
;
138 struct ar_context ar_response_ctx
;
139 struct at_context at_request_ctx
;
140 struct at_context at_response_ctx
;
143 struct iso_context
*it_context_list
;
145 struct iso_context
*ir_context_list
;
148 extern inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
150 return container_of(card
, struct fw_ohci
, card
);
153 #define CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
155 #define CONTEXT_RUN 0x8000
156 #define CONTEXT_WAKE 0x1000
157 #define CONTEXT_DEAD 0x0800
158 #define CONTEXT_ACTIVE 0x0400
160 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
161 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
162 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
164 #define FW_OHCI_MAJOR 240
165 #define OHCI1394_REGISTER_SIZE 0x800
166 #define OHCI_LOOP_COUNT 500
167 #define OHCI1394_PCI_HCI_Control 0x40
168 #define SELF_ID_BUF_SIZE 0x800
170 /* FIXME: Move this to linux/pci_ids.h */
171 #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
173 static char ohci_driver_name
[] = KBUILD_MODNAME
;
175 extern inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
177 writel(data
, ohci
->registers
+ offset
);
180 extern inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
182 return readl(ohci
->registers
+ offset
);
185 extern inline void flush_writes(const struct fw_ohci
*ohci
)
187 /* Do a dummy read to flush writes. */
188 reg_read(ohci
, OHCI1394_Version
);
192 ohci_update_phy_reg(struct fw_card
*card
, int addr
,
193 int clear_bits
, int set_bits
)
195 struct fw_ohci
*ohci
= fw_ohci(card
);
198 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
200 val
= reg_read(ohci
, OHCI1394_PhyControl
);
201 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
202 fw_error("failed to set phy reg bits.\n");
206 old
= OHCI1394_PhyControl_ReadData(val
);
207 old
= (old
& ~clear_bits
) | set_bits
;
208 reg_write(ohci
, OHCI1394_PhyControl
,
209 OHCI1394_PhyControl_Write(addr
, old
));
214 static void ar_context_run(struct ar_context
*ctx
)
216 reg_write(ctx
->ohci
, ctx
->command_ptr
, ctx
->descriptor_bus
| 1);
217 reg_write(ctx
->ohci
, ctx
->control_set
, CONTEXT_RUN
);
218 flush_writes(ctx
->ohci
);
221 static void ar_context_tasklet(unsigned long data
)
223 struct ar_context
*ctx
= (struct ar_context
*)data
;
224 struct fw_ohci
*ohci
= ctx
->ohci
;
226 int length
, speed
, ack
, timestamp
, tcode
;
228 /* FIXME: What to do about evt_* errors? */
229 length
= le16_to_cpu(ctx
->descriptor
.req_count
) -
230 le16_to_cpu(ctx
->descriptor
.res_count
) - 4;
231 status
= le32_to_cpu(ctx
->buffer
[length
/ 4]);
232 ack
= ((status
>> 16) & 0x1f) - 16;
233 speed
= (status
>> 21) & 0x7;
234 timestamp
= status
& 0xffff;
236 ctx
->buffer
[0] = le32_to_cpu(ctx
->buffer
[0]);
237 ctx
->buffer
[1] = le32_to_cpu(ctx
->buffer
[1]);
238 ctx
->buffer
[2] = le32_to_cpu(ctx
->buffer
[2]);
240 tcode
= (ctx
->buffer
[0] >> 4) & 0x0f;
241 if (TCODE_IS_BLOCK_PACKET(tcode
))
242 ctx
->buffer
[3] = le32_to_cpu(ctx
->buffer
[3]);
244 /* The OHCI bus reset handler synthesizes a phy packet with
245 * the new generation number when a bus reset happens (see
246 * section 8.4.2.3). This helps us determine when a request
247 * was received and make sure we send the response in the same
248 * generation. We only need this for requests; for responses
249 * we use the unique tlabel for finding the matching
252 if (ack
+ 16 == 0x09)
253 ohci
->request_generation
= (ctx
->buffer
[2] >> 16) & 0xff;
254 else if (ctx
== &ohci
->ar_request_ctx
)
255 fw_core_handle_request(&ohci
->card
, speed
, ack
, timestamp
,
256 ohci
->request_generation
,
257 length
, ctx
->buffer
);
259 fw_core_handle_response(&ohci
->card
, speed
, ack
, timestamp
,
260 length
, ctx
->buffer
);
262 ctx
->descriptor
.data_address
= cpu_to_le32(ctx
->buffer_bus
);
263 ctx
->descriptor
.req_count
= cpu_to_le16(sizeof ctx
->buffer
);
264 ctx
->descriptor
.res_count
= cpu_to_le16(sizeof ctx
->buffer
);
266 dma_sync_single_for_device(ohci
->card
.device
, ctx
->descriptor_bus
,
267 sizeof ctx
->descriptor_bus
, DMA_TO_DEVICE
);
269 /* FIXME: We stop and restart the ar context here, what if we
270 * stop while a receive is in progress? Maybe we could just
271 * loop the context back to itself and use it in buffer fill
272 * mode as intended... */
274 reg_write(ctx
->ohci
, ctx
->control_clear
, CONTEXT_RUN
);
279 ar_context_init(struct ar_context
*ctx
, struct fw_ohci
*ohci
, u32 control_set
)
281 ctx
->descriptor_bus
=
282 dma_map_single(ohci
->card
.device
, &ctx
->descriptor
,
283 sizeof ctx
->descriptor
, DMA_TO_DEVICE
);
284 if (ctx
->descriptor_bus
== 0)
287 if (ctx
->descriptor_bus
& 0xf)
288 fw_notify("descriptor not 16-byte aligned: 0x%08x\n",
289 ctx
->descriptor_bus
);
292 dma_map_single(ohci
->card
.device
, ctx
->buffer
,
293 sizeof ctx
->buffer
, DMA_FROM_DEVICE
);
295 if (ctx
->buffer_bus
== 0) {
296 dma_unmap_single(ohci
->card
.device
, ctx
->descriptor_bus
,
297 sizeof ctx
->descriptor
, DMA_TO_DEVICE
);
301 memset(&ctx
->descriptor
, 0, sizeof ctx
->descriptor
);
302 ctx
->descriptor
.control
= cpu_to_le16(descriptor_input_more
|
304 descriptor_branch_always
);
305 ctx
->descriptor
.req_count
= cpu_to_le16(sizeof ctx
->buffer
);
306 ctx
->descriptor
.data_address
= cpu_to_le32(ctx
->buffer_bus
);
307 ctx
->descriptor
.res_count
= cpu_to_le16(sizeof ctx
->buffer
);
309 ctx
->control_set
= control_set
;
310 ctx
->control_clear
= control_set
+ 4;
311 ctx
->command_ptr
= control_set
+ 12;
314 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
322 do_packet_callbacks(struct fw_ohci
*ohci
, struct list_head
*list
)
324 struct fw_packet
*p
, *next
;
326 list_for_each_entry_safe(p
, next
, list
, link
)
327 p
->callback(p
, &ohci
->card
, p
->status
);
331 complete_transmission(struct fw_packet
*packet
,
332 int status
, struct list_head
*list
)
334 list_move_tail(&packet
->link
, list
);
335 packet
->status
= status
;
338 /* This function prepares the first packet in the context queue for
339 * transmission. Must always be called with the ochi->lock held to
340 * ensure proper generation handling and locking around packet queue
343 at_context_setup_packet(struct at_context
*ctx
, struct list_head
*list
)
345 struct fw_packet
*packet
;
346 struct fw_ohci
*ohci
= ctx
->ohci
;
349 packet
= fw_packet(ctx
->list
.next
);
351 memset(&ctx
->d
, 0, sizeof ctx
->d
);
352 if (packet
->payload_length
> 0) {
353 packet
->payload_bus
= dma_map_single(ohci
->card
.device
,
355 packet
->payload_length
,
357 if (packet
->payload_bus
== 0) {
358 complete_transmission(packet
, -ENOMEM
, list
);
362 ctx
->d
.more
.control
=
363 cpu_to_le16(descriptor_output_more
|
364 descriptor_key_immediate
);
365 ctx
->d
.more
.req_count
= cpu_to_le16(packet
->header_length
);
366 ctx
->d
.more
.res_count
= cpu_to_le16(packet
->timestamp
);
367 ctx
->d
.last
.control
=
368 cpu_to_le16(descriptor_output_last
|
369 descriptor_irq_always
|
370 descriptor_branch_always
);
371 ctx
->d
.last
.req_count
= cpu_to_le16(packet
->payload_length
);
372 ctx
->d
.last
.data_address
= cpu_to_le32(packet
->payload_bus
);
375 ctx
->d
.more
.control
=
376 cpu_to_le16(descriptor_output_last
|
377 descriptor_key_immediate
|
378 descriptor_irq_always
|
379 descriptor_branch_always
);
380 ctx
->d
.more
.req_count
= cpu_to_le16(packet
->header_length
);
381 ctx
->d
.more
.res_count
= cpu_to_le16(packet
->timestamp
);
385 /* The DMA format for asyncronous link packets is different
386 * from the IEEE1394 layout, so shift the fields around
387 * accordingly. If header_length is 8, it's a PHY packet, to
388 * which we need to prepend an extra quadlet. */
389 if (packet
->header_length
> 8) {
390 ctx
->d
.header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
391 (packet
->speed
<< 16));
392 ctx
->d
.header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
393 (packet
->header
[0] & 0xffff0000));
394 ctx
->d
.header
[2] = cpu_to_le32(packet
->header
[2]);
396 tcode
= (packet
->header
[0] >> 4) & 0x0f;
397 if (TCODE_IS_BLOCK_PACKET(tcode
))
398 ctx
->d
.header
[3] = cpu_to_le32(packet
->header
[3]);
400 ctx
->d
.header
[3] = packet
->header
[3];
403 cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
404 (packet
->speed
<< 16));
405 ctx
->d
.header
[1] = cpu_to_le32(packet
->header
[0]);
406 ctx
->d
.header
[2] = cpu_to_le32(packet
->header
[1]);
407 ctx
->d
.more
.req_count
= cpu_to_le16(12);
410 /* FIXME: Document how the locking works. */
411 if (ohci
->generation
== packet
->generation
) {
412 reg_write(ctx
->ohci
, ctx
->command_ptr
,
413 ctx
->descriptor_bus
| z
);
414 reg_write(ctx
->ohci
, ctx
->control_set
,
415 CONTEXT_RUN
| CONTEXT_WAKE
);
417 /* We dont return error codes from this function; all
418 * transmission errors are reported through the
420 complete_transmission(packet
, -ESTALE
, list
);
424 static void at_context_stop(struct at_context
*ctx
)
428 reg_write(ctx
->ohci
, ctx
->control_clear
, CONTEXT_RUN
);
430 reg
= reg_read(ctx
->ohci
, ctx
->control_set
);
431 if (reg
& CONTEXT_ACTIVE
)
432 fw_notify("Tried to stop context, but it is still active "
436 static void at_context_tasklet(unsigned long data
)
438 struct at_context
*ctx
= (struct at_context
*)data
;
439 struct fw_ohci
*ohci
= ctx
->ohci
;
440 struct fw_packet
*packet
;
445 spin_lock_irqsave(&ohci
->lock
, flags
);
447 packet
= fw_packet(ctx
->list
.next
);
449 at_context_stop(ctx
);
451 if (packet
->payload_length
> 0) {
452 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
453 packet
->payload_length
, DMA_TO_DEVICE
);
454 evt
= le16_to_cpu(ctx
->d
.last
.transfer_status
) & 0x1f;
455 packet
->timestamp
= le16_to_cpu(ctx
->d
.last
.res_count
);
458 evt
= le16_to_cpu(ctx
->d
.more
.transfer_status
) & 0x1f;
459 packet
->timestamp
= le16_to_cpu(ctx
->d
.more
.res_count
);
464 case OHCI1394_evt_timeout
:
465 /* Async response transmit timed out. */
466 complete_transmission(packet
, -ETIMEDOUT
, &list
);
469 case OHCI1394_evt_flushed
:
470 /* The packet was flushed should give same
471 * error as when we try to use a stale
472 * generation count. */
473 complete_transmission(packet
, -ESTALE
, &list
);
476 case OHCI1394_evt_missing_ack
:
477 /* This would be a higher level software
478 * error, it is using a valid (current)
479 * generation count, but the node is not on
481 complete_transmission(packet
, -ENODEV
, &list
);
485 complete_transmission(packet
, -EIO
, &list
);
489 complete_transmission(packet
, evt
- 16, &list
);
491 /* If more packets are queued, set up the next one. */
492 if (!list_empty(&ctx
->list
))
493 at_context_setup_packet(ctx
, &list
);
495 spin_unlock_irqrestore(&ohci
->lock
, flags
);
497 do_packet_callbacks(ohci
, &list
);
501 at_context_init(struct at_context
*ctx
, struct fw_ohci
*ohci
, u32 control_set
)
503 INIT_LIST_HEAD(&ctx
->list
);
505 ctx
->descriptor_bus
=
506 dma_map_single(ohci
->card
.device
, &ctx
->d
,
507 sizeof ctx
->d
, DMA_TO_DEVICE
);
508 if (ctx
->descriptor_bus
== 0)
511 ctx
->control_set
= control_set
;
512 ctx
->control_clear
= control_set
+ 4;
513 ctx
->command_ptr
= control_set
+ 12;
516 tasklet_init(&ctx
->tasklet
, at_context_tasklet
, (unsigned long)ctx
);
522 at_context_transmit(struct at_context
*ctx
, struct fw_packet
*packet
)
528 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
530 was_empty
= list_empty(&ctx
->list
);
531 list_add_tail(&packet
->link
, &ctx
->list
);
533 at_context_setup_packet(ctx
, &list
);
535 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
537 do_packet_callbacks(ctx
->ohci
, &list
);
540 static void bus_reset_tasklet(unsigned long data
)
542 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
543 int self_id_count
, i
, j
, reg
, node_id
;
544 int generation
, new_generation
;
547 reg
= reg_read(ohci
, OHCI1394_NodeID
);
548 if (!(reg
& OHCI1394_NodeID_idValid
)) {
549 fw_error("node ID not valid, new bus reset in progress\n");
552 node_id
= reg
& 0xffff;
554 /* The count in the SelfIDCount register is the number of
555 * bytes in the self ID receive buffer. Since we also receive
556 * the inverted quadlets and a header quadlet, we shift one
557 * bit extra to get the actual number of self IDs. */
559 self_id_count
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 3) & 0x3ff;
560 generation
= (le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
562 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
563 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1])
564 fw_error("inconsistent self IDs\n");
565 ohci
->self_id_buffer
[j
] = le32_to_cpu(ohci
->self_id_cpu
[i
]);
568 /* Check the consistency of the self IDs we just read. The
569 * problem we face is that a new bus reset can start while we
570 * read out the self IDs from the DMA buffer. If this happens,
571 * the DMA buffer will be overwritten with new self IDs and we
572 * will read out inconsistent data. The OHCI specification
573 * (section 11.2) recommends a technique similar to
574 * linux/seqlock.h, where we remember the generation of the
575 * self IDs in the buffer before reading them out and compare
576 * it to the current generation after reading them out. If
577 * the two generations match we know we have a consistent set
580 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
581 if (new_generation
!= generation
) {
582 fw_notify("recursive bus reset detected, "
583 "discarding self ids\n");
587 /* FIXME: Document how the locking works. */
588 spin_lock_irqsave(&ohci
->lock
, flags
);
590 ohci
->generation
= generation
;
591 at_context_stop(&ohci
->at_request_ctx
);
592 at_context_stop(&ohci
->at_response_ctx
);
593 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
595 /* This next bit is unrelated to the AT context stuff but we
596 * have to do it under the spinlock also. If a new config rom
597 * was set up before this reset, the old one is now no longer
598 * in use and we can free it. Update the config rom pointers
599 * to point to the current config rom and clear the
600 * next_config_rom pointer so a new udpate can take place. */
602 if (ohci
->next_config_rom
!= NULL
) {
603 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
604 ohci
->config_rom
, ohci
->config_rom_bus
);
605 ohci
->config_rom
= ohci
->next_config_rom
;
606 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
607 ohci
->next_config_rom
= NULL
;
609 /* Restore config_rom image and manually update
610 * config_rom registers. Writing the header quadlet
611 * will indicate that the config rom is ready, so we
613 reg_write(ohci
, OHCI1394_BusOptions
,
614 be32_to_cpu(ohci
->config_rom
[2]));
615 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
616 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
619 spin_unlock_irqrestore(&ohci
->lock
, flags
);
621 fw_core_handle_bus_reset(&ohci
->card
, node_id
, generation
,
622 self_id_count
, ohci
->self_id_buffer
);
625 static irqreturn_t
irq_handler(int irq
, void *data
)
627 struct fw_ohci
*ohci
= data
;
628 u32 event
, iso_event
;
631 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
636 reg_write(ohci
, OHCI1394_IntEventClear
, event
);
638 if (event
& OHCI1394_selfIDComplete
)
639 tasklet_schedule(&ohci
->bus_reset_tasklet
);
641 if (event
& OHCI1394_RQPkt
)
642 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
644 if (event
& OHCI1394_RSPkt
)
645 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
647 if (event
& OHCI1394_reqTxComplete
)
648 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
650 if (event
& OHCI1394_respTxComplete
)
651 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
653 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventSet
);
654 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
657 i
= ffs(iso_event
) - 1;
658 tasklet_schedule(&ohci
->ir_context_list
[i
].tasklet
);
659 iso_event
&= ~(1 << i
);
662 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventSet
);
663 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
666 i
= ffs(iso_event
) - 1;
667 tasklet_schedule(&ohci
->it_context_list
[i
].tasklet
);
668 iso_event
&= ~(1 << i
);
674 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
676 struct fw_ohci
*ohci
= fw_ohci(card
);
677 struct pci_dev
*dev
= to_pci_dev(card
->device
);
679 /* When the link is not yet enabled, the atomic config rom
680 * update mechanism described below in ohci_set_config_rom()
681 * is not active. We have to update ConfigRomHeader and
682 * BusOptions manually, and the write to ConfigROMmap takes
683 * effect immediately. We tie this to the enabling of the
684 * link, so we have a valid config rom before enabling - the
685 * OHCI requires that ConfigROMhdr and BusOptions have valid
686 * values before enabling.
688 * However, when the ConfigROMmap is written, some controllers
689 * always read back quadlets 0 and 2 from the config rom to
690 * the ConfigRomHeader and BusOptions registers on bus reset.
691 * They shouldn't do that in this initial case where the link
692 * isn't enabled. This means we have to use the same
693 * workaround here, setting the bus header to 0 and then write
694 * the right values in the bus reset tasklet.
697 ohci
->next_config_rom
=
698 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
699 &ohci
->next_config_rom_bus
, GFP_KERNEL
);
700 if (ohci
->next_config_rom
== NULL
)
703 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
704 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
706 ohci
->next_header
= config_rom
[0];
707 ohci
->next_config_rom
[0] = 0;
708 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
709 reg_write(ohci
, OHCI1394_BusOptions
, config_rom
[2]);
710 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
712 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
714 if (request_irq(dev
->irq
, irq_handler
,
715 SA_SHIRQ
, ohci_driver_name
, ohci
)) {
716 fw_error("Failed to allocate shared interrupt %d.\n",
718 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
719 ohci
->config_rom
, ohci
->config_rom_bus
);
723 reg_write(ohci
, OHCI1394_HCControlSet
,
724 OHCI1394_HCControl_linkEnable
|
725 OHCI1394_HCControl_BIBimageValid
);
728 /* We are ready to go, initiate bus reset to finish the
731 fw_core_initiate_bus_reset(&ohci
->card
, 1);
737 ohci_set_config_rom(struct fw_card
*card
, u32
*config_rom
, size_t length
)
739 struct fw_ohci
*ohci
;
742 __be32
*next_config_rom
;
743 dma_addr_t next_config_rom_bus
;
745 ohci
= fw_ohci(card
);
747 /* When the OHCI controller is enabled, the config rom update
748 * mechanism is a bit tricky, but easy enough to use. See
749 * section 5.5.6 in the OHCI specification.
751 * The OHCI controller caches the new config rom address in a
752 * shadow register (ConfigROMmapNext) and needs a bus reset
753 * for the changes to take place. When the bus reset is
754 * detected, the controller loads the new values for the
755 * ConfigRomHeader and BusOptions registers from the specified
756 * config rom and loads ConfigROMmap from the ConfigROMmapNext
757 * shadow register. All automatically and atomically.
759 * Now, there's a twist to this story. The automatic load of
760 * ConfigRomHeader and BusOptions doesn't honor the
761 * noByteSwapData bit, so with a be32 config rom, the
762 * controller will load be32 values in to these registers
763 * during the atomic update, even on litte endian
764 * architectures. The workaround we use is to put a 0 in the
765 * header quadlet; 0 is endian agnostic and means that the
766 * config rom isn't ready yet. In the bus reset tasklet we
767 * then set up the real values for the two registers.
769 * We use ohci->lock to avoid racing with the code that sets
770 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
774 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
775 &next_config_rom_bus
, GFP_KERNEL
);
776 if (next_config_rom
== NULL
)
779 spin_lock_irqsave(&ohci
->lock
, flags
);
781 if (ohci
->next_config_rom
== NULL
) {
782 ohci
->next_config_rom
= next_config_rom
;
783 ohci
->next_config_rom_bus
= next_config_rom_bus
;
785 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
786 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
789 ohci
->next_header
= config_rom
[0];
790 ohci
->next_config_rom
[0] = 0;
792 reg_write(ohci
, OHCI1394_ConfigROMmap
,
793 ohci
->next_config_rom_bus
);
795 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
796 next_config_rom
, next_config_rom_bus
);
800 spin_unlock_irqrestore(&ohci
->lock
, flags
);
802 /* Now initiate a bus reset to have the changes take
803 * effect. We clean up the old config rom memory and DMA
804 * mappings in the bus reset tasklet, since the OHCI
805 * controller could need to access it before the bus reset
808 fw_core_initiate_bus_reset(&ohci
->card
, 1);
813 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
815 struct fw_ohci
*ohci
= fw_ohci(card
);
817 at_context_transmit(&ohci
->at_request_ctx
, packet
);
820 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
822 struct fw_ohci
*ohci
= fw_ohci(card
);
824 at_context_transmit(&ohci
->at_response_ctx
, packet
);
828 ohci_enable_phys_dma(struct fw_card
*card
, int node_id
, int generation
)
830 struct fw_ohci
*ohci
= fw_ohci(card
);
834 /* FIXME: make sure this bitmask is cleared when we clear the
835 * busReset interrupt bit. */
837 spin_lock_irqsave(&ohci
->lock
, flags
);
839 if (ohci
->generation
!= generation
) {
845 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << node_id
);
847 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
,
848 1 << (node_id
- 32));
852 spin_unlock_irqrestore(&ohci
->lock
, flags
);
858 static void ir_context_tasklet(unsigned long data
)
860 struct iso_context
*ctx
= (struct iso_context
*)data
;
865 #define ISO_BUFFER_SIZE (64 * 1024)
867 static void flush_iso_context(struct iso_context
*ctx
)
869 struct fw_ohci
*ohci
= fw_ohci(ctx
->base
.card
);
870 struct descriptor
*d
, *last
;
874 dma_sync_single_for_cpu(ohci
->card
.device
, ctx
->buffer_bus
,
875 ISO_BUFFER_SIZE
, DMA_TO_DEVICE
);
877 d
= ctx
->tail_descriptor
;
878 last
= ctx
->tail_descriptor_last
;
880 while (last
->branch_address
!= 0 && last
->transfer_status
!= 0) {
881 address
= le32_to_cpu(last
->branch_address
);
883 d
= ctx
->buffer
+ (address
- ctx
->buffer_bus
) / sizeof *d
;
890 if (le16_to_cpu(last
->control
) & descriptor_irq_always
)
891 ctx
->base
.callback(&ctx
->base
,
892 0, le16_to_cpu(last
->res_count
),
893 ctx
->base
.callback_data
);
896 ctx
->tail_descriptor
= d
;
897 ctx
->tail_descriptor_last
= last
;
900 static void it_context_tasklet(unsigned long data
)
902 struct iso_context
*ctx
= (struct iso_context
*)data
;
904 flush_iso_context(ctx
);
907 static struct fw_iso_context
*ohci_allocate_iso_context(struct fw_card
*card
,
910 struct fw_ohci
*ohci
= fw_ohci(card
);
911 struct iso_context
*ctx
, *list
;
912 void (*tasklet
) (unsigned long data
);
917 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
918 mask
= &ohci
->it_context_mask
;
919 list
= ohci
->it_context_list
;
920 tasklet
= it_context_tasklet
;
922 mask
= &ohci
->ir_context_mask
;
923 list
= ohci
->ir_context_list
;
924 tasklet
= ir_context_tasklet
;
927 spin_lock_irqsave(&ohci
->lock
, flags
);
928 index
= ffs(*mask
) - 1;
930 *mask
&= ~(1 << index
);
931 spin_unlock_irqrestore(&ohci
->lock
, flags
);
934 return ERR_PTR(-EBUSY
);
937 memset(ctx
, 0, sizeof *ctx
);
938 tasklet_init(&ctx
->tasklet
, tasklet
, (unsigned long)ctx
);
940 ctx
->buffer
= kmalloc(ISO_BUFFER_SIZE
, GFP_KERNEL
);
941 if (ctx
->buffer
== NULL
) {
942 spin_lock_irqsave(&ohci
->lock
, flags
);
944 spin_unlock_irqrestore(&ohci
->lock
, flags
);
945 return ERR_PTR(-ENOMEM
);
949 dma_map_single(card
->device
, ctx
->buffer
,
950 ISO_BUFFER_SIZE
, DMA_TO_DEVICE
);
952 ctx
->head_descriptor
= ctx
->buffer
;
953 ctx
->prev_descriptor
= ctx
->buffer
;
954 ctx
->tail_descriptor
= ctx
->buffer
;
955 ctx
->tail_descriptor_last
= ctx
->buffer
;
957 /* We put a dummy descriptor in the buffer that has a NULL
958 * branch address and looks like it's been sent. That way we
959 * have a descriptor to append DMA programs to. Also, the
960 * ring buffer invariant is that it always has at least one
961 * element so that head == tail means buffer full. */
963 memset(ctx
->head_descriptor
, 0, sizeof *ctx
->head_descriptor
);
964 ctx
->head_descriptor
->control
=
965 cpu_to_le16(descriptor_output_last
);
966 ctx
->head_descriptor
->transfer_status
= cpu_to_le16(0x8011);
967 ctx
->head_descriptor
++;
972 static int ohci_send_iso(struct fw_iso_context
*base
, s32 cycle
)
974 struct iso_context
*ctx
= (struct iso_context
*)base
;
975 struct fw_ohci
*ohci
= fw_ohci(ctx
->base
.card
);
979 index
= ctx
- ohci
->it_context_list
;
981 cycle_match
= CONTEXT_CYCLE_MATCH_ENABLE
|
982 (cycle
& 0x7fff) << 16;
984 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
985 reg_write(ohci
, OHCI1394_IsoXmitCommandPtr(index
),
986 le32_to_cpu(ctx
->tail_descriptor_last
->branch_address
));
987 reg_write(ohci
, OHCI1394_IsoXmitContextControlClear(index
), ~0);
988 reg_write(ohci
, OHCI1394_IsoXmitContextControlSet(index
),
989 CONTEXT_RUN
| cycle_match
);
995 static void ohci_free_iso_context(struct fw_iso_context
*base
)
997 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
998 struct iso_context
*ctx
= (struct iso_context
*)base
;
1002 flush_iso_context(ctx
);
1004 spin_lock_irqsave(&ohci
->lock
, flags
);
1006 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1007 index
= ctx
- ohci
->it_context_list
;
1008 reg_write(ohci
, OHCI1394_IsoXmitContextControlClear(index
), ~0);
1009 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
1010 ohci
->it_context_mask
|= 1 << index
;
1012 index
= ctx
- ohci
->ir_context_list
;
1013 reg_write(ohci
, OHCI1394_IsoRcvContextControlClear(index
), ~0);
1014 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
1015 ohci
->ir_context_mask
|= 1 << index
;
1019 dma_unmap_single(ohci
->card
.device
, ctx
->buffer_bus
,
1020 ISO_BUFFER_SIZE
, DMA_TO_DEVICE
);
1022 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1026 ohci_queue_iso(struct fw_iso_context
*base
,
1027 struct fw_iso_packet
*packet
, void *payload
)
1029 struct iso_context
*ctx
= (struct iso_context
*)base
;
1030 struct fw_ohci
*ohci
= fw_ohci(ctx
->base
.card
);
1031 struct descriptor
*d
, *end
, *last
, *tail
, *pd
;
1032 struct fw_iso_packet
*p
;
1035 u32 z
, header_z
, payload_z
, irq
;
1036 u32 payload_index
, payload_end_index
, next_page_index
;
1037 int index
, page
, end_page
, i
, length
, offset
;
1039 /* FIXME: Cycle lost behavior should be configurable: lose
1040 * packet, retransmit or terminate.. */
1043 payload_index
= payload
- ctx
->base
.buffer
;
1044 d
= ctx
->head_descriptor
;
1045 tail
= ctx
->tail_descriptor
;
1046 end
= ctx
->buffer
+ ISO_BUFFER_SIZE
/ sizeof(struct descriptor
);
1052 if (p
->header_length
> 0)
1055 /* Determine the first page the payload isn't contained in. */
1056 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
1057 if (p
->payload_length
> 0)
1058 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
1064 /* Get header size in number of descriptors. */
1065 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof *d
);
1067 if (d
+ z
+ header_z
<= tail
) {
1069 } else if (d
> tail
&& d
+ z
+ header_z
<= end
) {
1071 } else if (d
> tail
&& ctx
->buffer
+ z
+ header_z
<= tail
) {
1076 /* No space in buffer */
1080 memset(d
, 0, (z
+ header_z
) * sizeof *d
);
1081 d_bus
= ctx
->buffer_bus
+ (d
- ctx
->buffer
) * sizeof *d
;
1084 d
[0].control
= cpu_to_le16(descriptor_key_immediate
);
1085 d
[0].req_count
= cpu_to_le16(8);
1087 header
= (__le32
*) &d
[1];
1088 header
[0] = cpu_to_le32(it_header_sy(p
->sy
) |
1089 it_header_tag(p
->tag
) |
1090 it_header_tcode(TCODE_STREAM_DATA
) |
1091 it_header_channel(ctx
->base
.channel
) |
1092 it_header_speed(ctx
->base
.speed
));
1094 cpu_to_le32(it_header_data_length(p
->header_length
+
1095 p
->payload_length
));
1098 if (p
->header_length
> 0) {
1099 d
[2].req_count
= cpu_to_le16(p
->header_length
);
1100 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof *d
);
1101 memcpy(&d
[z
], p
->header
, p
->header_length
);
1104 pd
= d
+ z
- payload_z
;
1105 payload_end_index
= payload_index
+ p
->payload_length
;
1106 for (i
= 0; i
< payload_z
; i
++) {
1107 page
= payload_index
>> PAGE_SHIFT
;
1108 offset
= payload_index
& ~PAGE_MASK
;
1109 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
1111 min(next_page_index
, payload_end_index
) - payload_index
;
1112 pd
[i
].req_count
= cpu_to_le16(length
);
1113 pd
[i
].data_address
= cpu_to_le32(ctx
->base
.pages
[page
] + offset
);
1115 payload_index
+= length
;
1124 irq
= descriptor_irq_always
;
1126 irq
= descriptor_no_irq
;
1128 last
->control
= cpu_to_le16(descriptor_output_last
|
1130 descriptor_branch_always
|
1133 dma_sync_single_for_device(ohci
->card
.device
, ctx
->buffer_bus
,
1134 ISO_BUFFER_SIZE
, DMA_TO_DEVICE
);
1136 ctx
->head_descriptor
= d
+ z
+ header_z
;
1137 ctx
->prev_descriptor
->branch_address
= cpu_to_le32(d_bus
| z
);
1138 ctx
->prev_descriptor
= last
;
1140 index
= ctx
- ohci
->it_context_list
;
1141 reg_write(ohci
, OHCI1394_IsoXmitContextControlSet(index
), CONTEXT_WAKE
);
1147 static struct fw_card_driver ohci_driver
= {
1148 .name
= ohci_driver_name
,
1149 .enable
= ohci_enable
,
1150 .update_phy_reg
= ohci_update_phy_reg
,
1151 .set_config_rom
= ohci_set_config_rom
,
1152 .send_request
= ohci_send_request
,
1153 .send_response
= ohci_send_response
,
1154 .enable_phys_dma
= ohci_enable_phys_dma
,
1156 .allocate_iso_context
= ohci_allocate_iso_context
,
1157 .free_iso_context
= ohci_free_iso_context
,
1158 .queue_iso
= ohci_queue_iso
,
1159 .send_iso
= ohci_send_iso
1162 static int software_reset(struct fw_ohci
*ohci
)
1166 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1168 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1169 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1170 OHCI1394_HCControl_softReset
) == 0)
1178 /* ---------- pci subsystem interface ---------- */
1188 static int cleanup(struct fw_ohci
*ohci
, int stage
, int code
)
1190 struct pci_dev
*dev
= to_pci_dev(ohci
->card
.device
);
1193 case CLEANUP_SELF_ID
:
1194 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
1195 ohci
->self_id_cpu
, ohci
->self_id_bus
);
1196 case CLEANUP_REGISTERS
:
1197 kfree(ohci
->it_context_list
);
1198 kfree(ohci
->ir_context_list
);
1199 pci_iounmap(dev
, ohci
->registers
);
1201 pci_release_region(dev
, 0);
1202 case CLEANUP_DISABLE
:
1203 pci_disable_device(dev
);
1204 case CLEANUP_PUT_CARD
:
1205 fw_card_put(&ohci
->card
);
1211 static int __devinit
1212 pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
1214 struct fw_ohci
*ohci
;
1215 u32 bus_options
, max_receive
, link_speed
;
1220 ohci
= kzalloc(sizeof *ohci
, GFP_KERNEL
);
1222 fw_error("Could not malloc fw_ohci data.\n");
1226 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
1228 if (pci_enable_device(dev
)) {
1229 fw_error("Failed to enable OHCI hardware.\n");
1230 return cleanup(ohci
, CLEANUP_PUT_CARD
, -ENODEV
);
1233 pci_set_master(dev
);
1234 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
1235 pci_set_drvdata(dev
, ohci
);
1237 spin_lock_init(&ohci
->lock
);
1239 tasklet_init(&ohci
->bus_reset_tasklet
,
1240 bus_reset_tasklet
, (unsigned long)ohci
);
1242 if (pci_request_region(dev
, 0, ohci_driver_name
)) {
1243 fw_error("MMIO resource unavailable\n");
1244 return cleanup(ohci
, CLEANUP_DISABLE
, -EBUSY
);
1247 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
1248 if (ohci
->registers
== NULL
) {
1249 fw_error("Failed to remap registers\n");
1250 return cleanup(ohci
, CLEANUP_IOMEM
, -ENXIO
);
1253 if (software_reset(ohci
)) {
1254 fw_error("Failed to reset ohci card.\n");
1255 return cleanup(ohci
, CLEANUP_REGISTERS
, -EBUSY
);
1258 /* Now enable LPS, which we need in order to start accessing
1259 * most of the registers. In fact, on some cards (ALI M5251),
1260 * accessing registers in the SClk domain without LPS enabled
1261 * will lock up the machine. Wait 50msec to make sure we have
1262 * full link enabled. */
1263 reg_write(ohci
, OHCI1394_HCControlSet
,
1264 OHCI1394_HCControl_LPS
|
1265 OHCI1394_HCControl_postedWriteEnable
);
1269 reg_write(ohci
, OHCI1394_HCControlClear
,
1270 OHCI1394_HCControl_noByteSwapData
);
1272 reg_write(ohci
, OHCI1394_LinkControlSet
,
1273 OHCI1394_LinkControl_rcvSelfID
|
1274 OHCI1394_LinkControl_cycleTimerEnable
|
1275 OHCI1394_LinkControl_cycleMaster
);
1277 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
1278 OHCI1394_AsReqRcvContextControlSet
);
1280 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
1281 OHCI1394_AsRspRcvContextControlSet
);
1283 at_context_init(&ohci
->at_request_ctx
, ohci
,
1284 OHCI1394_AsReqTrContextControlSet
);
1286 at_context_init(&ohci
->at_response_ctx
, ohci
,
1287 OHCI1394_AsRspTrContextControlSet
);
1289 reg_write(ohci
, OHCI1394_ATRetries
,
1290 OHCI1394_MAX_AT_REQ_RETRIES
|
1291 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1292 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1294 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
1295 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
1296 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
1297 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
1298 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
1300 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
1301 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
1302 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
1303 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
1304 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
1306 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
1307 fw_error("Out of memory for it/ir contexts.\n");
1308 return cleanup(ohci
, CLEANUP_REGISTERS
, -ENOMEM
);
1311 /* self-id dma buffer allocation */
1312 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
1316 if (ohci
->self_id_cpu
== NULL
) {
1317 fw_error("Out of memory for self ID buffer.\n");
1318 return cleanup(ohci
, CLEANUP_REGISTERS
, -ENOMEM
);
1321 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1322 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1323 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1324 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1325 reg_write(ohci
, OHCI1394_IntMaskSet
,
1326 OHCI1394_selfIDComplete
|
1327 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1328 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1329 OHCI1394_isochRx
| OHCI1394_isochTx
|
1330 OHCI1394_masterIntEnable
);
1332 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
1333 max_receive
= (bus_options
>> 12) & 0xf;
1334 link_speed
= bus_options
& 0x7;
1335 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
1336 reg_read(ohci
, OHCI1394_GUIDLo
);
1338 error_code
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
1340 return cleanup(ohci
, CLEANUP_SELF_ID
, error_code
);
1342 fw_notify("Added fw-ohci device %s.\n", dev
->dev
.bus_id
);
1347 static void pci_remove(struct pci_dev
*dev
)
1349 struct fw_ohci
*ohci
;
1351 ohci
= pci_get_drvdata(dev
);
1352 reg_write(ohci
, OHCI1394_IntMaskClear
, OHCI1394_masterIntEnable
);
1353 fw_core_remove_card(&ohci
->card
);
1355 /* FIXME: Fail all pending packets here, now that the upper
1356 * layers can't queue any more. */
1358 software_reset(ohci
);
1359 free_irq(dev
->irq
, ohci
);
1360 cleanup(ohci
, CLEANUP_SELF_ID
, 0);
1362 fw_notify("Removed fw-ohci device.\n");
1365 static struct pci_device_id pci_table
[] = {
1366 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
1370 MODULE_DEVICE_TABLE(pci
, pci_table
);
1372 static struct pci_driver fw_ohci_pci_driver
= {
1373 .name
= ohci_driver_name
,
1374 .id_table
= pci_table
,
1376 .remove
= pci_remove
,
1379 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1380 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1381 MODULE_LICENSE("GPL");
1383 static int __init
fw_ohci_init(void)
1385 return pci_register_driver(&fw_ohci_pci_driver
);
1388 static void __exit
fw_ohci_cleanup(void)
1390 pci_unregister_driver(&fw_ohci_pci_driver
);
1393 module_init(fw_ohci_init
);
1394 module_exit(fw_ohci_cleanup
);