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Merge branches 'acpi-general' and 'acpi-video'
[mirror_ubuntu-artful-kernel.git] / drivers / firewire / ohci.c
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45 #include <linux/workqueue.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/page.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
58 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
59 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
60
61 #define DESCRIPTOR_OUTPUT_MORE 0
62 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
63 #define DESCRIPTOR_INPUT_MORE (2 << 12)
64 #define DESCRIPTOR_INPUT_LAST (3 << 12)
65 #define DESCRIPTOR_STATUS (1 << 11)
66 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
67 #define DESCRIPTOR_PING (1 << 7)
68 #define DESCRIPTOR_YY (1 << 6)
69 #define DESCRIPTOR_NO_IRQ (0 << 4)
70 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
71 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
72 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
73 #define DESCRIPTOR_WAIT (3 << 0)
74
75 #define DESCRIPTOR_CMD (0xf << 12)
76
77 struct descriptor {
78 __le16 req_count;
79 __le16 control;
80 __le32 data_address;
81 __le32 branch_address;
82 __le16 res_count;
83 __le16 transfer_status;
84 } __attribute__((aligned(16)));
85
86 #define CONTROL_SET(regs) (regs)
87 #define CONTROL_CLEAR(regs) ((regs) + 4)
88 #define COMMAND_PTR(regs) ((regs) + 12)
89 #define CONTEXT_MATCH(regs) ((regs) + 16)
90
91 #define AR_BUFFER_SIZE (32*1024)
92 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
93 /* we need at least two pages for proper list management */
94 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
95
96 #define MAX_ASYNC_PAYLOAD 4096
97 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
98 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
99
100 struct ar_context {
101 struct fw_ohci *ohci;
102 struct page *pages[AR_BUFFERS];
103 void *buffer;
104 struct descriptor *descriptors;
105 dma_addr_t descriptors_bus;
106 void *pointer;
107 unsigned int last_buffer_index;
108 u32 regs;
109 struct tasklet_struct tasklet;
110 };
111
112 struct context;
113
114 typedef int (*descriptor_callback_t)(struct context *ctx,
115 struct descriptor *d,
116 struct descriptor *last);
117
118 /*
119 * A buffer that contains a block of DMA-able coherent memory used for
120 * storing a portion of a DMA descriptor program.
121 */
122 struct descriptor_buffer {
123 struct list_head list;
124 dma_addr_t buffer_bus;
125 size_t buffer_size;
126 size_t used;
127 struct descriptor buffer[0];
128 };
129
130 struct context {
131 struct fw_ohci *ohci;
132 u32 regs;
133 int total_allocation;
134 u32 current_bus;
135 bool running;
136 bool flushing;
137
138 /*
139 * List of page-sized buffers for storing DMA descriptors.
140 * Head of list contains buffers in use and tail of list contains
141 * free buffers.
142 */
143 struct list_head buffer_list;
144
145 /*
146 * Pointer to a buffer inside buffer_list that contains the tail
147 * end of the current DMA program.
148 */
149 struct descriptor_buffer *buffer_tail;
150
151 /*
152 * The descriptor containing the branch address of the first
153 * descriptor that has not yet been filled by the device.
154 */
155 struct descriptor *last;
156
157 /*
158 * The last descriptor block in the DMA program. It contains the branch
159 * address that must be updated upon appending a new descriptor.
160 */
161 struct descriptor *prev;
162 int prev_z;
163
164 descriptor_callback_t callback;
165
166 struct tasklet_struct tasklet;
167 };
168
169 #define IT_HEADER_SY(v) ((v) << 0)
170 #define IT_HEADER_TCODE(v) ((v) << 4)
171 #define IT_HEADER_CHANNEL(v) ((v) << 8)
172 #define IT_HEADER_TAG(v) ((v) << 14)
173 #define IT_HEADER_SPEED(v) ((v) << 16)
174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
175
176 struct iso_context {
177 struct fw_iso_context base;
178 struct context context;
179 void *header;
180 size_t header_length;
181 unsigned long flushing_completions;
182 u32 mc_buffer_bus;
183 u16 mc_completed;
184 u16 last_timestamp;
185 u8 sync;
186 u8 tags;
187 };
188
189 #define CONFIG_ROM_SIZE 1024
190
191 struct fw_ohci {
192 struct fw_card card;
193
194 __iomem char *registers;
195 int node_id;
196 int generation;
197 int request_generation; /* for timestamping incoming requests */
198 unsigned quirks;
199 unsigned int pri_req_max;
200 u32 bus_time;
201 bool bus_time_running;
202 bool is_root;
203 bool csr_state_setclear_abdicate;
204 int n_ir;
205 int n_it;
206 /*
207 * Spinlock for accessing fw_ohci data. Never call out of
208 * this driver with this lock held.
209 */
210 spinlock_t lock;
211
212 struct mutex phy_reg_mutex;
213
214 void *misc_buffer;
215 dma_addr_t misc_buffer_bus;
216
217 struct ar_context ar_request_ctx;
218 struct ar_context ar_response_ctx;
219 struct context at_request_ctx;
220 struct context at_response_ctx;
221
222 u32 it_context_support;
223 u32 it_context_mask; /* unoccupied IT contexts */
224 struct iso_context *it_context_list;
225 u64 ir_context_channels; /* unoccupied channels */
226 u32 ir_context_support;
227 u32 ir_context_mask; /* unoccupied IR contexts */
228 struct iso_context *ir_context_list;
229 u64 mc_channels; /* channels in use by the multichannel IR context */
230 bool mc_allocated;
231
232 __be32 *config_rom;
233 dma_addr_t config_rom_bus;
234 __be32 *next_config_rom;
235 dma_addr_t next_config_rom_bus;
236 __be32 next_header;
237
238 __le32 *self_id;
239 dma_addr_t self_id_bus;
240 struct work_struct bus_reset_work;
241
242 u32 self_id_buffer[512];
243 };
244
245 static struct workqueue_struct *selfid_workqueue;
246
247 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
248 {
249 return container_of(card, struct fw_ohci, card);
250 }
251
252 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
253 #define IR_CONTEXT_BUFFER_FILL 0x80000000
254 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
255 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
256 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
257 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
258
259 #define CONTEXT_RUN 0x8000
260 #define CONTEXT_WAKE 0x1000
261 #define CONTEXT_DEAD 0x0800
262 #define CONTEXT_ACTIVE 0x0400
263
264 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
265 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
266 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
267
268 #define OHCI1394_REGISTER_SIZE 0x800
269 #define OHCI1394_PCI_HCI_Control 0x40
270 #define SELF_ID_BUF_SIZE 0x800
271 #define OHCI_TCODE_PHY_PACKET 0x0e
272 #define OHCI_VERSION_1_1 0x010010
273
274 static char ohci_driver_name[] = KBUILD_MODNAME;
275
276 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
277 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
278 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
279 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
280 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
281 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
282 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
283 #define PCI_DEVICE_ID_VIA_VT630X 0x3044
284 #define PCI_REV_ID_VIA_VT6306 0x46
285 #define PCI_DEVICE_ID_VIA_VT6315 0x3403
286
287 #define QUIRK_CYCLE_TIMER 0x1
288 #define QUIRK_RESET_PACKET 0x2
289 #define QUIRK_BE_HEADERS 0x4
290 #define QUIRK_NO_1394A 0x8
291 #define QUIRK_NO_MSI 0x10
292 #define QUIRK_TI_SLLZ059 0x20
293 #define QUIRK_IR_WAKE 0x40
294
295 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
296 static const struct {
297 unsigned short vendor, device, revision, flags;
298 } ohci_quirks[] = {
299 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_CYCLE_TIMER},
301
302 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
303 QUIRK_BE_HEADERS},
304
305 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
306 QUIRK_NO_MSI},
307
308 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
309 QUIRK_RESET_PACKET},
310
311 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
312 QUIRK_NO_MSI},
313
314 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
315 QUIRK_CYCLE_TIMER},
316
317 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
318 QUIRK_NO_MSI},
319
320 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
321 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
322
323 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
324 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
325
326 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
327 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
328
329 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
330 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
331
332 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
333 QUIRK_RESET_PACKET},
334
335 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
336 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
337
338 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
339 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
340
341 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
342 0},
343
344 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
345 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
346 };
347
348 /* This overrides anything that was found in ohci_quirks[]. */
349 static int param_quirks;
350 module_param_named(quirks, param_quirks, int, 0644);
351 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
352 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
353 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
354 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
355 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
356 ", disable MSI = " __stringify(QUIRK_NO_MSI)
357 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
358 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
359 ")");
360
361 #define OHCI_PARAM_DEBUG_AT_AR 1
362 #define OHCI_PARAM_DEBUG_SELFIDS 2
363 #define OHCI_PARAM_DEBUG_IRQS 4
364 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
365
366 static int param_debug;
367 module_param_named(debug, param_debug, int, 0644);
368 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
369 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
370 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
371 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
372 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
373 ", or a combination, or all = -1)");
374
375 static bool param_remote_dma;
376 module_param_named(remote_dma, param_remote_dma, bool, 0444);
377 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
378
379 static void log_irqs(struct fw_ohci *ohci, u32 evt)
380 {
381 if (likely(!(param_debug &
382 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
383 return;
384
385 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
386 !(evt & OHCI1394_busReset))
387 return;
388
389 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
390 evt & OHCI1394_selfIDComplete ? " selfID" : "",
391 evt & OHCI1394_RQPkt ? " AR_req" : "",
392 evt & OHCI1394_RSPkt ? " AR_resp" : "",
393 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
394 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
395 evt & OHCI1394_isochRx ? " IR" : "",
396 evt & OHCI1394_isochTx ? " IT" : "",
397 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
398 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
399 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
400 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
401 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
402 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
403 evt & OHCI1394_busReset ? " busReset" : "",
404 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
405 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
406 OHCI1394_respTxComplete | OHCI1394_isochRx |
407 OHCI1394_isochTx | OHCI1394_postedWriteErr |
408 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
409 OHCI1394_cycleInconsistent |
410 OHCI1394_regAccessFail | OHCI1394_busReset)
411 ? " ?" : "");
412 }
413
414 static const char *speed[] = {
415 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
416 };
417 static const char *power[] = {
418 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
419 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
420 };
421 static const char port[] = { '.', '-', 'p', 'c', };
422
423 static char _p(u32 *s, int shift)
424 {
425 return port[*s >> shift & 3];
426 }
427
428 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
429 {
430 u32 *s;
431
432 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
433 return;
434
435 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
436 self_id_count, generation, ohci->node_id);
437
438 for (s = ohci->self_id_buffer; self_id_count--; ++s)
439 if ((*s & 1 << 23) == 0)
440 ohci_notice(ohci,
441 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
442 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
443 speed[*s >> 14 & 3], *s >> 16 & 63,
444 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
445 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
446 else
447 ohci_notice(ohci,
448 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
449 *s, *s >> 24 & 63,
450 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
451 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
452 }
453
454 static const char *evts[] = {
455 [0x00] = "evt_no_status", [0x01] = "-reserved-",
456 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
457 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
458 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
459 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
460 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
461 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
462 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
463 [0x10] = "-reserved-", [0x11] = "ack_complete",
464 [0x12] = "ack_pending ", [0x13] = "-reserved-",
465 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
466 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
467 [0x18] = "-reserved-", [0x19] = "-reserved-",
468 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
469 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
470 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
471 [0x20] = "pending/cancelled",
472 };
473 static const char *tcodes[] = {
474 [0x0] = "QW req", [0x1] = "BW req",
475 [0x2] = "W resp", [0x3] = "-reserved-",
476 [0x4] = "QR req", [0x5] = "BR req",
477 [0x6] = "QR resp", [0x7] = "BR resp",
478 [0x8] = "cycle start", [0x9] = "Lk req",
479 [0xa] = "async stream packet", [0xb] = "Lk resp",
480 [0xc] = "-reserved-", [0xd] = "-reserved-",
481 [0xe] = "link internal", [0xf] = "-reserved-",
482 };
483
484 static void log_ar_at_event(struct fw_ohci *ohci,
485 char dir, int speed, u32 *header, int evt)
486 {
487 int tcode = header[0] >> 4 & 0xf;
488 char specific[12];
489
490 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
491 return;
492
493 if (unlikely(evt >= ARRAY_SIZE(evts)))
494 evt = 0x1f;
495
496 if (evt == OHCI1394_evt_bus_reset) {
497 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
498 dir, (header[2] >> 16) & 0xff);
499 return;
500 }
501
502 switch (tcode) {
503 case 0x0: case 0x6: case 0x8:
504 snprintf(specific, sizeof(specific), " = %08x",
505 be32_to_cpu((__force __be32)header[3]));
506 break;
507 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
508 snprintf(specific, sizeof(specific), " %x,%x",
509 header[3] >> 16, header[3] & 0xffff);
510 break;
511 default:
512 specific[0] = '\0';
513 }
514
515 switch (tcode) {
516 case 0xa:
517 ohci_notice(ohci, "A%c %s, %s\n",
518 dir, evts[evt], tcodes[tcode]);
519 break;
520 case 0xe:
521 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
522 dir, evts[evt], header[1], header[2]);
523 break;
524 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
525 ohci_notice(ohci,
526 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
527 dir, speed, header[0] >> 10 & 0x3f,
528 header[1] >> 16, header[0] >> 16, evts[evt],
529 tcodes[tcode], header[1] & 0xffff, header[2], specific);
530 break;
531 default:
532 ohci_notice(ohci,
533 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
534 dir, speed, header[0] >> 10 & 0x3f,
535 header[1] >> 16, header[0] >> 16, evts[evt],
536 tcodes[tcode], specific);
537 }
538 }
539
540 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
541 {
542 writel(data, ohci->registers + offset);
543 }
544
545 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
546 {
547 return readl(ohci->registers + offset);
548 }
549
550 static inline void flush_writes(const struct fw_ohci *ohci)
551 {
552 /* Do a dummy read to flush writes. */
553 reg_read(ohci, OHCI1394_Version);
554 }
555
556 /*
557 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
558 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
559 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
560 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
561 */
562 static int read_phy_reg(struct fw_ohci *ohci, int addr)
563 {
564 u32 val;
565 int i;
566
567 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
568 for (i = 0; i < 3 + 100; i++) {
569 val = reg_read(ohci, OHCI1394_PhyControl);
570 if (!~val)
571 return -ENODEV; /* Card was ejected. */
572
573 if (val & OHCI1394_PhyControl_ReadDone)
574 return OHCI1394_PhyControl_ReadData(val);
575
576 /*
577 * Try a few times without waiting. Sleeping is necessary
578 * only when the link/PHY interface is busy.
579 */
580 if (i >= 3)
581 msleep(1);
582 }
583 ohci_err(ohci, "failed to read phy reg %d\n", addr);
584 dump_stack();
585
586 return -EBUSY;
587 }
588
589 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
590 {
591 int i;
592
593 reg_write(ohci, OHCI1394_PhyControl,
594 OHCI1394_PhyControl_Write(addr, val));
595 for (i = 0; i < 3 + 100; i++) {
596 val = reg_read(ohci, OHCI1394_PhyControl);
597 if (!~val)
598 return -ENODEV; /* Card was ejected. */
599
600 if (!(val & OHCI1394_PhyControl_WritePending))
601 return 0;
602
603 if (i >= 3)
604 msleep(1);
605 }
606 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
607 dump_stack();
608
609 return -EBUSY;
610 }
611
612 static int update_phy_reg(struct fw_ohci *ohci, int addr,
613 int clear_bits, int set_bits)
614 {
615 int ret = read_phy_reg(ohci, addr);
616 if (ret < 0)
617 return ret;
618
619 /*
620 * The interrupt status bits are cleared by writing a one bit.
621 * Avoid clearing them unless explicitly requested in set_bits.
622 */
623 if (addr == 5)
624 clear_bits |= PHY_INT_STATUS_BITS;
625
626 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
627 }
628
629 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
630 {
631 int ret;
632
633 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
634 if (ret < 0)
635 return ret;
636
637 return read_phy_reg(ohci, addr);
638 }
639
640 static int ohci_read_phy_reg(struct fw_card *card, int addr)
641 {
642 struct fw_ohci *ohci = fw_ohci(card);
643 int ret;
644
645 mutex_lock(&ohci->phy_reg_mutex);
646 ret = read_phy_reg(ohci, addr);
647 mutex_unlock(&ohci->phy_reg_mutex);
648
649 return ret;
650 }
651
652 static int ohci_update_phy_reg(struct fw_card *card, int addr,
653 int clear_bits, int set_bits)
654 {
655 struct fw_ohci *ohci = fw_ohci(card);
656 int ret;
657
658 mutex_lock(&ohci->phy_reg_mutex);
659 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
660 mutex_unlock(&ohci->phy_reg_mutex);
661
662 return ret;
663 }
664
665 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
666 {
667 return page_private(ctx->pages[i]);
668 }
669
670 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
671 {
672 struct descriptor *d;
673
674 d = &ctx->descriptors[index];
675 d->branch_address &= cpu_to_le32(~0xf);
676 d->res_count = cpu_to_le16(PAGE_SIZE);
677 d->transfer_status = 0;
678
679 wmb(); /* finish init of new descriptors before branch_address update */
680 d = &ctx->descriptors[ctx->last_buffer_index];
681 d->branch_address |= cpu_to_le32(1);
682
683 ctx->last_buffer_index = index;
684
685 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
686 }
687
688 static void ar_context_release(struct ar_context *ctx)
689 {
690 unsigned int i;
691
692 if (ctx->buffer)
693 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
694
695 for (i = 0; i < AR_BUFFERS; i++)
696 if (ctx->pages[i]) {
697 dma_unmap_page(ctx->ohci->card.device,
698 ar_buffer_bus(ctx, i),
699 PAGE_SIZE, DMA_FROM_DEVICE);
700 __free_page(ctx->pages[i]);
701 }
702 }
703
704 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
705 {
706 struct fw_ohci *ohci = ctx->ohci;
707
708 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
709 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
710 flush_writes(ohci);
711
712 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
713 }
714 /* FIXME: restart? */
715 }
716
717 static inline unsigned int ar_next_buffer_index(unsigned int index)
718 {
719 return (index + 1) % AR_BUFFERS;
720 }
721
722 static inline unsigned int ar_prev_buffer_index(unsigned int index)
723 {
724 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
725 }
726
727 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
728 {
729 return ar_next_buffer_index(ctx->last_buffer_index);
730 }
731
732 /*
733 * We search for the buffer that contains the last AR packet DMA data written
734 * by the controller.
735 */
736 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
737 unsigned int *buffer_offset)
738 {
739 unsigned int i, next_i, last = ctx->last_buffer_index;
740 __le16 res_count, next_res_count;
741
742 i = ar_first_buffer_index(ctx);
743 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
744
745 /* A buffer that is not yet completely filled must be the last one. */
746 while (i != last && res_count == 0) {
747
748 /* Peek at the next descriptor. */
749 next_i = ar_next_buffer_index(i);
750 rmb(); /* read descriptors in order */
751 next_res_count = ACCESS_ONCE(
752 ctx->descriptors[next_i].res_count);
753 /*
754 * If the next descriptor is still empty, we must stop at this
755 * descriptor.
756 */
757 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
758 /*
759 * The exception is when the DMA data for one packet is
760 * split over three buffers; in this case, the middle
761 * buffer's descriptor might be never updated by the
762 * controller and look still empty, and we have to peek
763 * at the third one.
764 */
765 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
766 next_i = ar_next_buffer_index(next_i);
767 rmb();
768 next_res_count = ACCESS_ONCE(
769 ctx->descriptors[next_i].res_count);
770 if (next_res_count != cpu_to_le16(PAGE_SIZE))
771 goto next_buffer_is_active;
772 }
773
774 break;
775 }
776
777 next_buffer_is_active:
778 i = next_i;
779 res_count = next_res_count;
780 }
781
782 rmb(); /* read res_count before the DMA data */
783
784 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
785 if (*buffer_offset > PAGE_SIZE) {
786 *buffer_offset = 0;
787 ar_context_abort(ctx, "corrupted descriptor");
788 }
789
790 return i;
791 }
792
793 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
794 unsigned int end_buffer_index,
795 unsigned int end_buffer_offset)
796 {
797 unsigned int i;
798
799 i = ar_first_buffer_index(ctx);
800 while (i != end_buffer_index) {
801 dma_sync_single_for_cpu(ctx->ohci->card.device,
802 ar_buffer_bus(ctx, i),
803 PAGE_SIZE, DMA_FROM_DEVICE);
804 i = ar_next_buffer_index(i);
805 }
806 if (end_buffer_offset > 0)
807 dma_sync_single_for_cpu(ctx->ohci->card.device,
808 ar_buffer_bus(ctx, i),
809 end_buffer_offset, DMA_FROM_DEVICE);
810 }
811
812 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
813 #define cond_le32_to_cpu(v) \
814 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
815 #else
816 #define cond_le32_to_cpu(v) le32_to_cpu(v)
817 #endif
818
819 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
820 {
821 struct fw_ohci *ohci = ctx->ohci;
822 struct fw_packet p;
823 u32 status, length, tcode;
824 int evt;
825
826 p.header[0] = cond_le32_to_cpu(buffer[0]);
827 p.header[1] = cond_le32_to_cpu(buffer[1]);
828 p.header[2] = cond_le32_to_cpu(buffer[2]);
829
830 tcode = (p.header[0] >> 4) & 0x0f;
831 switch (tcode) {
832 case TCODE_WRITE_QUADLET_REQUEST:
833 case TCODE_READ_QUADLET_RESPONSE:
834 p.header[3] = (__force __u32) buffer[3];
835 p.header_length = 16;
836 p.payload_length = 0;
837 break;
838
839 case TCODE_READ_BLOCK_REQUEST :
840 p.header[3] = cond_le32_to_cpu(buffer[3]);
841 p.header_length = 16;
842 p.payload_length = 0;
843 break;
844
845 case TCODE_WRITE_BLOCK_REQUEST:
846 case TCODE_READ_BLOCK_RESPONSE:
847 case TCODE_LOCK_REQUEST:
848 case TCODE_LOCK_RESPONSE:
849 p.header[3] = cond_le32_to_cpu(buffer[3]);
850 p.header_length = 16;
851 p.payload_length = p.header[3] >> 16;
852 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
853 ar_context_abort(ctx, "invalid packet length");
854 return NULL;
855 }
856 break;
857
858 case TCODE_WRITE_RESPONSE:
859 case TCODE_READ_QUADLET_REQUEST:
860 case OHCI_TCODE_PHY_PACKET:
861 p.header_length = 12;
862 p.payload_length = 0;
863 break;
864
865 default:
866 ar_context_abort(ctx, "invalid tcode");
867 return NULL;
868 }
869
870 p.payload = (void *) buffer + p.header_length;
871
872 /* FIXME: What to do about evt_* errors? */
873 length = (p.header_length + p.payload_length + 3) / 4;
874 status = cond_le32_to_cpu(buffer[length]);
875 evt = (status >> 16) & 0x1f;
876
877 p.ack = evt - 16;
878 p.speed = (status >> 21) & 0x7;
879 p.timestamp = status & 0xffff;
880 p.generation = ohci->request_generation;
881
882 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
883
884 /*
885 * Several controllers, notably from NEC and VIA, forget to
886 * write ack_complete status at PHY packet reception.
887 */
888 if (evt == OHCI1394_evt_no_status &&
889 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
890 p.ack = ACK_COMPLETE;
891
892 /*
893 * The OHCI bus reset handler synthesizes a PHY packet with
894 * the new generation number when a bus reset happens (see
895 * section 8.4.2.3). This helps us determine when a request
896 * was received and make sure we send the response in the same
897 * generation. We only need this for requests; for responses
898 * we use the unique tlabel for finding the matching
899 * request.
900 *
901 * Alas some chips sometimes emit bus reset packets with a
902 * wrong generation. We set the correct generation for these
903 * at a slightly incorrect time (in bus_reset_work).
904 */
905 if (evt == OHCI1394_evt_bus_reset) {
906 if (!(ohci->quirks & QUIRK_RESET_PACKET))
907 ohci->request_generation = (p.header[2] >> 16) & 0xff;
908 } else if (ctx == &ohci->ar_request_ctx) {
909 fw_core_handle_request(&ohci->card, &p);
910 } else {
911 fw_core_handle_response(&ohci->card, &p);
912 }
913
914 return buffer + length + 1;
915 }
916
917 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
918 {
919 void *next;
920
921 while (p < end) {
922 next = handle_ar_packet(ctx, p);
923 if (!next)
924 return p;
925 p = next;
926 }
927
928 return p;
929 }
930
931 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
932 {
933 unsigned int i;
934
935 i = ar_first_buffer_index(ctx);
936 while (i != end_buffer) {
937 dma_sync_single_for_device(ctx->ohci->card.device,
938 ar_buffer_bus(ctx, i),
939 PAGE_SIZE, DMA_FROM_DEVICE);
940 ar_context_link_page(ctx, i);
941 i = ar_next_buffer_index(i);
942 }
943 }
944
945 static void ar_context_tasklet(unsigned long data)
946 {
947 struct ar_context *ctx = (struct ar_context *)data;
948 unsigned int end_buffer_index, end_buffer_offset;
949 void *p, *end;
950
951 p = ctx->pointer;
952 if (!p)
953 return;
954
955 end_buffer_index = ar_search_last_active_buffer(ctx,
956 &end_buffer_offset);
957 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
958 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
959
960 if (end_buffer_index < ar_first_buffer_index(ctx)) {
961 /*
962 * The filled part of the overall buffer wraps around; handle
963 * all packets up to the buffer end here. If the last packet
964 * wraps around, its tail will be visible after the buffer end
965 * because the buffer start pages are mapped there again.
966 */
967 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
968 p = handle_ar_packets(ctx, p, buffer_end);
969 if (p < buffer_end)
970 goto error;
971 /* adjust p to point back into the actual buffer */
972 p -= AR_BUFFERS * PAGE_SIZE;
973 }
974
975 p = handle_ar_packets(ctx, p, end);
976 if (p != end) {
977 if (p > end)
978 ar_context_abort(ctx, "inconsistent descriptor");
979 goto error;
980 }
981
982 ctx->pointer = p;
983 ar_recycle_buffers(ctx, end_buffer_index);
984
985 return;
986
987 error:
988 ctx->pointer = NULL;
989 }
990
991 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
992 unsigned int descriptors_offset, u32 regs)
993 {
994 unsigned int i;
995 dma_addr_t dma_addr;
996 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
997 struct descriptor *d;
998
999 ctx->regs = regs;
1000 ctx->ohci = ohci;
1001 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
1002
1003 for (i = 0; i < AR_BUFFERS; i++) {
1004 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
1005 if (!ctx->pages[i])
1006 goto out_of_memory;
1007 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1008 0, PAGE_SIZE, DMA_FROM_DEVICE);
1009 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1010 __free_page(ctx->pages[i]);
1011 ctx->pages[i] = NULL;
1012 goto out_of_memory;
1013 }
1014 set_page_private(ctx->pages[i], dma_addr);
1015 }
1016
1017 for (i = 0; i < AR_BUFFERS; i++)
1018 pages[i] = ctx->pages[i];
1019 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1020 pages[AR_BUFFERS + i] = ctx->pages[i];
1021 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1022 -1, PAGE_KERNEL);
1023 if (!ctx->buffer)
1024 goto out_of_memory;
1025
1026 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1027 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1028
1029 for (i = 0; i < AR_BUFFERS; i++) {
1030 d = &ctx->descriptors[i];
1031 d->req_count = cpu_to_le16(PAGE_SIZE);
1032 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1033 DESCRIPTOR_STATUS |
1034 DESCRIPTOR_BRANCH_ALWAYS);
1035 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1036 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1037 ar_next_buffer_index(i) * sizeof(struct descriptor));
1038 }
1039
1040 return 0;
1041
1042 out_of_memory:
1043 ar_context_release(ctx);
1044
1045 return -ENOMEM;
1046 }
1047
1048 static void ar_context_run(struct ar_context *ctx)
1049 {
1050 unsigned int i;
1051
1052 for (i = 0; i < AR_BUFFERS; i++)
1053 ar_context_link_page(ctx, i);
1054
1055 ctx->pointer = ctx->buffer;
1056
1057 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1058 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1059 }
1060
1061 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1062 {
1063 __le16 branch;
1064
1065 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1066
1067 /* figure out which descriptor the branch address goes in */
1068 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1069 return d;
1070 else
1071 return d + z - 1;
1072 }
1073
1074 static void context_tasklet(unsigned long data)
1075 {
1076 struct context *ctx = (struct context *) data;
1077 struct descriptor *d, *last;
1078 u32 address;
1079 int z;
1080 struct descriptor_buffer *desc;
1081
1082 desc = list_entry(ctx->buffer_list.next,
1083 struct descriptor_buffer, list);
1084 last = ctx->last;
1085 while (last->branch_address != 0) {
1086 struct descriptor_buffer *old_desc = desc;
1087 address = le32_to_cpu(last->branch_address);
1088 z = address & 0xf;
1089 address &= ~0xf;
1090 ctx->current_bus = address;
1091
1092 /* If the branch address points to a buffer outside of the
1093 * current buffer, advance to the next buffer. */
1094 if (address < desc->buffer_bus ||
1095 address >= desc->buffer_bus + desc->used)
1096 desc = list_entry(desc->list.next,
1097 struct descriptor_buffer, list);
1098 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1099 last = find_branch_descriptor(d, z);
1100
1101 if (!ctx->callback(ctx, d, last))
1102 break;
1103
1104 if (old_desc != desc) {
1105 /* If we've advanced to the next buffer, move the
1106 * previous buffer to the free list. */
1107 unsigned long flags;
1108 old_desc->used = 0;
1109 spin_lock_irqsave(&ctx->ohci->lock, flags);
1110 list_move_tail(&old_desc->list, &ctx->buffer_list);
1111 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1112 }
1113 ctx->last = last;
1114 }
1115 }
1116
1117 /*
1118 * Allocate a new buffer and add it to the list of free buffers for this
1119 * context. Must be called with ohci->lock held.
1120 */
1121 static int context_add_buffer(struct context *ctx)
1122 {
1123 struct descriptor_buffer *desc;
1124 dma_addr_t uninitialized_var(bus_addr);
1125 int offset;
1126
1127 /*
1128 * 16MB of descriptors should be far more than enough for any DMA
1129 * program. This will catch run-away userspace or DoS attacks.
1130 */
1131 if (ctx->total_allocation >= 16*1024*1024)
1132 return -ENOMEM;
1133
1134 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1135 &bus_addr, GFP_ATOMIC);
1136 if (!desc)
1137 return -ENOMEM;
1138
1139 offset = (void *)&desc->buffer - (void *)desc;
1140 desc->buffer_size = PAGE_SIZE - offset;
1141 desc->buffer_bus = bus_addr + offset;
1142 desc->used = 0;
1143
1144 list_add_tail(&desc->list, &ctx->buffer_list);
1145 ctx->total_allocation += PAGE_SIZE;
1146
1147 return 0;
1148 }
1149
1150 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1151 u32 regs, descriptor_callback_t callback)
1152 {
1153 ctx->ohci = ohci;
1154 ctx->regs = regs;
1155 ctx->total_allocation = 0;
1156
1157 INIT_LIST_HEAD(&ctx->buffer_list);
1158 if (context_add_buffer(ctx) < 0)
1159 return -ENOMEM;
1160
1161 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1162 struct descriptor_buffer, list);
1163
1164 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1165 ctx->callback = callback;
1166
1167 /*
1168 * We put a dummy descriptor in the buffer that has a NULL
1169 * branch address and looks like it's been sent. That way we
1170 * have a descriptor to append DMA programs to.
1171 */
1172 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1173 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1174 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1175 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1176 ctx->last = ctx->buffer_tail->buffer;
1177 ctx->prev = ctx->buffer_tail->buffer;
1178 ctx->prev_z = 1;
1179
1180 return 0;
1181 }
1182
1183 static void context_release(struct context *ctx)
1184 {
1185 struct fw_card *card = &ctx->ohci->card;
1186 struct descriptor_buffer *desc, *tmp;
1187
1188 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1189 dma_free_coherent(card->device, PAGE_SIZE, desc,
1190 desc->buffer_bus -
1191 ((void *)&desc->buffer - (void *)desc));
1192 }
1193
1194 /* Must be called with ohci->lock held */
1195 static struct descriptor *context_get_descriptors(struct context *ctx,
1196 int z, dma_addr_t *d_bus)
1197 {
1198 struct descriptor *d = NULL;
1199 struct descriptor_buffer *desc = ctx->buffer_tail;
1200
1201 if (z * sizeof(*d) > desc->buffer_size)
1202 return NULL;
1203
1204 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1205 /* No room for the descriptor in this buffer, so advance to the
1206 * next one. */
1207
1208 if (desc->list.next == &ctx->buffer_list) {
1209 /* If there is no free buffer next in the list,
1210 * allocate one. */
1211 if (context_add_buffer(ctx) < 0)
1212 return NULL;
1213 }
1214 desc = list_entry(desc->list.next,
1215 struct descriptor_buffer, list);
1216 ctx->buffer_tail = desc;
1217 }
1218
1219 d = desc->buffer + desc->used / sizeof(*d);
1220 memset(d, 0, z * sizeof(*d));
1221 *d_bus = desc->buffer_bus + desc->used;
1222
1223 return d;
1224 }
1225
1226 static void context_run(struct context *ctx, u32 extra)
1227 {
1228 struct fw_ohci *ohci = ctx->ohci;
1229
1230 reg_write(ohci, COMMAND_PTR(ctx->regs),
1231 le32_to_cpu(ctx->last->branch_address));
1232 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1233 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1234 ctx->running = true;
1235 flush_writes(ohci);
1236 }
1237
1238 static void context_append(struct context *ctx,
1239 struct descriptor *d, int z, int extra)
1240 {
1241 dma_addr_t d_bus;
1242 struct descriptor_buffer *desc = ctx->buffer_tail;
1243 struct descriptor *d_branch;
1244
1245 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1246
1247 desc->used += (z + extra) * sizeof(*d);
1248
1249 wmb(); /* finish init of new descriptors before branch_address update */
1250
1251 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1252 d_branch->branch_address = cpu_to_le32(d_bus | z);
1253
1254 /*
1255 * VT6306 incorrectly checks only the single descriptor at the
1256 * CommandPtr when the wake bit is written, so if it's a
1257 * multi-descriptor block starting with an INPUT_MORE, put a copy of
1258 * the branch address in the first descriptor.
1259 *
1260 * Not doing this for transmit contexts since not sure how it interacts
1261 * with skip addresses.
1262 */
1263 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1264 d_branch != ctx->prev &&
1265 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1266 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1267 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1268 }
1269
1270 ctx->prev = d;
1271 ctx->prev_z = z;
1272 }
1273
1274 static void context_stop(struct context *ctx)
1275 {
1276 struct fw_ohci *ohci = ctx->ohci;
1277 u32 reg;
1278 int i;
1279
1280 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1281 ctx->running = false;
1282
1283 for (i = 0; i < 1000; i++) {
1284 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1285 if ((reg & CONTEXT_ACTIVE) == 0)
1286 return;
1287
1288 if (i)
1289 udelay(10);
1290 }
1291 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1292 }
1293
1294 struct driver_data {
1295 u8 inline_data[8];
1296 struct fw_packet *packet;
1297 };
1298
1299 /*
1300 * This function apppends a packet to the DMA queue for transmission.
1301 * Must always be called with the ochi->lock held to ensure proper
1302 * generation handling and locking around packet queue manipulation.
1303 */
1304 static int at_context_queue_packet(struct context *ctx,
1305 struct fw_packet *packet)
1306 {
1307 struct fw_ohci *ohci = ctx->ohci;
1308 dma_addr_t d_bus, uninitialized_var(payload_bus);
1309 struct driver_data *driver_data;
1310 struct descriptor *d, *last;
1311 __le32 *header;
1312 int z, tcode;
1313
1314 d = context_get_descriptors(ctx, 4, &d_bus);
1315 if (d == NULL) {
1316 packet->ack = RCODE_SEND_ERROR;
1317 return -1;
1318 }
1319
1320 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1321 d[0].res_count = cpu_to_le16(packet->timestamp);
1322
1323 /*
1324 * The DMA format for asynchronous link packets is different
1325 * from the IEEE1394 layout, so shift the fields around
1326 * accordingly.
1327 */
1328
1329 tcode = (packet->header[0] >> 4) & 0x0f;
1330 header = (__le32 *) &d[1];
1331 switch (tcode) {
1332 case TCODE_WRITE_QUADLET_REQUEST:
1333 case TCODE_WRITE_BLOCK_REQUEST:
1334 case TCODE_WRITE_RESPONSE:
1335 case TCODE_READ_QUADLET_REQUEST:
1336 case TCODE_READ_BLOCK_REQUEST:
1337 case TCODE_READ_QUADLET_RESPONSE:
1338 case TCODE_READ_BLOCK_RESPONSE:
1339 case TCODE_LOCK_REQUEST:
1340 case TCODE_LOCK_RESPONSE:
1341 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1342 (packet->speed << 16));
1343 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1344 (packet->header[0] & 0xffff0000));
1345 header[2] = cpu_to_le32(packet->header[2]);
1346
1347 if (TCODE_IS_BLOCK_PACKET(tcode))
1348 header[3] = cpu_to_le32(packet->header[3]);
1349 else
1350 header[3] = (__force __le32) packet->header[3];
1351
1352 d[0].req_count = cpu_to_le16(packet->header_length);
1353 break;
1354
1355 case TCODE_LINK_INTERNAL:
1356 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1357 (packet->speed << 16));
1358 header[1] = cpu_to_le32(packet->header[1]);
1359 header[2] = cpu_to_le32(packet->header[2]);
1360 d[0].req_count = cpu_to_le16(12);
1361
1362 if (is_ping_packet(&packet->header[1]))
1363 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1364 break;
1365
1366 case TCODE_STREAM_DATA:
1367 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1368 (packet->speed << 16));
1369 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1370 d[0].req_count = cpu_to_le16(8);
1371 break;
1372
1373 default:
1374 /* BUG(); */
1375 packet->ack = RCODE_SEND_ERROR;
1376 return -1;
1377 }
1378
1379 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1380 driver_data = (struct driver_data *) &d[3];
1381 driver_data->packet = packet;
1382 packet->driver_data = driver_data;
1383
1384 if (packet->payload_length > 0) {
1385 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1386 payload_bus = dma_map_single(ohci->card.device,
1387 packet->payload,
1388 packet->payload_length,
1389 DMA_TO_DEVICE);
1390 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1391 packet->ack = RCODE_SEND_ERROR;
1392 return -1;
1393 }
1394 packet->payload_bus = payload_bus;
1395 packet->payload_mapped = true;
1396 } else {
1397 memcpy(driver_data->inline_data, packet->payload,
1398 packet->payload_length);
1399 payload_bus = d_bus + 3 * sizeof(*d);
1400 }
1401
1402 d[2].req_count = cpu_to_le16(packet->payload_length);
1403 d[2].data_address = cpu_to_le32(payload_bus);
1404 last = &d[2];
1405 z = 3;
1406 } else {
1407 last = &d[0];
1408 z = 2;
1409 }
1410
1411 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1412 DESCRIPTOR_IRQ_ALWAYS |
1413 DESCRIPTOR_BRANCH_ALWAYS);
1414
1415 /* FIXME: Document how the locking works. */
1416 if (ohci->generation != packet->generation) {
1417 if (packet->payload_mapped)
1418 dma_unmap_single(ohci->card.device, payload_bus,
1419 packet->payload_length, DMA_TO_DEVICE);
1420 packet->ack = RCODE_GENERATION;
1421 return -1;
1422 }
1423
1424 context_append(ctx, d, z, 4 - z);
1425
1426 if (ctx->running)
1427 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1428 else
1429 context_run(ctx, 0);
1430
1431 return 0;
1432 }
1433
1434 static void at_context_flush(struct context *ctx)
1435 {
1436 tasklet_disable(&ctx->tasklet);
1437
1438 ctx->flushing = true;
1439 context_tasklet((unsigned long)ctx);
1440 ctx->flushing = false;
1441
1442 tasklet_enable(&ctx->tasklet);
1443 }
1444
1445 static int handle_at_packet(struct context *context,
1446 struct descriptor *d,
1447 struct descriptor *last)
1448 {
1449 struct driver_data *driver_data;
1450 struct fw_packet *packet;
1451 struct fw_ohci *ohci = context->ohci;
1452 int evt;
1453
1454 if (last->transfer_status == 0 && !context->flushing)
1455 /* This descriptor isn't done yet, stop iteration. */
1456 return 0;
1457
1458 driver_data = (struct driver_data *) &d[3];
1459 packet = driver_data->packet;
1460 if (packet == NULL)
1461 /* This packet was cancelled, just continue. */
1462 return 1;
1463
1464 if (packet->payload_mapped)
1465 dma_unmap_single(ohci->card.device, packet->payload_bus,
1466 packet->payload_length, DMA_TO_DEVICE);
1467
1468 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1469 packet->timestamp = le16_to_cpu(last->res_count);
1470
1471 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1472
1473 switch (evt) {
1474 case OHCI1394_evt_timeout:
1475 /* Async response transmit timed out. */
1476 packet->ack = RCODE_CANCELLED;
1477 break;
1478
1479 case OHCI1394_evt_flushed:
1480 /*
1481 * The packet was flushed should give same error as
1482 * when we try to use a stale generation count.
1483 */
1484 packet->ack = RCODE_GENERATION;
1485 break;
1486
1487 case OHCI1394_evt_missing_ack:
1488 if (context->flushing)
1489 packet->ack = RCODE_GENERATION;
1490 else {
1491 /*
1492 * Using a valid (current) generation count, but the
1493 * node is not on the bus or not sending acks.
1494 */
1495 packet->ack = RCODE_NO_ACK;
1496 }
1497 break;
1498
1499 case ACK_COMPLETE + 0x10:
1500 case ACK_PENDING + 0x10:
1501 case ACK_BUSY_X + 0x10:
1502 case ACK_BUSY_A + 0x10:
1503 case ACK_BUSY_B + 0x10:
1504 case ACK_DATA_ERROR + 0x10:
1505 case ACK_TYPE_ERROR + 0x10:
1506 packet->ack = evt - 0x10;
1507 break;
1508
1509 case OHCI1394_evt_no_status:
1510 if (context->flushing) {
1511 packet->ack = RCODE_GENERATION;
1512 break;
1513 }
1514 /* fall through */
1515
1516 default:
1517 packet->ack = RCODE_SEND_ERROR;
1518 break;
1519 }
1520
1521 packet->callback(packet, &ohci->card, packet->ack);
1522
1523 return 1;
1524 }
1525
1526 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1527 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1528 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1529 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1530 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1531
1532 static void handle_local_rom(struct fw_ohci *ohci,
1533 struct fw_packet *packet, u32 csr)
1534 {
1535 struct fw_packet response;
1536 int tcode, length, i;
1537
1538 tcode = HEADER_GET_TCODE(packet->header[0]);
1539 if (TCODE_IS_BLOCK_PACKET(tcode))
1540 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1541 else
1542 length = 4;
1543
1544 i = csr - CSR_CONFIG_ROM;
1545 if (i + length > CONFIG_ROM_SIZE) {
1546 fw_fill_response(&response, packet->header,
1547 RCODE_ADDRESS_ERROR, NULL, 0);
1548 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1549 fw_fill_response(&response, packet->header,
1550 RCODE_TYPE_ERROR, NULL, 0);
1551 } else {
1552 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1553 (void *) ohci->config_rom + i, length);
1554 }
1555
1556 fw_core_handle_response(&ohci->card, &response);
1557 }
1558
1559 static void handle_local_lock(struct fw_ohci *ohci,
1560 struct fw_packet *packet, u32 csr)
1561 {
1562 struct fw_packet response;
1563 int tcode, length, ext_tcode, sel, try;
1564 __be32 *payload, lock_old;
1565 u32 lock_arg, lock_data;
1566
1567 tcode = HEADER_GET_TCODE(packet->header[0]);
1568 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1569 payload = packet->payload;
1570 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1571
1572 if (tcode == TCODE_LOCK_REQUEST &&
1573 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1574 lock_arg = be32_to_cpu(payload[0]);
1575 lock_data = be32_to_cpu(payload[1]);
1576 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1577 lock_arg = 0;
1578 lock_data = 0;
1579 } else {
1580 fw_fill_response(&response, packet->header,
1581 RCODE_TYPE_ERROR, NULL, 0);
1582 goto out;
1583 }
1584
1585 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1586 reg_write(ohci, OHCI1394_CSRData, lock_data);
1587 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1588 reg_write(ohci, OHCI1394_CSRControl, sel);
1589
1590 for (try = 0; try < 20; try++)
1591 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1592 lock_old = cpu_to_be32(reg_read(ohci,
1593 OHCI1394_CSRData));
1594 fw_fill_response(&response, packet->header,
1595 RCODE_COMPLETE,
1596 &lock_old, sizeof(lock_old));
1597 goto out;
1598 }
1599
1600 ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1601 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1602
1603 out:
1604 fw_core_handle_response(&ohci->card, &response);
1605 }
1606
1607 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1608 {
1609 u64 offset, csr;
1610
1611 if (ctx == &ctx->ohci->at_request_ctx) {
1612 packet->ack = ACK_PENDING;
1613 packet->callback(packet, &ctx->ohci->card, packet->ack);
1614 }
1615
1616 offset =
1617 ((unsigned long long)
1618 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1619 packet->header[2];
1620 csr = offset - CSR_REGISTER_BASE;
1621
1622 /* Handle config rom reads. */
1623 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1624 handle_local_rom(ctx->ohci, packet, csr);
1625 else switch (csr) {
1626 case CSR_BUS_MANAGER_ID:
1627 case CSR_BANDWIDTH_AVAILABLE:
1628 case CSR_CHANNELS_AVAILABLE_HI:
1629 case CSR_CHANNELS_AVAILABLE_LO:
1630 handle_local_lock(ctx->ohci, packet, csr);
1631 break;
1632 default:
1633 if (ctx == &ctx->ohci->at_request_ctx)
1634 fw_core_handle_request(&ctx->ohci->card, packet);
1635 else
1636 fw_core_handle_response(&ctx->ohci->card, packet);
1637 break;
1638 }
1639
1640 if (ctx == &ctx->ohci->at_response_ctx) {
1641 packet->ack = ACK_COMPLETE;
1642 packet->callback(packet, &ctx->ohci->card, packet->ack);
1643 }
1644 }
1645
1646 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1647 {
1648 unsigned long flags;
1649 int ret;
1650
1651 spin_lock_irqsave(&ctx->ohci->lock, flags);
1652
1653 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1654 ctx->ohci->generation == packet->generation) {
1655 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1656 handle_local_request(ctx, packet);
1657 return;
1658 }
1659
1660 ret = at_context_queue_packet(ctx, packet);
1661 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1662
1663 if (ret < 0)
1664 packet->callback(packet, &ctx->ohci->card, packet->ack);
1665
1666 }
1667
1668 static void detect_dead_context(struct fw_ohci *ohci,
1669 const char *name, unsigned int regs)
1670 {
1671 u32 ctl;
1672
1673 ctl = reg_read(ohci, CONTROL_SET(regs));
1674 if (ctl & CONTEXT_DEAD)
1675 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1676 name, evts[ctl & 0x1f]);
1677 }
1678
1679 static void handle_dead_contexts(struct fw_ohci *ohci)
1680 {
1681 unsigned int i;
1682 char name[8];
1683
1684 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1685 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1686 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1687 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1688 for (i = 0; i < 32; ++i) {
1689 if (!(ohci->it_context_support & (1 << i)))
1690 continue;
1691 sprintf(name, "IT%u", i);
1692 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1693 }
1694 for (i = 0; i < 32; ++i) {
1695 if (!(ohci->ir_context_support & (1 << i)))
1696 continue;
1697 sprintf(name, "IR%u", i);
1698 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1699 }
1700 /* TODO: maybe try to flush and restart the dead contexts */
1701 }
1702
1703 static u32 cycle_timer_ticks(u32 cycle_timer)
1704 {
1705 u32 ticks;
1706
1707 ticks = cycle_timer & 0xfff;
1708 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1709 ticks += (3072 * 8000) * (cycle_timer >> 25);
1710
1711 return ticks;
1712 }
1713
1714 /*
1715 * Some controllers exhibit one or more of the following bugs when updating the
1716 * iso cycle timer register:
1717 * - When the lowest six bits are wrapping around to zero, a read that happens
1718 * at the same time will return garbage in the lowest ten bits.
1719 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1720 * not incremented for about 60 ns.
1721 * - Occasionally, the entire register reads zero.
1722 *
1723 * To catch these, we read the register three times and ensure that the
1724 * difference between each two consecutive reads is approximately the same, i.e.
1725 * less than twice the other. Furthermore, any negative difference indicates an
1726 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1727 * execute, so we have enough precision to compute the ratio of the differences.)
1728 */
1729 static u32 get_cycle_time(struct fw_ohci *ohci)
1730 {
1731 u32 c0, c1, c2;
1732 u32 t0, t1, t2;
1733 s32 diff01, diff12;
1734 int i;
1735
1736 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1737
1738 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1739 i = 0;
1740 c1 = c2;
1741 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1742 do {
1743 c0 = c1;
1744 c1 = c2;
1745 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1746 t0 = cycle_timer_ticks(c0);
1747 t1 = cycle_timer_ticks(c1);
1748 t2 = cycle_timer_ticks(c2);
1749 diff01 = t1 - t0;
1750 diff12 = t2 - t1;
1751 } while ((diff01 <= 0 || diff12 <= 0 ||
1752 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1753 && i++ < 20);
1754 }
1755
1756 return c2;
1757 }
1758
1759 /*
1760 * This function has to be called at least every 64 seconds. The bus_time
1761 * field stores not only the upper 25 bits of the BUS_TIME register but also
1762 * the most significant bit of the cycle timer in bit 6 so that we can detect
1763 * changes in this bit.
1764 */
1765 static u32 update_bus_time(struct fw_ohci *ohci)
1766 {
1767 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1768
1769 if (unlikely(!ohci->bus_time_running)) {
1770 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1771 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1772 (cycle_time_seconds & 0x40);
1773 ohci->bus_time_running = true;
1774 }
1775
1776 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1777 ohci->bus_time += 0x40;
1778
1779 return ohci->bus_time | cycle_time_seconds;
1780 }
1781
1782 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1783 {
1784 int reg;
1785
1786 mutex_lock(&ohci->phy_reg_mutex);
1787 reg = write_phy_reg(ohci, 7, port_index);
1788 if (reg >= 0)
1789 reg = read_phy_reg(ohci, 8);
1790 mutex_unlock(&ohci->phy_reg_mutex);
1791 if (reg < 0)
1792 return reg;
1793
1794 switch (reg & 0x0f) {
1795 case 0x06:
1796 return 2; /* is child node (connected to parent node) */
1797 case 0x0e:
1798 return 3; /* is parent node (connected to child node) */
1799 }
1800 return 1; /* not connected */
1801 }
1802
1803 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1804 int self_id_count)
1805 {
1806 int i;
1807 u32 entry;
1808
1809 for (i = 0; i < self_id_count; i++) {
1810 entry = ohci->self_id_buffer[i];
1811 if ((self_id & 0xff000000) == (entry & 0xff000000))
1812 return -1;
1813 if ((self_id & 0xff000000) < (entry & 0xff000000))
1814 return i;
1815 }
1816 return i;
1817 }
1818
1819 static int initiated_reset(struct fw_ohci *ohci)
1820 {
1821 int reg;
1822 int ret = 0;
1823
1824 mutex_lock(&ohci->phy_reg_mutex);
1825 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1826 if (reg >= 0) {
1827 reg = read_phy_reg(ohci, 8);
1828 reg |= 0x40;
1829 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1830 if (reg >= 0) {
1831 reg = read_phy_reg(ohci, 12); /* read register 12 */
1832 if (reg >= 0) {
1833 if ((reg & 0x08) == 0x08) {
1834 /* bit 3 indicates "initiated reset" */
1835 ret = 0x2;
1836 }
1837 }
1838 }
1839 }
1840 mutex_unlock(&ohci->phy_reg_mutex);
1841 return ret;
1842 }
1843
1844 /*
1845 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1846 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1847 * Construct the selfID from phy register contents.
1848 */
1849 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1850 {
1851 int reg, i, pos, status;
1852 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1853 u32 self_id = 0x8040c800;
1854
1855 reg = reg_read(ohci, OHCI1394_NodeID);
1856 if (!(reg & OHCI1394_NodeID_idValid)) {
1857 ohci_notice(ohci,
1858 "node ID not valid, new bus reset in progress\n");
1859 return -EBUSY;
1860 }
1861 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1862
1863 reg = ohci_read_phy_reg(&ohci->card, 4);
1864 if (reg < 0)
1865 return reg;
1866 self_id |= ((reg & 0x07) << 8); /* power class */
1867
1868 reg = ohci_read_phy_reg(&ohci->card, 1);
1869 if (reg < 0)
1870 return reg;
1871 self_id |= ((reg & 0x3f) << 16); /* gap count */
1872
1873 for (i = 0; i < 3; i++) {
1874 status = get_status_for_port(ohci, i);
1875 if (status < 0)
1876 return status;
1877 self_id |= ((status & 0x3) << (6 - (i * 2)));
1878 }
1879
1880 self_id |= initiated_reset(ohci);
1881
1882 pos = get_self_id_pos(ohci, self_id, self_id_count);
1883 if (pos >= 0) {
1884 memmove(&(ohci->self_id_buffer[pos+1]),
1885 &(ohci->self_id_buffer[pos]),
1886 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1887 ohci->self_id_buffer[pos] = self_id;
1888 self_id_count++;
1889 }
1890 return self_id_count;
1891 }
1892
1893 static void bus_reset_work(struct work_struct *work)
1894 {
1895 struct fw_ohci *ohci =
1896 container_of(work, struct fw_ohci, bus_reset_work);
1897 int self_id_count, generation, new_generation, i, j;
1898 u32 reg;
1899 void *free_rom = NULL;
1900 dma_addr_t free_rom_bus = 0;
1901 bool is_new_root;
1902
1903 reg = reg_read(ohci, OHCI1394_NodeID);
1904 if (!(reg & OHCI1394_NodeID_idValid)) {
1905 ohci_notice(ohci,
1906 "node ID not valid, new bus reset in progress\n");
1907 return;
1908 }
1909 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1910 ohci_notice(ohci, "malconfigured bus\n");
1911 return;
1912 }
1913 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1914 OHCI1394_NodeID_nodeNumber);
1915
1916 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1917 if (!(ohci->is_root && is_new_root))
1918 reg_write(ohci, OHCI1394_LinkControlSet,
1919 OHCI1394_LinkControl_cycleMaster);
1920 ohci->is_root = is_new_root;
1921
1922 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1923 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1924 ohci_notice(ohci, "self ID receive error\n");
1925 return;
1926 }
1927 /*
1928 * The count in the SelfIDCount register is the number of
1929 * bytes in the self ID receive buffer. Since we also receive
1930 * the inverted quadlets and a header quadlet, we shift one
1931 * bit extra to get the actual number of self IDs.
1932 */
1933 self_id_count = (reg >> 3) & 0xff;
1934
1935 if (self_id_count > 252) {
1936 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1937 return;
1938 }
1939
1940 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1941 rmb();
1942
1943 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1944 u32 id = cond_le32_to_cpu(ohci->self_id[i]);
1945 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1946
1947 if (id != ~id2) {
1948 /*
1949 * If the invalid data looks like a cycle start packet,
1950 * it's likely to be the result of the cycle master
1951 * having a wrong gap count. In this case, the self IDs
1952 * so far are valid and should be processed so that the
1953 * bus manager can then correct the gap count.
1954 */
1955 if (id == 0xffff008f) {
1956 ohci_notice(ohci, "ignoring spurious self IDs\n");
1957 self_id_count = j;
1958 break;
1959 }
1960
1961 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1962 j, self_id_count, id, id2);
1963 return;
1964 }
1965 ohci->self_id_buffer[j] = id;
1966 }
1967
1968 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1969 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1970 if (self_id_count < 0) {
1971 ohci_notice(ohci,
1972 "could not construct local self ID\n");
1973 return;
1974 }
1975 }
1976
1977 if (self_id_count == 0) {
1978 ohci_notice(ohci, "no self IDs\n");
1979 return;
1980 }
1981 rmb();
1982
1983 /*
1984 * Check the consistency of the self IDs we just read. The
1985 * problem we face is that a new bus reset can start while we
1986 * read out the self IDs from the DMA buffer. If this happens,
1987 * the DMA buffer will be overwritten with new self IDs and we
1988 * will read out inconsistent data. The OHCI specification
1989 * (section 11.2) recommends a technique similar to
1990 * linux/seqlock.h, where we remember the generation of the
1991 * self IDs in the buffer before reading them out and compare
1992 * it to the current generation after reading them out. If
1993 * the two generations match we know we have a consistent set
1994 * of self IDs.
1995 */
1996
1997 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1998 if (new_generation != generation) {
1999 ohci_notice(ohci, "new bus reset, discarding self ids\n");
2000 return;
2001 }
2002
2003 /* FIXME: Document how the locking works. */
2004 spin_lock_irq(&ohci->lock);
2005
2006 ohci->generation = -1; /* prevent AT packet queueing */
2007 context_stop(&ohci->at_request_ctx);
2008 context_stop(&ohci->at_response_ctx);
2009
2010 spin_unlock_irq(&ohci->lock);
2011
2012 /*
2013 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2014 * packets in the AT queues and software needs to drain them.
2015 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2016 */
2017 at_context_flush(&ohci->at_request_ctx);
2018 at_context_flush(&ohci->at_response_ctx);
2019
2020 spin_lock_irq(&ohci->lock);
2021
2022 ohci->generation = generation;
2023 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2024
2025 if (ohci->quirks & QUIRK_RESET_PACKET)
2026 ohci->request_generation = generation;
2027
2028 /*
2029 * This next bit is unrelated to the AT context stuff but we
2030 * have to do it under the spinlock also. If a new config rom
2031 * was set up before this reset, the old one is now no longer
2032 * in use and we can free it. Update the config rom pointers
2033 * to point to the current config rom and clear the
2034 * next_config_rom pointer so a new update can take place.
2035 */
2036
2037 if (ohci->next_config_rom != NULL) {
2038 if (ohci->next_config_rom != ohci->config_rom) {
2039 free_rom = ohci->config_rom;
2040 free_rom_bus = ohci->config_rom_bus;
2041 }
2042 ohci->config_rom = ohci->next_config_rom;
2043 ohci->config_rom_bus = ohci->next_config_rom_bus;
2044 ohci->next_config_rom = NULL;
2045
2046 /*
2047 * Restore config_rom image and manually update
2048 * config_rom registers. Writing the header quadlet
2049 * will indicate that the config rom is ready, so we
2050 * do that last.
2051 */
2052 reg_write(ohci, OHCI1394_BusOptions,
2053 be32_to_cpu(ohci->config_rom[2]));
2054 ohci->config_rom[0] = ohci->next_header;
2055 reg_write(ohci, OHCI1394_ConfigROMhdr,
2056 be32_to_cpu(ohci->next_header));
2057 }
2058
2059 if (param_remote_dma) {
2060 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2061 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2062 }
2063
2064 spin_unlock_irq(&ohci->lock);
2065
2066 if (free_rom)
2067 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2068 free_rom, free_rom_bus);
2069
2070 log_selfids(ohci, generation, self_id_count);
2071
2072 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2073 self_id_count, ohci->self_id_buffer,
2074 ohci->csr_state_setclear_abdicate);
2075 ohci->csr_state_setclear_abdicate = false;
2076 }
2077
2078 static irqreturn_t irq_handler(int irq, void *data)
2079 {
2080 struct fw_ohci *ohci = data;
2081 u32 event, iso_event;
2082 int i;
2083
2084 event = reg_read(ohci, OHCI1394_IntEventClear);
2085
2086 if (!event || !~event)
2087 return IRQ_NONE;
2088
2089 /*
2090 * busReset and postedWriteErr must not be cleared yet
2091 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2092 */
2093 reg_write(ohci, OHCI1394_IntEventClear,
2094 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2095 log_irqs(ohci, event);
2096
2097 if (event & OHCI1394_selfIDComplete)
2098 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2099
2100 if (event & OHCI1394_RQPkt)
2101 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2102
2103 if (event & OHCI1394_RSPkt)
2104 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2105
2106 if (event & OHCI1394_reqTxComplete)
2107 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2108
2109 if (event & OHCI1394_respTxComplete)
2110 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2111
2112 if (event & OHCI1394_isochRx) {
2113 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2114 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2115
2116 while (iso_event) {
2117 i = ffs(iso_event) - 1;
2118 tasklet_schedule(
2119 &ohci->ir_context_list[i].context.tasklet);
2120 iso_event &= ~(1 << i);
2121 }
2122 }
2123
2124 if (event & OHCI1394_isochTx) {
2125 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2126 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2127
2128 while (iso_event) {
2129 i = ffs(iso_event) - 1;
2130 tasklet_schedule(
2131 &ohci->it_context_list[i].context.tasklet);
2132 iso_event &= ~(1 << i);
2133 }
2134 }
2135
2136 if (unlikely(event & OHCI1394_regAccessFail))
2137 ohci_err(ohci, "register access failure\n");
2138
2139 if (unlikely(event & OHCI1394_postedWriteErr)) {
2140 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2141 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2142 reg_write(ohci, OHCI1394_IntEventClear,
2143 OHCI1394_postedWriteErr);
2144 if (printk_ratelimit())
2145 ohci_err(ohci, "PCI posted write error\n");
2146 }
2147
2148 if (unlikely(event & OHCI1394_cycleTooLong)) {
2149 if (printk_ratelimit())
2150 ohci_notice(ohci, "isochronous cycle too long\n");
2151 reg_write(ohci, OHCI1394_LinkControlSet,
2152 OHCI1394_LinkControl_cycleMaster);
2153 }
2154
2155 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2156 /*
2157 * We need to clear this event bit in order to make
2158 * cycleMatch isochronous I/O work. In theory we should
2159 * stop active cycleMatch iso contexts now and restart
2160 * them at least two cycles later. (FIXME?)
2161 */
2162 if (printk_ratelimit())
2163 ohci_notice(ohci, "isochronous cycle inconsistent\n");
2164 }
2165
2166 if (unlikely(event & OHCI1394_unrecoverableError))
2167 handle_dead_contexts(ohci);
2168
2169 if (event & OHCI1394_cycle64Seconds) {
2170 spin_lock(&ohci->lock);
2171 update_bus_time(ohci);
2172 spin_unlock(&ohci->lock);
2173 } else
2174 flush_writes(ohci);
2175
2176 return IRQ_HANDLED;
2177 }
2178
2179 static int software_reset(struct fw_ohci *ohci)
2180 {
2181 u32 val;
2182 int i;
2183
2184 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2185 for (i = 0; i < 500; i++) {
2186 val = reg_read(ohci, OHCI1394_HCControlSet);
2187 if (!~val)
2188 return -ENODEV; /* Card was ejected. */
2189
2190 if (!(val & OHCI1394_HCControl_softReset))
2191 return 0;
2192
2193 msleep(1);
2194 }
2195
2196 return -EBUSY;
2197 }
2198
2199 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2200 {
2201 size_t size = length * 4;
2202
2203 memcpy(dest, src, size);
2204 if (size < CONFIG_ROM_SIZE)
2205 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2206 }
2207
2208 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2209 {
2210 bool enable_1394a;
2211 int ret, clear, set, offset;
2212
2213 /* Check if the driver should configure link and PHY. */
2214 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2215 OHCI1394_HCControl_programPhyEnable))
2216 return 0;
2217
2218 /* Paranoia: check whether the PHY supports 1394a, too. */
2219 enable_1394a = false;
2220 ret = read_phy_reg(ohci, 2);
2221 if (ret < 0)
2222 return ret;
2223 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2224 ret = read_paged_phy_reg(ohci, 1, 8);
2225 if (ret < 0)
2226 return ret;
2227 if (ret >= 1)
2228 enable_1394a = true;
2229 }
2230
2231 if (ohci->quirks & QUIRK_NO_1394A)
2232 enable_1394a = false;
2233
2234 /* Configure PHY and link consistently. */
2235 if (enable_1394a) {
2236 clear = 0;
2237 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2238 } else {
2239 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2240 set = 0;
2241 }
2242 ret = update_phy_reg(ohci, 5, clear, set);
2243 if (ret < 0)
2244 return ret;
2245
2246 if (enable_1394a)
2247 offset = OHCI1394_HCControlSet;
2248 else
2249 offset = OHCI1394_HCControlClear;
2250 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2251
2252 /* Clean up: configuration has been taken care of. */
2253 reg_write(ohci, OHCI1394_HCControlClear,
2254 OHCI1394_HCControl_programPhyEnable);
2255
2256 return 0;
2257 }
2258
2259 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2260 {
2261 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2262 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2263 int reg, i;
2264
2265 reg = read_phy_reg(ohci, 2);
2266 if (reg < 0)
2267 return reg;
2268 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2269 return 0;
2270
2271 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2272 reg = read_paged_phy_reg(ohci, 1, i + 10);
2273 if (reg < 0)
2274 return reg;
2275 if (reg != id[i])
2276 return 0;
2277 }
2278 return 1;
2279 }
2280
2281 static int ohci_enable(struct fw_card *card,
2282 const __be32 *config_rom, size_t length)
2283 {
2284 struct fw_ohci *ohci = fw_ohci(card);
2285 u32 lps, version, irqs;
2286 int i, ret;
2287
2288 if (software_reset(ohci)) {
2289 ohci_err(ohci, "failed to reset ohci card\n");
2290 return -EBUSY;
2291 }
2292
2293 /*
2294 * Now enable LPS, which we need in order to start accessing
2295 * most of the registers. In fact, on some cards (ALI M5251),
2296 * accessing registers in the SClk domain without LPS enabled
2297 * will lock up the machine. Wait 50msec to make sure we have
2298 * full link enabled. However, with some cards (well, at least
2299 * a JMicron PCIe card), we have to try again sometimes.
2300 *
2301 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2302 * cannot actually use the phy at that time. These need tens of
2303 * millisecods pause between LPS write and first phy access too.
2304 */
2305
2306 reg_write(ohci, OHCI1394_HCControlSet,
2307 OHCI1394_HCControl_LPS |
2308 OHCI1394_HCControl_postedWriteEnable);
2309 flush_writes(ohci);
2310
2311 for (lps = 0, i = 0; !lps && i < 3; i++) {
2312 msleep(50);
2313 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2314 OHCI1394_HCControl_LPS;
2315 }
2316
2317 if (!lps) {
2318 ohci_err(ohci, "failed to set Link Power Status\n");
2319 return -EIO;
2320 }
2321
2322 if (ohci->quirks & QUIRK_TI_SLLZ059) {
2323 ret = probe_tsb41ba3d(ohci);
2324 if (ret < 0)
2325 return ret;
2326 if (ret)
2327 ohci_notice(ohci, "local TSB41BA3D phy\n");
2328 else
2329 ohci->quirks &= ~QUIRK_TI_SLLZ059;
2330 }
2331
2332 reg_write(ohci, OHCI1394_HCControlClear,
2333 OHCI1394_HCControl_noByteSwapData);
2334
2335 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2336 reg_write(ohci, OHCI1394_LinkControlSet,
2337 OHCI1394_LinkControl_cycleTimerEnable |
2338 OHCI1394_LinkControl_cycleMaster);
2339
2340 reg_write(ohci, OHCI1394_ATRetries,
2341 OHCI1394_MAX_AT_REQ_RETRIES |
2342 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2343 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2344 (200 << 16));
2345
2346 ohci->bus_time_running = false;
2347
2348 for (i = 0; i < 32; i++)
2349 if (ohci->ir_context_support & (1 << i))
2350 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2351 IR_CONTEXT_MULTI_CHANNEL_MODE);
2352
2353 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2354 if (version >= OHCI_VERSION_1_1) {
2355 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2356 0xfffffffe);
2357 card->broadcast_channel_auto_allocated = true;
2358 }
2359
2360 /* Get implemented bits of the priority arbitration request counter. */
2361 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2362 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2363 reg_write(ohci, OHCI1394_FairnessControl, 0);
2364 card->priority_budget_implemented = ohci->pri_req_max != 0;
2365
2366 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2367 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2368 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2369
2370 ret = configure_1394a_enhancements(ohci);
2371 if (ret < 0)
2372 return ret;
2373
2374 /* Activate link_on bit and contender bit in our self ID packets.*/
2375 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2376 if (ret < 0)
2377 return ret;
2378
2379 /*
2380 * When the link is not yet enabled, the atomic config rom
2381 * update mechanism described below in ohci_set_config_rom()
2382 * is not active. We have to update ConfigRomHeader and
2383 * BusOptions manually, and the write to ConfigROMmap takes
2384 * effect immediately. We tie this to the enabling of the
2385 * link, so we have a valid config rom before enabling - the
2386 * OHCI requires that ConfigROMhdr and BusOptions have valid
2387 * values before enabling.
2388 *
2389 * However, when the ConfigROMmap is written, some controllers
2390 * always read back quadlets 0 and 2 from the config rom to
2391 * the ConfigRomHeader and BusOptions registers on bus reset.
2392 * They shouldn't do that in this initial case where the link
2393 * isn't enabled. This means we have to use the same
2394 * workaround here, setting the bus header to 0 and then write
2395 * the right values in the bus reset tasklet.
2396 */
2397
2398 if (config_rom) {
2399 ohci->next_config_rom =
2400 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2401 &ohci->next_config_rom_bus,
2402 GFP_KERNEL);
2403 if (ohci->next_config_rom == NULL)
2404 return -ENOMEM;
2405
2406 copy_config_rom(ohci->next_config_rom, config_rom, length);
2407 } else {
2408 /*
2409 * In the suspend case, config_rom is NULL, which
2410 * means that we just reuse the old config rom.
2411 */
2412 ohci->next_config_rom = ohci->config_rom;
2413 ohci->next_config_rom_bus = ohci->config_rom_bus;
2414 }
2415
2416 ohci->next_header = ohci->next_config_rom[0];
2417 ohci->next_config_rom[0] = 0;
2418 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2419 reg_write(ohci, OHCI1394_BusOptions,
2420 be32_to_cpu(ohci->next_config_rom[2]));
2421 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2422
2423 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2424
2425 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2426 OHCI1394_RQPkt | OHCI1394_RSPkt |
2427 OHCI1394_isochTx | OHCI1394_isochRx |
2428 OHCI1394_postedWriteErr |
2429 OHCI1394_selfIDComplete |
2430 OHCI1394_regAccessFail |
2431 OHCI1394_cycleInconsistent |
2432 OHCI1394_unrecoverableError |
2433 OHCI1394_cycleTooLong |
2434 OHCI1394_masterIntEnable;
2435 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2436 irqs |= OHCI1394_busReset;
2437 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2438
2439 reg_write(ohci, OHCI1394_HCControlSet,
2440 OHCI1394_HCControl_linkEnable |
2441 OHCI1394_HCControl_BIBimageValid);
2442
2443 reg_write(ohci, OHCI1394_LinkControlSet,
2444 OHCI1394_LinkControl_rcvSelfID |
2445 OHCI1394_LinkControl_rcvPhyPkt);
2446
2447 ar_context_run(&ohci->ar_request_ctx);
2448 ar_context_run(&ohci->ar_response_ctx);
2449
2450 flush_writes(ohci);
2451
2452 /* We are ready to go, reset bus to finish initialization. */
2453 fw_schedule_bus_reset(&ohci->card, false, true);
2454
2455 return 0;
2456 }
2457
2458 static int ohci_set_config_rom(struct fw_card *card,
2459 const __be32 *config_rom, size_t length)
2460 {
2461 struct fw_ohci *ohci;
2462 __be32 *next_config_rom;
2463 dma_addr_t uninitialized_var(next_config_rom_bus);
2464
2465 ohci = fw_ohci(card);
2466
2467 /*
2468 * When the OHCI controller is enabled, the config rom update
2469 * mechanism is a bit tricky, but easy enough to use. See
2470 * section 5.5.6 in the OHCI specification.
2471 *
2472 * The OHCI controller caches the new config rom address in a
2473 * shadow register (ConfigROMmapNext) and needs a bus reset
2474 * for the changes to take place. When the bus reset is
2475 * detected, the controller loads the new values for the
2476 * ConfigRomHeader and BusOptions registers from the specified
2477 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2478 * shadow register. All automatically and atomically.
2479 *
2480 * Now, there's a twist to this story. The automatic load of
2481 * ConfigRomHeader and BusOptions doesn't honor the
2482 * noByteSwapData bit, so with a be32 config rom, the
2483 * controller will load be32 values in to these registers
2484 * during the atomic update, even on litte endian
2485 * architectures. The workaround we use is to put a 0 in the
2486 * header quadlet; 0 is endian agnostic and means that the
2487 * config rom isn't ready yet. In the bus reset tasklet we
2488 * then set up the real values for the two registers.
2489 *
2490 * We use ohci->lock to avoid racing with the code that sets
2491 * ohci->next_config_rom to NULL (see bus_reset_work).
2492 */
2493
2494 next_config_rom =
2495 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2496 &next_config_rom_bus, GFP_KERNEL);
2497 if (next_config_rom == NULL)
2498 return -ENOMEM;
2499
2500 spin_lock_irq(&ohci->lock);
2501
2502 /*
2503 * If there is not an already pending config_rom update,
2504 * push our new allocation into the ohci->next_config_rom
2505 * and then mark the local variable as null so that we
2506 * won't deallocate the new buffer.
2507 *
2508 * OTOH, if there is a pending config_rom update, just
2509 * use that buffer with the new config_rom data, and
2510 * let this routine free the unused DMA allocation.
2511 */
2512
2513 if (ohci->next_config_rom == NULL) {
2514 ohci->next_config_rom = next_config_rom;
2515 ohci->next_config_rom_bus = next_config_rom_bus;
2516 next_config_rom = NULL;
2517 }
2518
2519 copy_config_rom(ohci->next_config_rom, config_rom, length);
2520
2521 ohci->next_header = config_rom[0];
2522 ohci->next_config_rom[0] = 0;
2523
2524 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2525
2526 spin_unlock_irq(&ohci->lock);
2527
2528 /* If we didn't use the DMA allocation, delete it. */
2529 if (next_config_rom != NULL)
2530 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2531 next_config_rom, next_config_rom_bus);
2532
2533 /*
2534 * Now initiate a bus reset to have the changes take
2535 * effect. We clean up the old config rom memory and DMA
2536 * mappings in the bus reset tasklet, since the OHCI
2537 * controller could need to access it before the bus reset
2538 * takes effect.
2539 */
2540
2541 fw_schedule_bus_reset(&ohci->card, true, true);
2542
2543 return 0;
2544 }
2545
2546 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2547 {
2548 struct fw_ohci *ohci = fw_ohci(card);
2549
2550 at_context_transmit(&ohci->at_request_ctx, packet);
2551 }
2552
2553 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2554 {
2555 struct fw_ohci *ohci = fw_ohci(card);
2556
2557 at_context_transmit(&ohci->at_response_ctx, packet);
2558 }
2559
2560 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2561 {
2562 struct fw_ohci *ohci = fw_ohci(card);
2563 struct context *ctx = &ohci->at_request_ctx;
2564 struct driver_data *driver_data = packet->driver_data;
2565 int ret = -ENOENT;
2566
2567 tasklet_disable(&ctx->tasklet);
2568
2569 if (packet->ack != 0)
2570 goto out;
2571
2572 if (packet->payload_mapped)
2573 dma_unmap_single(ohci->card.device, packet->payload_bus,
2574 packet->payload_length, DMA_TO_DEVICE);
2575
2576 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2577 driver_data->packet = NULL;
2578 packet->ack = RCODE_CANCELLED;
2579 packet->callback(packet, &ohci->card, packet->ack);
2580 ret = 0;
2581 out:
2582 tasklet_enable(&ctx->tasklet);
2583
2584 return ret;
2585 }
2586
2587 static int ohci_enable_phys_dma(struct fw_card *card,
2588 int node_id, int generation)
2589 {
2590 struct fw_ohci *ohci = fw_ohci(card);
2591 unsigned long flags;
2592 int n, ret = 0;
2593
2594 if (param_remote_dma)
2595 return 0;
2596
2597 /*
2598 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2599 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2600 */
2601
2602 spin_lock_irqsave(&ohci->lock, flags);
2603
2604 if (ohci->generation != generation) {
2605 ret = -ESTALE;
2606 goto out;
2607 }
2608
2609 /*
2610 * Note, if the node ID contains a non-local bus ID, physical DMA is
2611 * enabled for _all_ nodes on remote buses.
2612 */
2613
2614 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2615 if (n < 32)
2616 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2617 else
2618 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2619
2620 flush_writes(ohci);
2621 out:
2622 spin_unlock_irqrestore(&ohci->lock, flags);
2623
2624 return ret;
2625 }
2626
2627 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2628 {
2629 struct fw_ohci *ohci = fw_ohci(card);
2630 unsigned long flags;
2631 u32 value;
2632
2633 switch (csr_offset) {
2634 case CSR_STATE_CLEAR:
2635 case CSR_STATE_SET:
2636 if (ohci->is_root &&
2637 (reg_read(ohci, OHCI1394_LinkControlSet) &
2638 OHCI1394_LinkControl_cycleMaster))
2639 value = CSR_STATE_BIT_CMSTR;
2640 else
2641 value = 0;
2642 if (ohci->csr_state_setclear_abdicate)
2643 value |= CSR_STATE_BIT_ABDICATE;
2644
2645 return value;
2646
2647 case CSR_NODE_IDS:
2648 return reg_read(ohci, OHCI1394_NodeID) << 16;
2649
2650 case CSR_CYCLE_TIME:
2651 return get_cycle_time(ohci);
2652
2653 case CSR_BUS_TIME:
2654 /*
2655 * We might be called just after the cycle timer has wrapped
2656 * around but just before the cycle64Seconds handler, so we
2657 * better check here, too, if the bus time needs to be updated.
2658 */
2659 spin_lock_irqsave(&ohci->lock, flags);
2660 value = update_bus_time(ohci);
2661 spin_unlock_irqrestore(&ohci->lock, flags);
2662 return value;
2663
2664 case CSR_BUSY_TIMEOUT:
2665 value = reg_read(ohci, OHCI1394_ATRetries);
2666 return (value >> 4) & 0x0ffff00f;
2667
2668 case CSR_PRIORITY_BUDGET:
2669 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2670 (ohci->pri_req_max << 8);
2671
2672 default:
2673 WARN_ON(1);
2674 return 0;
2675 }
2676 }
2677
2678 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2679 {
2680 struct fw_ohci *ohci = fw_ohci(card);
2681 unsigned long flags;
2682
2683 switch (csr_offset) {
2684 case CSR_STATE_CLEAR:
2685 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2686 reg_write(ohci, OHCI1394_LinkControlClear,
2687 OHCI1394_LinkControl_cycleMaster);
2688 flush_writes(ohci);
2689 }
2690 if (value & CSR_STATE_BIT_ABDICATE)
2691 ohci->csr_state_setclear_abdicate = false;
2692 break;
2693
2694 case CSR_STATE_SET:
2695 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2696 reg_write(ohci, OHCI1394_LinkControlSet,
2697 OHCI1394_LinkControl_cycleMaster);
2698 flush_writes(ohci);
2699 }
2700 if (value & CSR_STATE_BIT_ABDICATE)
2701 ohci->csr_state_setclear_abdicate = true;
2702 break;
2703
2704 case CSR_NODE_IDS:
2705 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2706 flush_writes(ohci);
2707 break;
2708
2709 case CSR_CYCLE_TIME:
2710 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2711 reg_write(ohci, OHCI1394_IntEventSet,
2712 OHCI1394_cycleInconsistent);
2713 flush_writes(ohci);
2714 break;
2715
2716 case CSR_BUS_TIME:
2717 spin_lock_irqsave(&ohci->lock, flags);
2718 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2719 (value & ~0x7f);
2720 spin_unlock_irqrestore(&ohci->lock, flags);
2721 break;
2722
2723 case CSR_BUSY_TIMEOUT:
2724 value = (value & 0xf) | ((value & 0xf) << 4) |
2725 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2726 reg_write(ohci, OHCI1394_ATRetries, value);
2727 flush_writes(ohci);
2728 break;
2729
2730 case CSR_PRIORITY_BUDGET:
2731 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2732 flush_writes(ohci);
2733 break;
2734
2735 default:
2736 WARN_ON(1);
2737 break;
2738 }
2739 }
2740
2741 static void flush_iso_completions(struct iso_context *ctx)
2742 {
2743 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2744 ctx->header_length, ctx->header,
2745 ctx->base.callback_data);
2746 ctx->header_length = 0;
2747 }
2748
2749 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2750 {
2751 u32 *ctx_hdr;
2752
2753 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2754 if (ctx->base.drop_overflow_headers)
2755 return;
2756 flush_iso_completions(ctx);
2757 }
2758
2759 ctx_hdr = ctx->header + ctx->header_length;
2760 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2761
2762 /*
2763 * The two iso header quadlets are byteswapped to little
2764 * endian by the controller, but we want to present them
2765 * as big endian for consistency with the bus endianness.
2766 */
2767 if (ctx->base.header_size > 0)
2768 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2769 if (ctx->base.header_size > 4)
2770 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2771 if (ctx->base.header_size > 8)
2772 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2773 ctx->header_length += ctx->base.header_size;
2774 }
2775
2776 static int handle_ir_packet_per_buffer(struct context *context,
2777 struct descriptor *d,
2778 struct descriptor *last)
2779 {
2780 struct iso_context *ctx =
2781 container_of(context, struct iso_context, context);
2782 struct descriptor *pd;
2783 u32 buffer_dma;
2784
2785 for (pd = d; pd <= last; pd++)
2786 if (pd->transfer_status)
2787 break;
2788 if (pd > last)
2789 /* Descriptor(s) not done yet, stop iteration */
2790 return 0;
2791
2792 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2793 d++;
2794 buffer_dma = le32_to_cpu(d->data_address);
2795 dma_sync_single_range_for_cpu(context->ohci->card.device,
2796 buffer_dma & PAGE_MASK,
2797 buffer_dma & ~PAGE_MASK,
2798 le16_to_cpu(d->req_count),
2799 DMA_FROM_DEVICE);
2800 }
2801
2802 copy_iso_headers(ctx, (u32 *) (last + 1));
2803
2804 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2805 flush_iso_completions(ctx);
2806
2807 return 1;
2808 }
2809
2810 /* d == last because each descriptor block is only a single descriptor. */
2811 static int handle_ir_buffer_fill(struct context *context,
2812 struct descriptor *d,
2813 struct descriptor *last)
2814 {
2815 struct iso_context *ctx =
2816 container_of(context, struct iso_context, context);
2817 unsigned int req_count, res_count, completed;
2818 u32 buffer_dma;
2819
2820 req_count = le16_to_cpu(last->req_count);
2821 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2822 completed = req_count - res_count;
2823 buffer_dma = le32_to_cpu(last->data_address);
2824
2825 if (completed > 0) {
2826 ctx->mc_buffer_bus = buffer_dma;
2827 ctx->mc_completed = completed;
2828 }
2829
2830 if (res_count != 0)
2831 /* Descriptor(s) not done yet, stop iteration */
2832 return 0;
2833
2834 dma_sync_single_range_for_cpu(context->ohci->card.device,
2835 buffer_dma & PAGE_MASK,
2836 buffer_dma & ~PAGE_MASK,
2837 completed, DMA_FROM_DEVICE);
2838
2839 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2840 ctx->base.callback.mc(&ctx->base,
2841 buffer_dma + completed,
2842 ctx->base.callback_data);
2843 ctx->mc_completed = 0;
2844 }
2845
2846 return 1;
2847 }
2848
2849 static void flush_ir_buffer_fill(struct iso_context *ctx)
2850 {
2851 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2852 ctx->mc_buffer_bus & PAGE_MASK,
2853 ctx->mc_buffer_bus & ~PAGE_MASK,
2854 ctx->mc_completed, DMA_FROM_DEVICE);
2855
2856 ctx->base.callback.mc(&ctx->base,
2857 ctx->mc_buffer_bus + ctx->mc_completed,
2858 ctx->base.callback_data);
2859 ctx->mc_completed = 0;
2860 }
2861
2862 static inline void sync_it_packet_for_cpu(struct context *context,
2863 struct descriptor *pd)
2864 {
2865 __le16 control;
2866 u32 buffer_dma;
2867
2868 /* only packets beginning with OUTPUT_MORE* have data buffers */
2869 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2870 return;
2871
2872 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2873 pd += 2;
2874
2875 /*
2876 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2877 * data buffer is in the context program's coherent page and must not
2878 * be synced.
2879 */
2880 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2881 (context->current_bus & PAGE_MASK)) {
2882 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2883 return;
2884 pd++;
2885 }
2886
2887 do {
2888 buffer_dma = le32_to_cpu(pd->data_address);
2889 dma_sync_single_range_for_cpu(context->ohci->card.device,
2890 buffer_dma & PAGE_MASK,
2891 buffer_dma & ~PAGE_MASK,
2892 le16_to_cpu(pd->req_count),
2893 DMA_TO_DEVICE);
2894 control = pd->control;
2895 pd++;
2896 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2897 }
2898
2899 static int handle_it_packet(struct context *context,
2900 struct descriptor *d,
2901 struct descriptor *last)
2902 {
2903 struct iso_context *ctx =
2904 container_of(context, struct iso_context, context);
2905 struct descriptor *pd;
2906 __be32 *ctx_hdr;
2907
2908 for (pd = d; pd <= last; pd++)
2909 if (pd->transfer_status)
2910 break;
2911 if (pd > last)
2912 /* Descriptor(s) not done yet, stop iteration */
2913 return 0;
2914
2915 sync_it_packet_for_cpu(context, d);
2916
2917 if (ctx->header_length + 4 > PAGE_SIZE) {
2918 if (ctx->base.drop_overflow_headers)
2919 return 1;
2920 flush_iso_completions(ctx);
2921 }
2922
2923 ctx_hdr = ctx->header + ctx->header_length;
2924 ctx->last_timestamp = le16_to_cpu(last->res_count);
2925 /* Present this value as big-endian to match the receive code */
2926 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2927 le16_to_cpu(pd->res_count));
2928 ctx->header_length += 4;
2929
2930 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2931 flush_iso_completions(ctx);
2932
2933 return 1;
2934 }
2935
2936 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2937 {
2938 u32 hi = channels >> 32, lo = channels;
2939
2940 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2941 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2942 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2943 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2944 mmiowb();
2945 ohci->mc_channels = channels;
2946 }
2947
2948 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2949 int type, int channel, size_t header_size)
2950 {
2951 struct fw_ohci *ohci = fw_ohci(card);
2952 struct iso_context *uninitialized_var(ctx);
2953 descriptor_callback_t uninitialized_var(callback);
2954 u64 *uninitialized_var(channels);
2955 u32 *uninitialized_var(mask), uninitialized_var(regs);
2956 int index, ret = -EBUSY;
2957
2958 spin_lock_irq(&ohci->lock);
2959
2960 switch (type) {
2961 case FW_ISO_CONTEXT_TRANSMIT:
2962 mask = &ohci->it_context_mask;
2963 callback = handle_it_packet;
2964 index = ffs(*mask) - 1;
2965 if (index >= 0) {
2966 *mask &= ~(1 << index);
2967 regs = OHCI1394_IsoXmitContextBase(index);
2968 ctx = &ohci->it_context_list[index];
2969 }
2970 break;
2971
2972 case FW_ISO_CONTEXT_RECEIVE:
2973 channels = &ohci->ir_context_channels;
2974 mask = &ohci->ir_context_mask;
2975 callback = handle_ir_packet_per_buffer;
2976 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2977 if (index >= 0) {
2978 *channels &= ~(1ULL << channel);
2979 *mask &= ~(1 << index);
2980 regs = OHCI1394_IsoRcvContextBase(index);
2981 ctx = &ohci->ir_context_list[index];
2982 }
2983 break;
2984
2985 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2986 mask = &ohci->ir_context_mask;
2987 callback = handle_ir_buffer_fill;
2988 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2989 if (index >= 0) {
2990 ohci->mc_allocated = true;
2991 *mask &= ~(1 << index);
2992 regs = OHCI1394_IsoRcvContextBase(index);
2993 ctx = &ohci->ir_context_list[index];
2994 }
2995 break;
2996
2997 default:
2998 index = -1;
2999 ret = -ENOSYS;
3000 }
3001
3002 spin_unlock_irq(&ohci->lock);
3003
3004 if (index < 0)
3005 return ERR_PTR(ret);
3006
3007 memset(ctx, 0, sizeof(*ctx));
3008 ctx->header_length = 0;
3009 ctx->header = (void *) __get_free_page(GFP_KERNEL);
3010 if (ctx->header == NULL) {
3011 ret = -ENOMEM;
3012 goto out;
3013 }
3014 ret = context_init(&ctx->context, ohci, regs, callback);
3015 if (ret < 0)
3016 goto out_with_header;
3017
3018 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3019 set_multichannel_mask(ohci, 0);
3020 ctx->mc_completed = 0;
3021 }
3022
3023 return &ctx->base;
3024
3025 out_with_header:
3026 free_page((unsigned long)ctx->header);
3027 out:
3028 spin_lock_irq(&ohci->lock);
3029
3030 switch (type) {
3031 case FW_ISO_CONTEXT_RECEIVE:
3032 *channels |= 1ULL << channel;
3033 break;
3034
3035 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3036 ohci->mc_allocated = false;
3037 break;
3038 }
3039 *mask |= 1 << index;
3040
3041 spin_unlock_irq(&ohci->lock);
3042
3043 return ERR_PTR(ret);
3044 }
3045
3046 static int ohci_start_iso(struct fw_iso_context *base,
3047 s32 cycle, u32 sync, u32 tags)
3048 {
3049 struct iso_context *ctx = container_of(base, struct iso_context, base);
3050 struct fw_ohci *ohci = ctx->context.ohci;
3051 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3052 int index;
3053
3054 /* the controller cannot start without any queued packets */
3055 if (ctx->context.last->branch_address == 0)
3056 return -ENODATA;
3057
3058 switch (ctx->base.type) {
3059 case FW_ISO_CONTEXT_TRANSMIT:
3060 index = ctx - ohci->it_context_list;
3061 match = 0;
3062 if (cycle >= 0)
3063 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3064 (cycle & 0x7fff) << 16;
3065
3066 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3067 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3068 context_run(&ctx->context, match);
3069 break;
3070
3071 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3072 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3073 /* fall through */
3074 case FW_ISO_CONTEXT_RECEIVE:
3075 index = ctx - ohci->ir_context_list;
3076 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3077 if (cycle >= 0) {
3078 match |= (cycle & 0x07fff) << 12;
3079 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3080 }
3081
3082 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3083 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3084 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3085 context_run(&ctx->context, control);
3086
3087 ctx->sync = sync;
3088 ctx->tags = tags;
3089
3090 break;
3091 }
3092
3093 return 0;
3094 }
3095
3096 static int ohci_stop_iso(struct fw_iso_context *base)
3097 {
3098 struct fw_ohci *ohci = fw_ohci(base->card);
3099 struct iso_context *ctx = container_of(base, struct iso_context, base);
3100 int index;
3101
3102 switch (ctx->base.type) {
3103 case FW_ISO_CONTEXT_TRANSMIT:
3104 index = ctx - ohci->it_context_list;
3105 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3106 break;
3107
3108 case FW_ISO_CONTEXT_RECEIVE:
3109 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3110 index = ctx - ohci->ir_context_list;
3111 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3112 break;
3113 }
3114 flush_writes(ohci);
3115 context_stop(&ctx->context);
3116 tasklet_kill(&ctx->context.tasklet);
3117
3118 return 0;
3119 }
3120
3121 static void ohci_free_iso_context(struct fw_iso_context *base)
3122 {
3123 struct fw_ohci *ohci = fw_ohci(base->card);
3124 struct iso_context *ctx = container_of(base, struct iso_context, base);
3125 unsigned long flags;
3126 int index;
3127
3128 ohci_stop_iso(base);
3129 context_release(&ctx->context);
3130 free_page((unsigned long)ctx->header);
3131
3132 spin_lock_irqsave(&ohci->lock, flags);
3133
3134 switch (base->type) {
3135 case FW_ISO_CONTEXT_TRANSMIT:
3136 index = ctx - ohci->it_context_list;
3137 ohci->it_context_mask |= 1 << index;
3138 break;
3139
3140 case FW_ISO_CONTEXT_RECEIVE:
3141 index = ctx - ohci->ir_context_list;
3142 ohci->ir_context_mask |= 1 << index;
3143 ohci->ir_context_channels |= 1ULL << base->channel;
3144 break;
3145
3146 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3147 index = ctx - ohci->ir_context_list;
3148 ohci->ir_context_mask |= 1 << index;
3149 ohci->ir_context_channels |= ohci->mc_channels;
3150 ohci->mc_channels = 0;
3151 ohci->mc_allocated = false;
3152 break;
3153 }
3154
3155 spin_unlock_irqrestore(&ohci->lock, flags);
3156 }
3157
3158 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3159 {
3160 struct fw_ohci *ohci = fw_ohci(base->card);
3161 unsigned long flags;
3162 int ret;
3163
3164 switch (base->type) {
3165 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3166
3167 spin_lock_irqsave(&ohci->lock, flags);
3168
3169 /* Don't allow multichannel to grab other contexts' channels. */
3170 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3171 *channels = ohci->ir_context_channels;
3172 ret = -EBUSY;
3173 } else {
3174 set_multichannel_mask(ohci, *channels);
3175 ret = 0;
3176 }
3177
3178 spin_unlock_irqrestore(&ohci->lock, flags);
3179
3180 break;
3181 default:
3182 ret = -EINVAL;
3183 }
3184
3185 return ret;
3186 }
3187
3188 #ifdef CONFIG_PM
3189 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3190 {
3191 int i;
3192 struct iso_context *ctx;
3193
3194 for (i = 0 ; i < ohci->n_ir ; i++) {
3195 ctx = &ohci->ir_context_list[i];
3196 if (ctx->context.running)
3197 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3198 }
3199
3200 for (i = 0 ; i < ohci->n_it ; i++) {
3201 ctx = &ohci->it_context_list[i];
3202 if (ctx->context.running)
3203 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3204 }
3205 }
3206 #endif
3207
3208 static int queue_iso_transmit(struct iso_context *ctx,
3209 struct fw_iso_packet *packet,
3210 struct fw_iso_buffer *buffer,
3211 unsigned long payload)
3212 {
3213 struct descriptor *d, *last, *pd;
3214 struct fw_iso_packet *p;
3215 __le32 *header;
3216 dma_addr_t d_bus, page_bus;
3217 u32 z, header_z, payload_z, irq;
3218 u32 payload_index, payload_end_index, next_page_index;
3219 int page, end_page, i, length, offset;
3220
3221 p = packet;
3222 payload_index = payload;
3223
3224 if (p->skip)
3225 z = 1;
3226 else
3227 z = 2;
3228 if (p->header_length > 0)
3229 z++;
3230
3231 /* Determine the first page the payload isn't contained in. */
3232 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3233 if (p->payload_length > 0)
3234 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3235 else
3236 payload_z = 0;
3237
3238 z += payload_z;
3239
3240 /* Get header size in number of descriptors. */
3241 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3242
3243 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3244 if (d == NULL)
3245 return -ENOMEM;
3246
3247 if (!p->skip) {
3248 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3249 d[0].req_count = cpu_to_le16(8);
3250 /*
3251 * Link the skip address to this descriptor itself. This causes
3252 * a context to skip a cycle whenever lost cycles or FIFO
3253 * overruns occur, without dropping the data. The application
3254 * should then decide whether this is an error condition or not.
3255 * FIXME: Make the context's cycle-lost behaviour configurable?
3256 */
3257 d[0].branch_address = cpu_to_le32(d_bus | z);
3258
3259 header = (__le32 *) &d[1];
3260 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3261 IT_HEADER_TAG(p->tag) |
3262 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3263 IT_HEADER_CHANNEL(ctx->base.channel) |
3264 IT_HEADER_SPEED(ctx->base.speed));
3265 header[1] =
3266 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3267 p->payload_length));
3268 }
3269
3270 if (p->header_length > 0) {
3271 d[2].req_count = cpu_to_le16(p->header_length);
3272 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3273 memcpy(&d[z], p->header, p->header_length);
3274 }
3275
3276 pd = d + z - payload_z;
3277 payload_end_index = payload_index + p->payload_length;
3278 for (i = 0; i < payload_z; i++) {
3279 page = payload_index >> PAGE_SHIFT;
3280 offset = payload_index & ~PAGE_MASK;
3281 next_page_index = (page + 1) << PAGE_SHIFT;
3282 length =
3283 min(next_page_index, payload_end_index) - payload_index;
3284 pd[i].req_count = cpu_to_le16(length);
3285
3286 page_bus = page_private(buffer->pages[page]);
3287 pd[i].data_address = cpu_to_le32(page_bus + offset);
3288
3289 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3290 page_bus, offset, length,
3291 DMA_TO_DEVICE);
3292
3293 payload_index += length;
3294 }
3295
3296 if (p->interrupt)
3297 irq = DESCRIPTOR_IRQ_ALWAYS;
3298 else
3299 irq = DESCRIPTOR_NO_IRQ;
3300
3301 last = z == 2 ? d : d + z - 1;
3302 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3303 DESCRIPTOR_STATUS |
3304 DESCRIPTOR_BRANCH_ALWAYS |
3305 irq);
3306
3307 context_append(&ctx->context, d, z, header_z);
3308
3309 return 0;
3310 }
3311
3312 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3313 struct fw_iso_packet *packet,
3314 struct fw_iso_buffer *buffer,
3315 unsigned long payload)
3316 {
3317 struct device *device = ctx->context.ohci->card.device;
3318 struct descriptor *d, *pd;
3319 dma_addr_t d_bus, page_bus;
3320 u32 z, header_z, rest;
3321 int i, j, length;
3322 int page, offset, packet_count, header_size, payload_per_buffer;
3323
3324 /*
3325 * The OHCI controller puts the isochronous header and trailer in the
3326 * buffer, so we need at least 8 bytes.
3327 */
3328 packet_count = packet->header_length / ctx->base.header_size;
3329 header_size = max(ctx->base.header_size, (size_t)8);
3330
3331 /* Get header size in number of descriptors. */
3332 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3333 page = payload >> PAGE_SHIFT;
3334 offset = payload & ~PAGE_MASK;
3335 payload_per_buffer = packet->payload_length / packet_count;
3336
3337 for (i = 0; i < packet_count; i++) {
3338 /* d points to the header descriptor */
3339 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3340 d = context_get_descriptors(&ctx->context,
3341 z + header_z, &d_bus);
3342 if (d == NULL)
3343 return -ENOMEM;
3344
3345 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3346 DESCRIPTOR_INPUT_MORE);
3347 if (packet->skip && i == 0)
3348 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3349 d->req_count = cpu_to_le16(header_size);
3350 d->res_count = d->req_count;
3351 d->transfer_status = 0;
3352 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3353
3354 rest = payload_per_buffer;
3355 pd = d;
3356 for (j = 1; j < z; j++) {
3357 pd++;
3358 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3359 DESCRIPTOR_INPUT_MORE);
3360
3361 if (offset + rest < PAGE_SIZE)
3362 length = rest;
3363 else
3364 length = PAGE_SIZE - offset;
3365 pd->req_count = cpu_to_le16(length);
3366 pd->res_count = pd->req_count;
3367 pd->transfer_status = 0;
3368
3369 page_bus = page_private(buffer->pages[page]);
3370 pd->data_address = cpu_to_le32(page_bus + offset);
3371
3372 dma_sync_single_range_for_device(device, page_bus,
3373 offset, length,
3374 DMA_FROM_DEVICE);
3375
3376 offset = (offset + length) & ~PAGE_MASK;
3377 rest -= length;
3378 if (offset == 0)
3379 page++;
3380 }
3381 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3382 DESCRIPTOR_INPUT_LAST |
3383 DESCRIPTOR_BRANCH_ALWAYS);
3384 if (packet->interrupt && i == packet_count - 1)
3385 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3386
3387 context_append(&ctx->context, d, z, header_z);
3388 }
3389
3390 return 0;
3391 }
3392
3393 static int queue_iso_buffer_fill(struct iso_context *ctx,
3394 struct fw_iso_packet *packet,
3395 struct fw_iso_buffer *buffer,
3396 unsigned long payload)
3397 {
3398 struct descriptor *d;
3399 dma_addr_t d_bus, page_bus;
3400 int page, offset, rest, z, i, length;
3401
3402 page = payload >> PAGE_SHIFT;
3403 offset = payload & ~PAGE_MASK;
3404 rest = packet->payload_length;
3405
3406 /* We need one descriptor for each page in the buffer. */
3407 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3408
3409 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3410 return -EFAULT;
3411
3412 for (i = 0; i < z; i++) {
3413 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3414 if (d == NULL)
3415 return -ENOMEM;
3416
3417 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3418 DESCRIPTOR_BRANCH_ALWAYS);
3419 if (packet->skip && i == 0)
3420 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3421 if (packet->interrupt && i == z - 1)
3422 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3423
3424 if (offset + rest < PAGE_SIZE)
3425 length = rest;
3426 else
3427 length = PAGE_SIZE - offset;
3428 d->req_count = cpu_to_le16(length);
3429 d->res_count = d->req_count;
3430 d->transfer_status = 0;
3431
3432 page_bus = page_private(buffer->pages[page]);
3433 d->data_address = cpu_to_le32(page_bus + offset);
3434
3435 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3436 page_bus, offset, length,
3437 DMA_FROM_DEVICE);
3438
3439 rest -= length;
3440 offset = 0;
3441 page++;
3442
3443 context_append(&ctx->context, d, 1, 0);
3444 }
3445
3446 return 0;
3447 }
3448
3449 static int ohci_queue_iso(struct fw_iso_context *base,
3450 struct fw_iso_packet *packet,
3451 struct fw_iso_buffer *buffer,
3452 unsigned long payload)
3453 {
3454 struct iso_context *ctx = container_of(base, struct iso_context, base);
3455 unsigned long flags;
3456 int ret = -ENOSYS;
3457
3458 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3459 switch (base->type) {
3460 case FW_ISO_CONTEXT_TRANSMIT:
3461 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3462 break;
3463 case FW_ISO_CONTEXT_RECEIVE:
3464 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3465 break;
3466 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3467 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3468 break;
3469 }
3470 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3471
3472 return ret;
3473 }
3474
3475 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3476 {
3477 struct context *ctx =
3478 &container_of(base, struct iso_context, base)->context;
3479
3480 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3481 }
3482
3483 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3484 {
3485 struct iso_context *ctx = container_of(base, struct iso_context, base);
3486 int ret = 0;
3487
3488 tasklet_disable(&ctx->context.tasklet);
3489
3490 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3491 context_tasklet((unsigned long)&ctx->context);
3492
3493 switch (base->type) {
3494 case FW_ISO_CONTEXT_TRANSMIT:
3495 case FW_ISO_CONTEXT_RECEIVE:
3496 if (ctx->header_length != 0)
3497 flush_iso_completions(ctx);
3498 break;
3499 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3500 if (ctx->mc_completed != 0)
3501 flush_ir_buffer_fill(ctx);
3502 break;
3503 default:
3504 ret = -ENOSYS;
3505 }
3506
3507 clear_bit_unlock(0, &ctx->flushing_completions);
3508 smp_mb__after_atomic();
3509 }
3510
3511 tasklet_enable(&ctx->context.tasklet);
3512
3513 return ret;
3514 }
3515
3516 static const struct fw_card_driver ohci_driver = {
3517 .enable = ohci_enable,
3518 .read_phy_reg = ohci_read_phy_reg,
3519 .update_phy_reg = ohci_update_phy_reg,
3520 .set_config_rom = ohci_set_config_rom,
3521 .send_request = ohci_send_request,
3522 .send_response = ohci_send_response,
3523 .cancel_packet = ohci_cancel_packet,
3524 .enable_phys_dma = ohci_enable_phys_dma,
3525 .read_csr = ohci_read_csr,
3526 .write_csr = ohci_write_csr,
3527
3528 .allocate_iso_context = ohci_allocate_iso_context,
3529 .free_iso_context = ohci_free_iso_context,
3530 .set_iso_channels = ohci_set_iso_channels,
3531 .queue_iso = ohci_queue_iso,
3532 .flush_queue_iso = ohci_flush_queue_iso,
3533 .flush_iso_completions = ohci_flush_iso_completions,
3534 .start_iso = ohci_start_iso,
3535 .stop_iso = ohci_stop_iso,
3536 };
3537
3538 #ifdef CONFIG_PPC_PMAC
3539 static void pmac_ohci_on(struct pci_dev *dev)
3540 {
3541 if (machine_is(powermac)) {
3542 struct device_node *ofn = pci_device_to_OF_node(dev);
3543
3544 if (ofn) {
3545 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3546 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3547 }
3548 }
3549 }
3550
3551 static void pmac_ohci_off(struct pci_dev *dev)
3552 {
3553 if (machine_is(powermac)) {
3554 struct device_node *ofn = pci_device_to_OF_node(dev);
3555
3556 if (ofn) {
3557 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3558 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3559 }
3560 }
3561 }
3562 #else
3563 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3564 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3565 #endif /* CONFIG_PPC_PMAC */
3566
3567 static int pci_probe(struct pci_dev *dev,
3568 const struct pci_device_id *ent)
3569 {
3570 struct fw_ohci *ohci;
3571 u32 bus_options, max_receive, link_speed, version;
3572 u64 guid;
3573 int i, err;
3574 size_t size;
3575
3576 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3577 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3578 return -ENOSYS;
3579 }
3580
3581 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3582 if (ohci == NULL) {
3583 err = -ENOMEM;
3584 goto fail;
3585 }
3586
3587 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3588
3589 pmac_ohci_on(dev);
3590
3591 err = pci_enable_device(dev);
3592 if (err) {
3593 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3594 goto fail_free;
3595 }
3596
3597 pci_set_master(dev);
3598 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3599 pci_set_drvdata(dev, ohci);
3600
3601 spin_lock_init(&ohci->lock);
3602 mutex_init(&ohci->phy_reg_mutex);
3603
3604 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3605
3606 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3607 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3608 ohci_err(ohci, "invalid MMIO resource\n");
3609 err = -ENXIO;
3610 goto fail_disable;
3611 }
3612
3613 err = pci_request_region(dev, 0, ohci_driver_name);
3614 if (err) {
3615 ohci_err(ohci, "MMIO resource unavailable\n");
3616 goto fail_disable;
3617 }
3618
3619 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3620 if (ohci->registers == NULL) {
3621 ohci_err(ohci, "failed to remap registers\n");
3622 err = -ENXIO;
3623 goto fail_iomem;
3624 }
3625
3626 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3627 if ((ohci_quirks[i].vendor == dev->vendor) &&
3628 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3629 ohci_quirks[i].device == dev->device) &&
3630 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3631 ohci_quirks[i].revision >= dev->revision)) {
3632 ohci->quirks = ohci_quirks[i].flags;
3633 break;
3634 }
3635 if (param_quirks)
3636 ohci->quirks = param_quirks;
3637
3638 /*
3639 * Because dma_alloc_coherent() allocates at least one page,
3640 * we save space by using a common buffer for the AR request/
3641 * response descriptors and the self IDs buffer.
3642 */
3643 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3644 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3645 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3646 PAGE_SIZE,
3647 &ohci->misc_buffer_bus,
3648 GFP_KERNEL);
3649 if (!ohci->misc_buffer) {
3650 err = -ENOMEM;
3651 goto fail_iounmap;
3652 }
3653
3654 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3655 OHCI1394_AsReqRcvContextControlSet);
3656 if (err < 0)
3657 goto fail_misc_buf;
3658
3659 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3660 OHCI1394_AsRspRcvContextControlSet);
3661 if (err < 0)
3662 goto fail_arreq_ctx;
3663
3664 err = context_init(&ohci->at_request_ctx, ohci,
3665 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3666 if (err < 0)
3667 goto fail_arrsp_ctx;
3668
3669 err = context_init(&ohci->at_response_ctx, ohci,
3670 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3671 if (err < 0)
3672 goto fail_atreq_ctx;
3673
3674 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3675 ohci->ir_context_channels = ~0ULL;
3676 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3677 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3678 ohci->ir_context_mask = ohci->ir_context_support;
3679 ohci->n_ir = hweight32(ohci->ir_context_mask);
3680 size = sizeof(struct iso_context) * ohci->n_ir;
3681 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3682
3683 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3684 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3685 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3686 ohci->it_context_mask = ohci->it_context_support;
3687 ohci->n_it = hweight32(ohci->it_context_mask);
3688 size = sizeof(struct iso_context) * ohci->n_it;
3689 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3690
3691 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3692 err = -ENOMEM;
3693 goto fail_contexts;
3694 }
3695
3696 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
3697 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3698
3699 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3700 max_receive = (bus_options >> 12) & 0xf;
3701 link_speed = bus_options & 0x7;
3702 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3703 reg_read(ohci, OHCI1394_GUIDLo);
3704
3705 if (!(ohci->quirks & QUIRK_NO_MSI))
3706 pci_enable_msi(dev);
3707 if (request_irq(dev->irq, irq_handler,
3708 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3709 ohci_driver_name, ohci)) {
3710 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3711 err = -EIO;
3712 goto fail_msi;
3713 }
3714
3715 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3716 if (err)
3717 goto fail_irq;
3718
3719 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3720 ohci_notice(ohci,
3721 "added OHCI v%x.%x device as card %d, "
3722 "%d IR + %d IT contexts, quirks 0x%x%s\n",
3723 version >> 16, version & 0xff, ohci->card.index,
3724 ohci->n_ir, ohci->n_it, ohci->quirks,
3725 reg_read(ohci, OHCI1394_PhyUpperBound) ?
3726 ", physUB" : "");
3727
3728 return 0;
3729
3730 fail_irq:
3731 free_irq(dev->irq, ohci);
3732 fail_msi:
3733 pci_disable_msi(dev);
3734 fail_contexts:
3735 kfree(ohci->ir_context_list);
3736 kfree(ohci->it_context_list);
3737 context_release(&ohci->at_response_ctx);
3738 fail_atreq_ctx:
3739 context_release(&ohci->at_request_ctx);
3740 fail_arrsp_ctx:
3741 ar_context_release(&ohci->ar_response_ctx);
3742 fail_arreq_ctx:
3743 ar_context_release(&ohci->ar_request_ctx);
3744 fail_misc_buf:
3745 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3746 ohci->misc_buffer, ohci->misc_buffer_bus);
3747 fail_iounmap:
3748 pci_iounmap(dev, ohci->registers);
3749 fail_iomem:
3750 pci_release_region(dev, 0);
3751 fail_disable:
3752 pci_disable_device(dev);
3753 fail_free:
3754 kfree(ohci);
3755 pmac_ohci_off(dev);
3756 fail:
3757 return err;
3758 }
3759
3760 static void pci_remove(struct pci_dev *dev)
3761 {
3762 struct fw_ohci *ohci = pci_get_drvdata(dev);
3763
3764 /*
3765 * If the removal is happening from the suspend state, LPS won't be
3766 * enabled and host registers (eg., IntMaskClear) won't be accessible.
3767 */
3768 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3769 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3770 flush_writes(ohci);
3771 }
3772 cancel_work_sync(&ohci->bus_reset_work);
3773 fw_core_remove_card(&ohci->card);
3774
3775 /*
3776 * FIXME: Fail all pending packets here, now that the upper
3777 * layers can't queue any more.
3778 */
3779
3780 software_reset(ohci);
3781 free_irq(dev->irq, ohci);
3782
3783 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3784 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3785 ohci->next_config_rom, ohci->next_config_rom_bus);
3786 if (ohci->config_rom)
3787 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3788 ohci->config_rom, ohci->config_rom_bus);
3789 ar_context_release(&ohci->ar_request_ctx);
3790 ar_context_release(&ohci->ar_response_ctx);
3791 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3792 ohci->misc_buffer, ohci->misc_buffer_bus);
3793 context_release(&ohci->at_request_ctx);
3794 context_release(&ohci->at_response_ctx);
3795 kfree(ohci->it_context_list);
3796 kfree(ohci->ir_context_list);
3797 pci_disable_msi(dev);
3798 pci_iounmap(dev, ohci->registers);
3799 pci_release_region(dev, 0);
3800 pci_disable_device(dev);
3801 kfree(ohci);
3802 pmac_ohci_off(dev);
3803
3804 dev_notice(&dev->dev, "removed fw-ohci device\n");
3805 }
3806
3807 #ifdef CONFIG_PM
3808 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3809 {
3810 struct fw_ohci *ohci = pci_get_drvdata(dev);
3811 int err;
3812
3813 software_reset(ohci);
3814 err = pci_save_state(dev);
3815 if (err) {
3816 ohci_err(ohci, "pci_save_state failed\n");
3817 return err;
3818 }
3819 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3820 if (err)
3821 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3822 pmac_ohci_off(dev);
3823
3824 return 0;
3825 }
3826
3827 static int pci_resume(struct pci_dev *dev)
3828 {
3829 struct fw_ohci *ohci = pci_get_drvdata(dev);
3830 int err;
3831
3832 pmac_ohci_on(dev);
3833 pci_set_power_state(dev, PCI_D0);
3834 pci_restore_state(dev);
3835 err = pci_enable_device(dev);
3836 if (err) {
3837 ohci_err(ohci, "pci_enable_device failed\n");
3838 return err;
3839 }
3840
3841 /* Some systems don't setup GUID register on resume from ram */
3842 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3843 !reg_read(ohci, OHCI1394_GUIDHi)) {
3844 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3845 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3846 }
3847
3848 err = ohci_enable(&ohci->card, NULL, 0);
3849 if (err)
3850 return err;
3851
3852 ohci_resume_iso_dma(ohci);
3853
3854 return 0;
3855 }
3856 #endif
3857
3858 static const struct pci_device_id pci_table[] = {
3859 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3860 { }
3861 };
3862
3863 MODULE_DEVICE_TABLE(pci, pci_table);
3864
3865 static struct pci_driver fw_ohci_pci_driver = {
3866 .name = ohci_driver_name,
3867 .id_table = pci_table,
3868 .probe = pci_probe,
3869 .remove = pci_remove,
3870 #ifdef CONFIG_PM
3871 .resume = pci_resume,
3872 .suspend = pci_suspend,
3873 #endif
3874 };
3875
3876 static int __init fw_ohci_init(void)
3877 {
3878 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3879 if (!selfid_workqueue)
3880 return -ENOMEM;
3881
3882 return pci_register_driver(&fw_ohci_pci_driver);
3883 }
3884
3885 static void __exit fw_ohci_cleanup(void)
3886 {
3887 pci_unregister_driver(&fw_ohci_pci_driver);
3888 destroy_workqueue(selfid_workqueue);
3889 }
3890
3891 module_init(fw_ohci_init);
3892 module_exit(fw_ohci_cleanup);
3893
3894 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3895 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3896 MODULE_LICENSE("GPL");
3897
3898 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3899 MODULE_ALIAS("ohci1394");
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