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firmware: qcom_scm: Make __qcom_scm_is_call_available() return bool
[mirror_ubuntu-hirsute-kernel.git] / drivers / firmware / qcom_scm.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
4 */
5 #include <linux/platform_device.h>
6 #include <linux/init.h>
7 #include <linux/cpumask.h>
8 #include <linux/export.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/module.h>
11 #include <linux/types.h>
12 #include <linux/qcom_scm.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/of_platform.h>
16 #include <linux/clk.h>
17 #include <linux/reset-controller.h>
18 #include <linux/arm-smccc.h>
19
20 #include "qcom_scm.h"
21
22 static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
23 module_param(download_mode, bool, 0);
24
25 #define SCM_HAS_CORE_CLK BIT(0)
26 #define SCM_HAS_IFACE_CLK BIT(1)
27 #define SCM_HAS_BUS_CLK BIT(2)
28
29 struct qcom_scm {
30 struct device *dev;
31 struct clk *core_clk;
32 struct clk *iface_clk;
33 struct clk *bus_clk;
34 struct reset_controller_dev reset;
35
36 u64 dload_mode_addr;
37 };
38
39 struct qcom_scm_current_perm_info {
40 __le32 vmid;
41 __le32 perm;
42 __le64 ctx;
43 __le32 ctx_size;
44 __le32 unused;
45 };
46
47 struct qcom_scm_mem_map_info {
48 __le64 mem_addr;
49 __le64 mem_size;
50 };
51
52 #define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
53 #define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
54 #define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
55 #define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
56
57 #define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
58 #define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
59 #define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
60 #define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
61
62 struct qcom_scm_wb_entry {
63 int flag;
64 void *entry;
65 };
66
67 static struct qcom_scm_wb_entry qcom_scm_wb[] = {
68 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
69 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
70 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
71 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
72 };
73
74 static const char *qcom_scm_convention_names[] = {
75 [SMC_CONVENTION_UNKNOWN] = "unknown",
76 [SMC_CONVENTION_ARM_32] = "smc arm 32",
77 [SMC_CONVENTION_ARM_64] = "smc arm 64",
78 [SMC_CONVENTION_LEGACY] = "smc legacy",
79 };
80
81 static struct qcom_scm *__scm;
82
83 static int qcom_scm_clk_enable(void)
84 {
85 int ret;
86
87 ret = clk_prepare_enable(__scm->core_clk);
88 if (ret)
89 goto bail;
90
91 ret = clk_prepare_enable(__scm->iface_clk);
92 if (ret)
93 goto disable_core;
94
95 ret = clk_prepare_enable(__scm->bus_clk);
96 if (ret)
97 goto disable_iface;
98
99 return 0;
100
101 disable_iface:
102 clk_disable_unprepare(__scm->iface_clk);
103 disable_core:
104 clk_disable_unprepare(__scm->core_clk);
105 bail:
106 return ret;
107 }
108
109 static void qcom_scm_clk_disable(void)
110 {
111 clk_disable_unprepare(__scm->core_clk);
112 clk_disable_unprepare(__scm->iface_clk);
113 clk_disable_unprepare(__scm->bus_clk);
114 }
115
116 enum qcom_scm_convention qcom_scm_convention;
117 static bool has_queried __read_mostly;
118 static DEFINE_SPINLOCK(query_lock);
119
120 static void __query_convention(void)
121 {
122 unsigned long flags;
123 struct qcom_scm_desc desc = {
124 .svc = QCOM_SCM_SVC_INFO,
125 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
126 .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
127 QCOM_SCM_INFO_IS_CALL_AVAIL) |
128 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
129 .arginfo = QCOM_SCM_ARGS(1),
130 .owner = ARM_SMCCC_OWNER_SIP,
131 };
132 struct qcom_scm_res res;
133 int ret;
134
135 spin_lock_irqsave(&query_lock, flags);
136 if (has_queried)
137 goto out;
138
139 qcom_scm_convention = SMC_CONVENTION_ARM_64;
140 // Device isn't required as there is only one argument - no device
141 // needed to dma_map_single to secure world
142 ret = scm_smc_call(NULL, &desc, &res, true);
143 if (!ret && res.result[0] == 1)
144 goto out;
145
146 qcom_scm_convention = SMC_CONVENTION_ARM_32;
147 ret = scm_smc_call(NULL, &desc, &res, true);
148 if (!ret && res.result[0] == 1)
149 goto out;
150
151 qcom_scm_convention = SMC_CONVENTION_LEGACY;
152 out:
153 has_queried = true;
154 spin_unlock_irqrestore(&query_lock, flags);
155 pr_info("qcom_scm: convention: %s\n",
156 qcom_scm_convention_names[qcom_scm_convention]);
157 }
158
159 static inline enum qcom_scm_convention __get_convention(void)
160 {
161 if (unlikely(!has_queried))
162 __query_convention();
163 return qcom_scm_convention;
164 }
165
166 /**
167 * qcom_scm_call() - Invoke a syscall in the secure world
168 * @dev: device
169 * @svc_id: service identifier
170 * @cmd_id: command identifier
171 * @desc: Descriptor structure containing arguments and return values
172 *
173 * Sends a command to the SCM and waits for the command to finish processing.
174 * This should *only* be called in pre-emptible context.
175 */
176 static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
177 struct qcom_scm_res *res)
178 {
179 might_sleep();
180 switch (__get_convention()) {
181 case SMC_CONVENTION_ARM_32:
182 case SMC_CONVENTION_ARM_64:
183 return scm_smc_call(dev, desc, res, false);
184 case SMC_CONVENTION_LEGACY:
185 return scm_legacy_call(dev, desc, res);
186 default:
187 pr_err("Unknown current SCM calling convention.\n");
188 return -EINVAL;
189 }
190 }
191
192 /**
193 * qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
194 * @dev: device
195 * @svc_id: service identifier
196 * @cmd_id: command identifier
197 * @desc: Descriptor structure containing arguments and return values
198 * @res: Structure containing results from SMC/HVC call
199 *
200 * Sends a command to the SCM and waits for the command to finish processing.
201 * This can be called in atomic context.
202 */
203 static int qcom_scm_call_atomic(struct device *dev,
204 const struct qcom_scm_desc *desc,
205 struct qcom_scm_res *res)
206 {
207 switch (__get_convention()) {
208 case SMC_CONVENTION_ARM_32:
209 case SMC_CONVENTION_ARM_64:
210 return scm_smc_call(dev, desc, res, true);
211 case SMC_CONVENTION_LEGACY:
212 return scm_legacy_call_atomic(dev, desc, res);
213 default:
214 pr_err("Unknown current SCM calling convention.\n");
215 return -EINVAL;
216 }
217 }
218
219 static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
220 u32 cmd_id)
221 {
222 int ret;
223 struct qcom_scm_desc desc = {
224 .svc = QCOM_SCM_SVC_INFO,
225 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
226 .owner = ARM_SMCCC_OWNER_SIP,
227 };
228 struct qcom_scm_res res;
229
230 desc.arginfo = QCOM_SCM_ARGS(1);
231 switch (__get_convention()) {
232 case SMC_CONVENTION_ARM_32:
233 case SMC_CONVENTION_ARM_64:
234 desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
235 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
236 break;
237 case SMC_CONVENTION_LEGACY:
238 desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id);
239 break;
240 default:
241 pr_err("Unknown SMC convention being used\n");
242 return -EINVAL;
243 }
244
245 ret = qcom_scm_call(dev, &desc, &res);
246
247 return ret ? false : !!res.result[0];
248 }
249
250 /**
251 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
252 * @entry: Entry point function for the cpus
253 * @cpus: The cpumask of cpus that will use the entry point
254 *
255 * Set the Linux entry point for the SCM to transfer control to when coming
256 * out of a power down. CPU power down may be executed on cpuidle or hotplug.
257 */
258 int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
259 {
260 int ret;
261 int flags = 0;
262 int cpu;
263 struct qcom_scm_desc desc = {
264 .svc = QCOM_SCM_SVC_BOOT,
265 .cmd = QCOM_SCM_BOOT_SET_ADDR,
266 .arginfo = QCOM_SCM_ARGS(2),
267 };
268
269 /*
270 * Reassign only if we are switching from hotplug entry point
271 * to cpuidle entry point or vice versa.
272 */
273 for_each_cpu(cpu, cpus) {
274 if (entry == qcom_scm_wb[cpu].entry)
275 continue;
276 flags |= qcom_scm_wb[cpu].flag;
277 }
278
279 /* No change in entry function */
280 if (!flags)
281 return 0;
282
283 desc.args[0] = flags;
284 desc.args[1] = virt_to_phys(entry);
285
286 ret = qcom_scm_call(__scm->dev, &desc, NULL);
287 if (!ret) {
288 for_each_cpu(cpu, cpus)
289 qcom_scm_wb[cpu].entry = entry;
290 }
291
292 return ret;
293 }
294 EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
295
296 /**
297 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
298 * @entry: Entry point function for the cpus
299 * @cpus: The cpumask of cpus that will use the entry point
300 *
301 * Set the cold boot address of the cpus. Any cpu outside the supported
302 * range would be removed from the cpu present mask.
303 */
304 int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
305 {
306 int flags = 0;
307 int cpu;
308 int scm_cb_flags[] = {
309 QCOM_SCM_FLAG_COLDBOOT_CPU0,
310 QCOM_SCM_FLAG_COLDBOOT_CPU1,
311 QCOM_SCM_FLAG_COLDBOOT_CPU2,
312 QCOM_SCM_FLAG_COLDBOOT_CPU3,
313 };
314 struct qcom_scm_desc desc = {
315 .svc = QCOM_SCM_SVC_BOOT,
316 .cmd = QCOM_SCM_BOOT_SET_ADDR,
317 .arginfo = QCOM_SCM_ARGS(2),
318 .owner = ARM_SMCCC_OWNER_SIP,
319 };
320
321 if (!cpus || (cpus && cpumask_empty(cpus)))
322 return -EINVAL;
323
324 for_each_cpu(cpu, cpus) {
325 if (cpu < ARRAY_SIZE(scm_cb_flags))
326 flags |= scm_cb_flags[cpu];
327 else
328 set_cpu_present(cpu, false);
329 }
330
331 desc.args[0] = flags;
332 desc.args[1] = virt_to_phys(entry);
333
334 return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
335 }
336 EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
337
338 /**
339 * qcom_scm_cpu_power_down() - Power down the cpu
340 * @flags - Flags to flush cache
341 *
342 * This is an end point to power down cpu. If there was a pending interrupt,
343 * the control would return from this function, otherwise, the cpu jumps to the
344 * warm boot entry point set for this cpu upon reset.
345 */
346 void qcom_scm_cpu_power_down(u32 flags)
347 {
348 struct qcom_scm_desc desc = {
349 .svc = QCOM_SCM_SVC_BOOT,
350 .cmd = QCOM_SCM_BOOT_TERMINATE_PC,
351 .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
352 .arginfo = QCOM_SCM_ARGS(1),
353 .owner = ARM_SMCCC_OWNER_SIP,
354 };
355
356 qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
357 }
358 EXPORT_SYMBOL(qcom_scm_cpu_power_down);
359
360 int qcom_scm_set_remote_state(u32 state, u32 id)
361 {
362 struct qcom_scm_desc desc = {
363 .svc = QCOM_SCM_SVC_BOOT,
364 .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
365 .arginfo = QCOM_SCM_ARGS(2),
366 .args[0] = state,
367 .args[1] = id,
368 .owner = ARM_SMCCC_OWNER_SIP,
369 };
370 struct qcom_scm_res res;
371 int ret;
372
373 ret = qcom_scm_call(__scm->dev, &desc, &res);
374
375 return ret ? : res.result[0];
376 }
377 EXPORT_SYMBOL(qcom_scm_set_remote_state);
378
379 static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
380 {
381 struct qcom_scm_desc desc = {
382 .svc = QCOM_SCM_SVC_BOOT,
383 .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
384 .arginfo = QCOM_SCM_ARGS(2),
385 .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE,
386 .owner = ARM_SMCCC_OWNER_SIP,
387 };
388
389 desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
390
391 return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
392 }
393
394 static void qcom_scm_set_download_mode(bool enable)
395 {
396 bool avail;
397 int ret = 0;
398
399 avail = __qcom_scm_is_call_available(__scm->dev,
400 QCOM_SCM_SVC_BOOT,
401 QCOM_SCM_BOOT_SET_DLOAD_MODE);
402 if (avail) {
403 ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
404 } else if (__scm->dload_mode_addr) {
405 ret = qcom_scm_io_writel(__scm->dload_mode_addr,
406 enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
407 } else {
408 dev_err(__scm->dev,
409 "No available mechanism for setting download mode\n");
410 }
411
412 if (ret)
413 dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
414 }
415
416 /**
417 * qcom_scm_pas_init_image() - Initialize peripheral authentication service
418 * state machine for a given peripheral, using the
419 * metadata
420 * @peripheral: peripheral id
421 * @metadata: pointer to memory containing ELF header, program header table
422 * and optional blob of data used for authenticating the metadata
423 * and the rest of the firmware
424 * @size: size of the metadata
425 *
426 * Returns 0 on success.
427 */
428 int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
429 {
430 dma_addr_t mdata_phys;
431 void *mdata_buf;
432 int ret;
433 struct qcom_scm_desc desc = {
434 .svc = QCOM_SCM_SVC_PIL,
435 .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
436 .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
437 .args[0] = peripheral,
438 .owner = ARM_SMCCC_OWNER_SIP,
439 };
440 struct qcom_scm_res res;
441
442 /*
443 * During the scm call memory protection will be enabled for the meta
444 * data blob, so make sure it's physically contiguous, 4K aligned and
445 * non-cachable to avoid XPU violations.
446 */
447 mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
448 GFP_KERNEL);
449 if (!mdata_buf) {
450 dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
451 return -ENOMEM;
452 }
453 memcpy(mdata_buf, metadata, size);
454
455 ret = qcom_scm_clk_enable();
456 if (ret)
457 goto free_metadata;
458
459 desc.args[1] = mdata_phys;
460
461 ret = qcom_scm_call(__scm->dev, &desc, &res);
462
463 qcom_scm_clk_disable();
464
465 free_metadata:
466 dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
467
468 return ret ? : res.result[0];
469 }
470 EXPORT_SYMBOL(qcom_scm_pas_init_image);
471
472 /**
473 * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
474 * for firmware loading
475 * @peripheral: peripheral id
476 * @addr: start address of memory area to prepare
477 * @size: size of the memory area to prepare
478 *
479 * Returns 0 on success.
480 */
481 int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
482 {
483 int ret;
484 struct qcom_scm_desc desc = {
485 .svc = QCOM_SCM_SVC_PIL,
486 .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
487 .arginfo = QCOM_SCM_ARGS(3),
488 .args[0] = peripheral,
489 .args[1] = addr,
490 .args[2] = size,
491 .owner = ARM_SMCCC_OWNER_SIP,
492 };
493 struct qcom_scm_res res;
494
495 ret = qcom_scm_clk_enable();
496 if (ret)
497 return ret;
498
499 ret = qcom_scm_call(__scm->dev, &desc, &res);
500 qcom_scm_clk_disable();
501
502 return ret ? : res.result[0];
503 }
504 EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
505
506 /**
507 * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
508 * and reset the remote processor
509 * @peripheral: peripheral id
510 *
511 * Return 0 on success.
512 */
513 int qcom_scm_pas_auth_and_reset(u32 peripheral)
514 {
515 int ret;
516 struct qcom_scm_desc desc = {
517 .svc = QCOM_SCM_SVC_PIL,
518 .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
519 .arginfo = QCOM_SCM_ARGS(1),
520 .args[0] = peripheral,
521 .owner = ARM_SMCCC_OWNER_SIP,
522 };
523 struct qcom_scm_res res;
524
525 ret = qcom_scm_clk_enable();
526 if (ret)
527 return ret;
528
529 ret = qcom_scm_call(__scm->dev, &desc, &res);
530 qcom_scm_clk_disable();
531
532 return ret ? : res.result[0];
533 }
534 EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
535
536 /**
537 * qcom_scm_pas_shutdown() - Shut down the remote processor
538 * @peripheral: peripheral id
539 *
540 * Returns 0 on success.
541 */
542 int qcom_scm_pas_shutdown(u32 peripheral)
543 {
544 int ret;
545 struct qcom_scm_desc desc = {
546 .svc = QCOM_SCM_SVC_PIL,
547 .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
548 .arginfo = QCOM_SCM_ARGS(1),
549 .args[0] = peripheral,
550 .owner = ARM_SMCCC_OWNER_SIP,
551 };
552 struct qcom_scm_res res;
553
554 ret = qcom_scm_clk_enable();
555 if (ret)
556 return ret;
557
558 ret = qcom_scm_call(__scm->dev, &desc, &res);
559
560 qcom_scm_clk_disable();
561
562 return ret ? : res.result[0];
563 }
564 EXPORT_SYMBOL(qcom_scm_pas_shutdown);
565
566 /**
567 * qcom_scm_pas_supported() - Check if the peripheral authentication service is
568 * available for the given peripherial
569 * @peripheral: peripheral id
570 *
571 * Returns true if PAS is supported for this peripheral, otherwise false.
572 */
573 bool qcom_scm_pas_supported(u32 peripheral)
574 {
575 int ret;
576 struct qcom_scm_desc desc = {
577 .svc = QCOM_SCM_SVC_PIL,
578 .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
579 .arginfo = QCOM_SCM_ARGS(1),
580 .args[0] = peripheral,
581 .owner = ARM_SMCCC_OWNER_SIP,
582 };
583 struct qcom_scm_res res;
584
585 if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
586 QCOM_SCM_PIL_PAS_IS_SUPPORTED))
587 return false;
588
589 ret = qcom_scm_call(__scm->dev, &desc, &res);
590
591 return ret ? false : !!res.result[0];
592 }
593 EXPORT_SYMBOL(qcom_scm_pas_supported);
594
595 static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
596 {
597 struct qcom_scm_desc desc = {
598 .svc = QCOM_SCM_SVC_PIL,
599 .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
600 .arginfo = QCOM_SCM_ARGS(2),
601 .args[0] = reset,
602 .args[1] = 0,
603 .owner = ARM_SMCCC_OWNER_SIP,
604 };
605 struct qcom_scm_res res;
606 int ret;
607
608 ret = qcom_scm_call(__scm->dev, &desc, &res);
609
610 return ret ? : res.result[0];
611 }
612
613 static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
614 unsigned long idx)
615 {
616 if (idx != 0)
617 return -EINVAL;
618
619 return __qcom_scm_pas_mss_reset(__scm->dev, 1);
620 }
621
622 static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
623 unsigned long idx)
624 {
625 if (idx != 0)
626 return -EINVAL;
627
628 return __qcom_scm_pas_mss_reset(__scm->dev, 0);
629 }
630
631 static const struct reset_control_ops qcom_scm_pas_reset_ops = {
632 .assert = qcom_scm_pas_reset_assert,
633 .deassert = qcom_scm_pas_reset_deassert,
634 };
635
636 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
637 {
638 struct qcom_scm_desc desc = {
639 .svc = QCOM_SCM_SVC_IO,
640 .cmd = QCOM_SCM_IO_READ,
641 .arginfo = QCOM_SCM_ARGS(1),
642 .args[0] = addr,
643 .owner = ARM_SMCCC_OWNER_SIP,
644 };
645 struct qcom_scm_res res;
646 int ret;
647
648
649 ret = qcom_scm_call_atomic(__scm->dev, &desc, &res);
650 if (ret >= 0)
651 *val = res.result[0];
652
653 return ret < 0 ? ret : 0;
654 }
655 EXPORT_SYMBOL(qcom_scm_io_readl);
656
657 int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
658 {
659 struct qcom_scm_desc desc = {
660 .svc = QCOM_SCM_SVC_IO,
661 .cmd = QCOM_SCM_IO_WRITE,
662 .arginfo = QCOM_SCM_ARGS(2),
663 .args[0] = addr,
664 .args[1] = val,
665 .owner = ARM_SMCCC_OWNER_SIP,
666 };
667
668 return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
669 }
670 EXPORT_SYMBOL(qcom_scm_io_writel);
671
672 /**
673 * qcom_scm_restore_sec_cfg_available() - Check if secure environment
674 * supports restore security config interface.
675 *
676 * Return true if restore-cfg interface is supported, false if not.
677 */
678 bool qcom_scm_restore_sec_cfg_available(void)
679 {
680 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
681 QCOM_SCM_MP_RESTORE_SEC_CFG);
682 }
683 EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);
684
685 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
686 {
687 struct qcom_scm_desc desc = {
688 .svc = QCOM_SCM_SVC_MP,
689 .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
690 .arginfo = QCOM_SCM_ARGS(2),
691 .args[0] = device_id,
692 .args[1] = spare,
693 .owner = ARM_SMCCC_OWNER_SIP,
694 };
695 struct qcom_scm_res res;
696 int ret;
697
698 ret = qcom_scm_call(__scm->dev, &desc, &res);
699
700 return ret ? : res.result[0];
701 }
702 EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
703
704 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
705 {
706 struct qcom_scm_desc desc = {
707 .svc = QCOM_SCM_SVC_MP,
708 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
709 .arginfo = QCOM_SCM_ARGS(1),
710 .args[0] = spare,
711 .owner = ARM_SMCCC_OWNER_SIP,
712 };
713 struct qcom_scm_res res;
714 int ret;
715
716 ret = qcom_scm_call(__scm->dev, &desc, &res);
717
718 if (size)
719 *size = res.result[0];
720
721 return ret ? : res.result[1];
722 }
723 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
724
725 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
726 {
727 struct qcom_scm_desc desc = {
728 .svc = QCOM_SCM_SVC_MP,
729 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
730 .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
731 QCOM_SCM_VAL),
732 .args[0] = addr,
733 .args[1] = size,
734 .args[2] = spare,
735 .owner = ARM_SMCCC_OWNER_SIP,
736 };
737 int ret;
738
739 desc.args[0] = addr;
740 desc.args[1] = size;
741 desc.args[2] = spare;
742 desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
743 QCOM_SCM_VAL);
744
745 ret = qcom_scm_call(__scm->dev, &desc, NULL);
746
747 /* the pg table has been initialized already, ignore the error */
748 if (ret == -EPERM)
749 ret = 0;
750
751 return ret;
752 }
753 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
754
755 int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
756 u32 cp_nonpixel_start,
757 u32 cp_nonpixel_size)
758 {
759 int ret;
760 struct qcom_scm_desc desc = {
761 .svc = QCOM_SCM_SVC_MP,
762 .cmd = QCOM_SCM_MP_VIDEO_VAR,
763 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL,
764 QCOM_SCM_VAL, QCOM_SCM_VAL),
765 .args[0] = cp_start,
766 .args[1] = cp_size,
767 .args[2] = cp_nonpixel_start,
768 .args[3] = cp_nonpixel_size,
769 .owner = ARM_SMCCC_OWNER_SIP,
770 };
771 struct qcom_scm_res res;
772
773 ret = qcom_scm_call(__scm->dev, &desc, &res);
774
775 return ret ? : res.result[0];
776 }
777 EXPORT_SYMBOL(qcom_scm_mem_protect_video_var);
778
779 static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
780 size_t mem_sz, phys_addr_t src, size_t src_sz,
781 phys_addr_t dest, size_t dest_sz)
782 {
783 int ret;
784 struct qcom_scm_desc desc = {
785 .svc = QCOM_SCM_SVC_MP,
786 .cmd = QCOM_SCM_MP_ASSIGN,
787 .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
788 QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
789 QCOM_SCM_VAL, QCOM_SCM_VAL),
790 .args[0] = mem_region,
791 .args[1] = mem_sz,
792 .args[2] = src,
793 .args[3] = src_sz,
794 .args[4] = dest,
795 .args[5] = dest_sz,
796 .args[6] = 0,
797 .owner = ARM_SMCCC_OWNER_SIP,
798 };
799 struct qcom_scm_res res;
800
801 ret = qcom_scm_call(dev, &desc, &res);
802
803 return ret ? : res.result[0];
804 }
805
806 /**
807 * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
808 * @mem_addr: mem region whose ownership need to be reassigned
809 * @mem_sz: size of the region.
810 * @srcvm: vmid for current set of owners, each set bit in
811 * flag indicate a unique owner
812 * @newvm: array having new owners and corresponding permission
813 * flags
814 * @dest_cnt: number of owners in next set.
815 *
816 * Return negative errno on failure or 0 on success with @srcvm updated.
817 */
818 int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
819 unsigned int *srcvm,
820 const struct qcom_scm_vmperm *newvm,
821 unsigned int dest_cnt)
822 {
823 struct qcom_scm_current_perm_info *destvm;
824 struct qcom_scm_mem_map_info *mem_to_map;
825 phys_addr_t mem_to_map_phys;
826 phys_addr_t dest_phys;
827 dma_addr_t ptr_phys;
828 size_t mem_to_map_sz;
829 size_t dest_sz;
830 size_t src_sz;
831 size_t ptr_sz;
832 int next_vm;
833 __le32 *src;
834 void *ptr;
835 int ret, i, b;
836 unsigned long srcvm_bits = *srcvm;
837
838 src_sz = hweight_long(srcvm_bits) * sizeof(*src);
839 mem_to_map_sz = sizeof(*mem_to_map);
840 dest_sz = dest_cnt * sizeof(*destvm);
841 ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
842 ALIGN(dest_sz, SZ_64);
843
844 ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
845 if (!ptr)
846 return -ENOMEM;
847
848 /* Fill source vmid detail */
849 src = ptr;
850 i = 0;
851 for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG)
852 src[i++] = cpu_to_le32(b);
853
854 /* Fill details of mem buff to map */
855 mem_to_map = ptr + ALIGN(src_sz, SZ_64);
856 mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
857 mem_to_map->mem_addr = cpu_to_le64(mem_addr);
858 mem_to_map->mem_size = cpu_to_le64(mem_sz);
859
860 next_vm = 0;
861 /* Fill details of next vmid detail */
862 destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
863 dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
864 for (i = 0; i < dest_cnt; i++, destvm++, newvm++) {
865 destvm->vmid = cpu_to_le32(newvm->vmid);
866 destvm->perm = cpu_to_le32(newvm->perm);
867 destvm->ctx = 0;
868 destvm->ctx_size = 0;
869 next_vm |= BIT(newvm->vmid);
870 }
871
872 ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
873 ptr_phys, src_sz, dest_phys, dest_sz);
874 dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys);
875 if (ret) {
876 dev_err(__scm->dev,
877 "Assign memory protection call failed %d\n", ret);
878 return -EINVAL;
879 }
880
881 *srcvm = next_vm;
882 return 0;
883 }
884 EXPORT_SYMBOL(qcom_scm_assign_mem);
885
886 /**
887 * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
888 */
889 bool qcom_scm_ocmem_lock_available(void)
890 {
891 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
892 QCOM_SCM_OCMEM_LOCK_CMD);
893 }
894 EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
895
896 /**
897 * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
898 * region to the specified initiator
899 *
900 * @id: tz initiator id
901 * @offset: OCMEM offset
902 * @size: OCMEM size
903 * @mode: access mode (WIDE/NARROW)
904 */
905 int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
906 u32 mode)
907 {
908 struct qcom_scm_desc desc = {
909 .svc = QCOM_SCM_SVC_OCMEM,
910 .cmd = QCOM_SCM_OCMEM_LOCK_CMD,
911 .args[0] = id,
912 .args[1] = offset,
913 .args[2] = size,
914 .args[3] = mode,
915 .arginfo = QCOM_SCM_ARGS(4),
916 };
917
918 return qcom_scm_call(__scm->dev, &desc, NULL);
919 }
920 EXPORT_SYMBOL(qcom_scm_ocmem_lock);
921
922 /**
923 * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
924 * region from the specified initiator
925 *
926 * @id: tz initiator id
927 * @offset: OCMEM offset
928 * @size: OCMEM size
929 */
930 int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
931 {
932 struct qcom_scm_desc desc = {
933 .svc = QCOM_SCM_SVC_OCMEM,
934 .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
935 .args[0] = id,
936 .args[1] = offset,
937 .args[2] = size,
938 .arginfo = QCOM_SCM_ARGS(3),
939 };
940
941 return qcom_scm_call(__scm->dev, &desc, NULL);
942 }
943 EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
944
945 /**
946 * qcom_scm_ice_available() - Is the ICE key programming interface available?
947 *
948 * Return: true iff the SCM calls wrapped by qcom_scm_ice_invalidate_key() and
949 * qcom_scm_ice_set_key() are available.
950 */
951 bool qcom_scm_ice_available(void)
952 {
953 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
954 QCOM_SCM_ES_INVALIDATE_ICE_KEY) &&
955 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
956 QCOM_SCM_ES_CONFIG_SET_ICE_KEY);
957 }
958 EXPORT_SYMBOL(qcom_scm_ice_available);
959
960 /**
961 * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key
962 * @index: the keyslot to invalidate
963 *
964 * The UFSHCI standard defines a standard way to do this, but it doesn't work on
965 * these SoCs; only this SCM call does.
966 *
967 * Return: 0 on success; -errno on failure.
968 */
969 int qcom_scm_ice_invalidate_key(u32 index)
970 {
971 struct qcom_scm_desc desc = {
972 .svc = QCOM_SCM_SVC_ES,
973 .cmd = QCOM_SCM_ES_INVALIDATE_ICE_KEY,
974 .arginfo = QCOM_SCM_ARGS(1),
975 .args[0] = index,
976 .owner = ARM_SMCCC_OWNER_SIP,
977 };
978
979 return qcom_scm_call(__scm->dev, &desc, NULL);
980 }
981 EXPORT_SYMBOL(qcom_scm_ice_invalidate_key);
982
983 /**
984 * qcom_scm_ice_set_key() - Set an inline encryption key
985 * @index: the keyslot into which to set the key
986 * @key: the key to program
987 * @key_size: the size of the key in bytes
988 * @cipher: the encryption algorithm the key is for
989 * @data_unit_size: the encryption data unit size, i.e. the size of each
990 * individual plaintext and ciphertext. Given in 512-byte
991 * units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc.
992 *
993 * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it
994 * can then be used to encrypt/decrypt UFS I/O requests inline.
995 *
996 * The UFSHCI standard defines a standard way to do this, but it doesn't work on
997 * these SoCs; only this SCM call does.
998 *
999 * Return: 0 on success; -errno on failure.
1000 */
1001 int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
1002 enum qcom_scm_ice_cipher cipher, u32 data_unit_size)
1003 {
1004 struct qcom_scm_desc desc = {
1005 .svc = QCOM_SCM_SVC_ES,
1006 .cmd = QCOM_SCM_ES_CONFIG_SET_ICE_KEY,
1007 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RW,
1008 QCOM_SCM_VAL, QCOM_SCM_VAL,
1009 QCOM_SCM_VAL),
1010 .args[0] = index,
1011 .args[2] = key_size,
1012 .args[3] = cipher,
1013 .args[4] = data_unit_size,
1014 .owner = ARM_SMCCC_OWNER_SIP,
1015 };
1016 void *keybuf;
1017 dma_addr_t key_phys;
1018 int ret;
1019
1020 /*
1021 * 'key' may point to vmalloc()'ed memory, but we need to pass a
1022 * physical address that's been properly flushed. The sanctioned way to
1023 * do this is by using the DMA API. But as is best practice for crypto
1024 * keys, we also must wipe the key after use. This makes kmemdup() +
1025 * dma_map_single() not clearly correct, since the DMA API can use
1026 * bounce buffers. Instead, just use dma_alloc_coherent(). Programming
1027 * keys is normally rare and thus not performance-critical.
1028 */
1029
1030 keybuf = dma_alloc_coherent(__scm->dev, key_size, &key_phys,
1031 GFP_KERNEL);
1032 if (!keybuf)
1033 return -ENOMEM;
1034 memcpy(keybuf, key, key_size);
1035 desc.args[1] = key_phys;
1036
1037 ret = qcom_scm_call(__scm->dev, &desc, NULL);
1038
1039 memzero_explicit(keybuf, key_size);
1040
1041 dma_free_coherent(__scm->dev, key_size, keybuf, key_phys);
1042 return ret;
1043 }
1044 EXPORT_SYMBOL(qcom_scm_ice_set_key);
1045
1046 /**
1047 * qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
1048 *
1049 * Return true if HDCP is supported, false if not.
1050 */
1051 bool qcom_scm_hdcp_available(void)
1052 {
1053 bool avail;
1054 int ret = qcom_scm_clk_enable();
1055
1056 if (ret)
1057 return ret;
1058
1059 avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
1060 QCOM_SCM_HDCP_INVOKE);
1061
1062 qcom_scm_clk_disable();
1063
1064 return avail;
1065 }
1066 EXPORT_SYMBOL(qcom_scm_hdcp_available);
1067
1068 /**
1069 * qcom_scm_hdcp_req() - Send HDCP request.
1070 * @req: HDCP request array
1071 * @req_cnt: HDCP request array count
1072 * @resp: response buffer passed to SCM
1073 *
1074 * Write HDCP register(s) through SCM.
1075 */
1076 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
1077 {
1078 int ret;
1079 struct qcom_scm_desc desc = {
1080 .svc = QCOM_SCM_SVC_HDCP,
1081 .cmd = QCOM_SCM_HDCP_INVOKE,
1082 .arginfo = QCOM_SCM_ARGS(10),
1083 .args = {
1084 req[0].addr,
1085 req[0].val,
1086 req[1].addr,
1087 req[1].val,
1088 req[2].addr,
1089 req[2].val,
1090 req[3].addr,
1091 req[3].val,
1092 req[4].addr,
1093 req[4].val
1094 },
1095 .owner = ARM_SMCCC_OWNER_SIP,
1096 };
1097 struct qcom_scm_res res;
1098
1099 if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
1100 return -ERANGE;
1101
1102 ret = qcom_scm_clk_enable();
1103 if (ret)
1104 return ret;
1105
1106 ret = qcom_scm_call(__scm->dev, &desc, &res);
1107 *resp = res.result[0];
1108
1109 qcom_scm_clk_disable();
1110
1111 return ret;
1112 }
1113 EXPORT_SYMBOL(qcom_scm_hdcp_req);
1114
1115 int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
1116 {
1117 struct qcom_scm_desc desc = {
1118 .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
1119 .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
1120 .arginfo = QCOM_SCM_ARGS(2),
1121 .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL,
1122 .args[1] = en,
1123 .owner = ARM_SMCCC_OWNER_SIP,
1124 };
1125
1126
1127 return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
1128 }
1129 EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
1130
1131 static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
1132 {
1133 struct device_node *tcsr;
1134 struct device_node *np = dev->of_node;
1135 struct resource res;
1136 u32 offset;
1137 int ret;
1138
1139 tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
1140 if (!tcsr)
1141 return 0;
1142
1143 ret = of_address_to_resource(tcsr, 0, &res);
1144 of_node_put(tcsr);
1145 if (ret)
1146 return ret;
1147
1148 ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
1149 if (ret < 0)
1150 return ret;
1151
1152 *addr = res.start + offset;
1153
1154 return 0;
1155 }
1156
1157 /**
1158 * qcom_scm_is_available() - Checks if SCM is available
1159 */
1160 bool qcom_scm_is_available(void)
1161 {
1162 return !!__scm;
1163 }
1164 EXPORT_SYMBOL(qcom_scm_is_available);
1165
1166 static int qcom_scm_probe(struct platform_device *pdev)
1167 {
1168 struct qcom_scm *scm;
1169 unsigned long clks;
1170 int ret;
1171
1172 scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
1173 if (!scm)
1174 return -ENOMEM;
1175
1176 ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
1177 if (ret < 0)
1178 return ret;
1179
1180 clks = (unsigned long)of_device_get_match_data(&pdev->dev);
1181
1182 scm->core_clk = devm_clk_get(&pdev->dev, "core");
1183 if (IS_ERR(scm->core_clk)) {
1184 if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
1185 return PTR_ERR(scm->core_clk);
1186
1187 if (clks & SCM_HAS_CORE_CLK) {
1188 dev_err(&pdev->dev, "failed to acquire core clk\n");
1189 return PTR_ERR(scm->core_clk);
1190 }
1191
1192 scm->core_clk = NULL;
1193 }
1194
1195 scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
1196 if (IS_ERR(scm->iface_clk)) {
1197 if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
1198 return PTR_ERR(scm->iface_clk);
1199
1200 if (clks & SCM_HAS_IFACE_CLK) {
1201 dev_err(&pdev->dev, "failed to acquire iface clk\n");
1202 return PTR_ERR(scm->iface_clk);
1203 }
1204
1205 scm->iface_clk = NULL;
1206 }
1207
1208 scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
1209 if (IS_ERR(scm->bus_clk)) {
1210 if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
1211 return PTR_ERR(scm->bus_clk);
1212
1213 if (clks & SCM_HAS_BUS_CLK) {
1214 dev_err(&pdev->dev, "failed to acquire bus clk\n");
1215 return PTR_ERR(scm->bus_clk);
1216 }
1217
1218 scm->bus_clk = NULL;
1219 }
1220
1221 scm->reset.ops = &qcom_scm_pas_reset_ops;
1222 scm->reset.nr_resets = 1;
1223 scm->reset.of_node = pdev->dev.of_node;
1224 ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
1225 if (ret)
1226 return ret;
1227
1228 /* vote for max clk rate for highest performance */
1229 ret = clk_set_rate(scm->core_clk, INT_MAX);
1230 if (ret)
1231 return ret;
1232
1233 __scm = scm;
1234 __scm->dev = &pdev->dev;
1235
1236 __query_convention();
1237
1238 /*
1239 * If requested enable "download mode", from this point on warmboot
1240 * will cause the the boot stages to enter download mode, unless
1241 * disabled below by a clean shutdown/reboot.
1242 */
1243 if (download_mode)
1244 qcom_scm_set_download_mode(true);
1245
1246 return 0;
1247 }
1248
1249 static void qcom_scm_shutdown(struct platform_device *pdev)
1250 {
1251 /* Clean shutdown, disable download mode to allow normal restart */
1252 if (download_mode)
1253 qcom_scm_set_download_mode(false);
1254 }
1255
1256 static const struct of_device_id qcom_scm_dt_match[] = {
1257 { .compatible = "qcom,scm-apq8064",
1258 /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
1259 },
1260 { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
1261 SCM_HAS_IFACE_CLK |
1262 SCM_HAS_BUS_CLK)
1263 },
1264 { .compatible = "qcom,scm-ipq4019" },
1265 { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
1266 { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
1267 { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
1268 SCM_HAS_IFACE_CLK |
1269 SCM_HAS_BUS_CLK)
1270 },
1271 { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
1272 SCM_HAS_IFACE_CLK |
1273 SCM_HAS_BUS_CLK)
1274 },
1275 { .compatible = "qcom,scm-msm8994" },
1276 { .compatible = "qcom,scm-msm8996" },
1277 { .compatible = "qcom,scm" },
1278 {}
1279 };
1280
1281 static struct platform_driver qcom_scm_driver = {
1282 .driver = {
1283 .name = "qcom_scm",
1284 .of_match_table = qcom_scm_dt_match,
1285 },
1286 .probe = qcom_scm_probe,
1287 .shutdown = qcom_scm_shutdown,
1288 };
1289
1290 static int __init qcom_scm_init(void)
1291 {
1292 return platform_driver_register(&qcom_scm_driver);
1293 }
1294 subsys_initcall(qcom_scm_init);
Ubuntu Hirsute Linux kernel mirror