drivers/firmware/qcom_scm.h

   1 /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12 #ifndef __QCOM_SCM_INT_H
  13 #define __QCOM_SCM_INT_H
  14
  15 #define QCOM_SCM_SVC_BOOT               0x1
  16 #define QCOM_SCM_BOOT_ADDR              0x1
  17 #define QCOM_SCM_SET_DLOAD_MODE         0x10
  18 #define QCOM_SCM_BOOT_ADDR_MC           0x11
  19 #define QCOM_SCM_SET_REMOTE_STATE       0xa
  20 extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
  21 extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
  22
  23 #define QCOM_SCM_FLAG_HLOS              0x01
  24 #define QCOM_SCM_FLAG_COLDBOOT_MC       0x02
  25 #define QCOM_SCM_FLAG_WARMBOOT_MC       0x04
  26 extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
  27                 const cpumask_t *cpus);
  28 extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
  29
  30 #define QCOM_SCM_CMD_TERMINATE_PC       0x2
  31 #define QCOM_SCM_FLUSH_FLAG_MASK        0x3
  32 #define QCOM_SCM_CMD_CORE_HOTPLUGGED    0x10
  33 extern void __qcom_scm_cpu_power_down(u32 flags);
  34
  35 #define QCOM_SCM_SVC_IO                 0x5
  36 #define QCOM_SCM_IO_READ                0x1
  37 #define QCOM_SCM_IO_WRITE               0x2
  38 extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
  39 extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
  40
  41 #define QCOM_SCM_SVC_INFO               0x6
  42 #define QCOM_IS_CALL_AVAIL_CMD          0x1
  43 extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
  44                 u32 cmd_id);
  45
  46 #define QCOM_SCM_SVC_HDCP               0x11
  47 #define QCOM_SCM_CMD_HDCP               0x01
  48 extern int __qcom_scm_hdcp_req(struct device *dev,
  49                 struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
  50
  51 extern void __qcom_scm_init(void);
  52
  53 #define QCOM_SCM_SVC_PIL                0x2
  54 #define QCOM_SCM_PAS_INIT_IMAGE_CMD     0x1
  55 #define QCOM_SCM_PAS_MEM_SETUP_CMD      0x2
  56 #define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5
  57 #define QCOM_SCM_PAS_SHUTDOWN_CMD       0x6
  58 #define QCOM_SCM_PAS_IS_SUPPORTED_CMD   0x7
  59 #define QCOM_SCM_PAS_MSS_RESET          0xa
  60 extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
  61 extern int  __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
  62                 dma_addr_t metadata_phys);
  63 extern int  __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
  64                 phys_addr_t addr, phys_addr_t size);
  65 extern int  __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
  66 extern int  __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
  67 extern int  __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
  68
  69 /* common error codes */
  70 #define QCOM_SCM_V2_EBUSY       -12
  71 #define QCOM_SCM_ENOMEM         -5
  72 #define QCOM_SCM_EOPNOTSUPP     -4
  73 #define QCOM_SCM_EINVAL_ADDR    -3
  74 #define QCOM_SCM_EINVAL_ARG     -2
  75 #define QCOM_SCM_ERROR          -1
  76 #define QCOM_SCM_INTERRUPTED    1
  77
  78 static inline int qcom_scm_remap_error(int err)
  79 {
  80         switch (err) {
  81         case QCOM_SCM_ERROR:
  82                 return -EIO;
  83         case QCOM_SCM_EINVAL_ADDR:
  84         case QCOM_SCM_EINVAL_ARG:
  85                 return -EINVAL;
  86         case QCOM_SCM_EOPNOTSUPP:
  87                 return -EOPNOTSUPP;
  88         case QCOM_SCM_ENOMEM:
  89                 return -ENOMEM;
  90         case QCOM_SCM_V2_EBUSY:
  91                 return -EBUSY;
  92         }
  93         return -EINVAL;
  94 }
  95
  96 #define QCOM_SCM_SVC_MP                 0xc
  97 #define QCOM_SCM_RESTORE_SEC_CFG        2
  98 extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
  99                                       u32 spare);
 100 #define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE 3
 101 #define QCOM_SCM_IOMMU_SECURE_PTBL_INIT 4
 102 extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
 103                                              size_t *size);
 104 extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
 105                                              u32 size, u32 spare);
 106 #define QCOM_MEM_PROT_ASSIGN_ID 0x16
 107 extern int  __qcom_scm_assign_mem(struct device *dev,
 108                                   phys_addr_t mem_region, size_t mem_sz,
 109                                   phys_addr_t src, size_t src_sz,
 110                                   phys_addr_t dest, size_t dest_sz);
 111
 112 #endif