drivers/fpga/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 #
   3 # FPGA framework configuration
   4 #
   5
   6 menuconfig FPGA
   7         tristate "FPGA Configuration Framework"
   8         help
   9           Say Y here if you want support for configuring FPGAs from the
  10           kernel.  The FPGA framework adds a FPGA manager class and FPGA
  11           manager drivers.
  12
  13 if FPGA
  14
  15 config FPGA_MGR_SOCFPGA
  16         tristate "Altera SOCFPGA FPGA Manager"
  17         depends on ARCH_SOCFPGA || COMPILE_TEST
  18         help
  19           FPGA manager driver support for Altera SOCFPGA.
  20
  21 config FPGA_MGR_SOCFPGA_A10
  22         tristate "Altera SoCFPGA Arria10"
  23         depends on ARCH_SOCFPGA || COMPILE_TEST
  24         select REGMAP_MMIO
  25         help
  26           FPGA manager driver support for Altera Arria10 SoCFPGA.
  27
  28 config ALTERA_PR_IP_CORE
  29         tristate "Altera Partial Reconfiguration IP Core"
  30         help
  31           Core driver support for Altera Partial Reconfiguration IP component
  32
  33 config ALTERA_PR_IP_CORE_PLAT
  34         tristate "Platform support of Altera Partial Reconfiguration IP Core"
  35         depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
  36         help
  37           Platform driver support for Altera Partial Reconfiguration IP
  38           component
  39
  40 config FPGA_MGR_ALTERA_PS_SPI
  41         tristate "Altera FPGA Passive Serial over SPI"
  42         depends on SPI
  43         select BITREVERSE
  44         help
  45           FPGA manager driver support for Altera Arria/Cyclone/Stratix
  46           using the passive serial interface over SPI.
  47
  48 config FPGA_MGR_ALTERA_CVP
  49         tristate "Altera CvP FPGA Manager"
  50         depends on PCI
  51         help
  52           FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
  53           Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
  54
  55 config FPGA_MGR_ZYNQ_FPGA
  56         tristate "Xilinx Zynq FPGA"
  57         depends on ARCH_ZYNQ || COMPILE_TEST
  58         help
  59           FPGA manager driver support for Xilinx Zynq FPGAs.
  60
  61 config FPGA_MGR_STRATIX10_SOC
  62         tristate "Intel Stratix10 SoC FPGA Manager"
  63         depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
  64         help
  65           FPGA manager driver support for the Intel Stratix10 SoC.
  66
  67 config FPGA_MGR_XILINX_SPI
  68         tristate "Xilinx Configuration over Slave Serial (SPI)"
  69         depends on SPI
  70         help
  71           FPGA manager driver support for Xilinx FPGA configuration
  72           over slave serial interface.
  73
  74 config FPGA_MGR_ICE40_SPI
  75         tristate "Lattice iCE40 SPI"
  76         depends on OF && SPI
  77         help
  78           FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
  79
  80 config FPGA_MGR_MACHXO2_SPI
  81         tristate "Lattice MachXO2 SPI"
  82         depends on SPI
  83         help
  84           FPGA manager driver support for Lattice MachXO2 configuration
  85           over slave SPI interface.
  86
  87 config FPGA_MGR_TS73XX
  88         tristate "Technologic Systems TS-73xx SBC FPGA Manager"
  89         depends on ARCH_EP93XX && MACH_TS72XX
  90         help
  91           FPGA manager driver support for the Altera Cyclone II FPGA
  92           present on the TS-73xx SBC boards.
  93
  94 config FPGA_BRIDGE
  95         tristate "FPGA Bridge Framework"
  96         help
  97           Say Y here if you want to support bridges connected between host
  98           processors and FPGAs or between FPGAs.
  99
 100 config SOCFPGA_FPGA_BRIDGE
 101         tristate "Altera SoCFPGA FPGA Bridges"
 102         depends on ARCH_SOCFPGA && FPGA_BRIDGE
 103         help
 104           Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
 105           devices.
 106
 107 config ALTERA_FREEZE_BRIDGE
 108         tristate "Altera FPGA Freeze Bridge"
 109         depends on FPGA_BRIDGE && HAS_IOMEM
 110         help
 111           Say Y to enable drivers for Altera FPGA Freeze bridges.  A
 112           freeze bridge is a bridge that exists in the FPGA fabric to
 113           isolate one region of the FPGA from the busses while that
 114           region is being reprogrammed.
 115
 116 config XILINX_PR_DECOUPLER
 117         tristate "Xilinx LogiCORE PR Decoupler"
 118         depends on FPGA_BRIDGE
 119         depends on HAS_IOMEM
 120         help
 121           Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
 122           The PR Decoupler exists in the FPGA fabric to isolate one
 123           region of the FPGA from the busses while that region is
 124           being reprogrammed during partial reconfig.
 125
 126 config FPGA_REGION
 127         tristate "FPGA Region"
 128         depends on FPGA_BRIDGE
 129         help
 130           FPGA Region common code.  A FPGA Region controls a FPGA Manager
 131           and the FPGA Bridges associated with either a reconfigurable
 132           region of an FPGA or a whole FPGA.
 133
 134 config OF_FPGA_REGION
 135         tristate "FPGA Region Device Tree Overlay Support"
 136         depends on OF && FPGA_REGION
 137         help
 138           Support for loading FPGA images by applying a Device Tree
 139           overlay.
 140
 141 config FPGA_DFL
 142         tristate "FPGA Device Feature List (DFL) support"
 143         select FPGA_BRIDGE
 144         select FPGA_REGION
 145         help
 146           Device Feature List (DFL) defines a feature list structure that
 147           creates a linked list of feature headers within the MMIO space
 148           to provide an extensible way of adding features for FPGA.
 149           Driver can walk through the feature headers to enumerate feature
 150           devices (e.g. FPGA Management Engine, Port and Accelerator
 151           Function Unit) and their private features for target FPGA devices.
 152
 153           Select this option to enable common support for Field-Programmable
 154           Gate Array (FPGA) solutions which implement Device Feature List.
 155           It provides enumeration APIs and feature device infrastructure.
 156
 157 config FPGA_DFL_FME
 158         tristate "FPGA DFL FME Driver"
 159         depends on FPGA_DFL && HWMON && PERF_EVENTS
 160         help
 161           The FPGA Management Engine (FME) is a feature device implemented
 162           under Device Feature List (DFL) framework. Select this option to
 163           enable the platform device driver for FME which implements all
 164           FPGA platform level management features. There shall be one FME
 165           per DFL based FPGA device.
 166
 167 config FPGA_DFL_FME_MGR
 168         tristate "FPGA DFL FME Manager Driver"
 169         depends on FPGA_DFL_FME && HAS_IOMEM
 170         help
 171           Say Y to enable FPGA Manager driver for FPGA Management Engine.
 172
 173 config FPGA_DFL_FME_BRIDGE
 174         tristate "FPGA DFL FME Bridge Driver"
 175         depends on FPGA_DFL_FME && HAS_IOMEM
 176         help
 177           Say Y to enable FPGA Bridge driver for FPGA Management Engine.
 178
 179 config FPGA_DFL_FME_REGION
 180         tristate "FPGA DFL FME Region Driver"
 181         depends on FPGA_DFL_FME && HAS_IOMEM
 182         help
 183           Say Y to enable FPGA Region driver for FPGA Management Engine.
 184
 185 config FPGA_DFL_AFU
 186         tristate "FPGA DFL AFU Driver"
 187         depends on FPGA_DFL
 188         help
 189           This is the driver for FPGA Accelerated Function Unit (AFU) which
 190           implements AFU and Port management features. A User AFU connects
 191           to the FPGA infrastructure via a Port. There may be more than one
 192           Port/AFU per DFL based FPGA device.
 193
 194 config FPGA_DFL_PCI
 195         tristate "FPGA DFL PCIe Device Driver"
 196         depends on PCI && FPGA_DFL
 197         help
 198           Select this option to enable PCIe driver for PCIe-based
 199           Field-Programmable Gate Array (FPGA) solutions which implement
 200           the Device Feature List (DFL). This driver provides interfaces
 201           for userspace applications to configure, enumerate, open and access
 202           FPGA accelerators on the FPGA DFL devices, enables system level
 203           management functions such as FPGA partial reconfiguration, power
 204           management and virtualization with DFL framework and DFL feature
 205           device drivers.
 206
 207           To compile this as a module, choose M here.
 208
 209 config FPGA_MGR_ZYNQMP_FPGA
 210         tristate "Xilinx ZynqMP FPGA"
 211         depends on ARCH_ZYNQMP || COMPILE_TEST
 212         help
 213           FPGA manager driver support for Xilinx ZynqMP FPGAs.
 214           This driver uses the processor configuration port(PCAP)
 215           to configure the programmable logic(PL) through PS
 216           on ZynqMP SoC.
 217
 218 endif # FPGA