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1 #
2 # FPGA framework configuration
3 #
4
5 menu "FPGA Configuration Support"
6
7 config FPGA
8 tristate "FPGA Configuration Framework"
9 help
10 Say Y here if you want support for configuring FPGAs from the
11 kernel. The FPGA framework adds a FPGA manager class and FPGA
12 manager drivers.
13
14 if FPGA
15
16 config FPGA_REGION
17 tristate "FPGA Region"
18 depends on OF && FPGA_BRIDGE
19 help
20 FPGA Regions allow loading FPGA images under control of
21 the Device Tree.
22
23 config FPGA_MGR_ICE40_SPI
24 tristate "Lattice iCE40 SPI"
25 depends on OF && SPI
26 help
27 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
28
29 config FPGA_MGR_SOCFPGA
30 tristate "Altera SOCFPGA FPGA Manager"
31 depends on ARCH_SOCFPGA || COMPILE_TEST
32 help
33 FPGA manager driver support for Altera SOCFPGA.
34
35 config FPGA_MGR_SOCFPGA_A10
36 tristate "Altera SoCFPGA Arria10"
37 depends on ARCH_SOCFPGA || COMPILE_TEST
38 select REGMAP_MMIO
39 help
40 FPGA manager driver support for Altera Arria10 SoCFPGA.
41
42 config FPGA_MGR_TS73XX
43 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
44 depends on ARCH_EP93XX && MACH_TS72XX
45 help
46 FPGA manager driver support for the Altera Cyclone II FPGA
47 present on the TS-73xx SBC boards.
48
49 config FPGA_MGR_ZYNQ_FPGA
50 tristate "Xilinx Zynq FPGA"
51 depends on ARCH_ZYNQ || COMPILE_TEST
52 depends on HAS_DMA
53 help
54 FPGA manager driver support for Xilinx Zynq FPGAs.
55
56 config FPGA_BRIDGE
57 tristate "FPGA Bridge Framework"
58 depends on OF
59 help
60 Say Y here if you want to support bridges connected between host
61 processors and FPGAs or between FPGAs.
62
63 config SOCFPGA_FPGA_BRIDGE
64 tristate "Altera SoCFPGA FPGA Bridges"
65 depends on ARCH_SOCFPGA && FPGA_BRIDGE
66 help
67 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
68 devices.
69
70 config ALTERA_FREEZE_BRIDGE
71 tristate "Altera FPGA Freeze Bridge"
72 depends on ARCH_SOCFPGA && FPGA_BRIDGE
73 help
74 Say Y to enable drivers for Altera FPGA Freeze bridges. A
75 freeze bridge is a bridge that exists in the FPGA fabric to
76 isolate one region of the FPGA from the busses while that
77 region is being reprogrammed.
78
79 endif # FPGA
80
81 endmenu