drivers/fpga/zynq-fpga.c

   1 /*
   2  * Copyright (c) 2011-2015 Xilinx Inc.
   3  * Copyright (c) 2015, National Instruments Corp.
   4  *
   5  * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
   6  * in their vendor tree.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/fpga/fpga-mgr.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/iopoll.h>
  26 #include <linux/module.h>
  27 #include <linux/mfd/syscon.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/pm.h>
  31 #include <linux/regmap.h>
  32 #include <linux/string.h>
  33 #include <linux/scatterlist.h>
  34
  35 /* Offsets into SLCR regmap */
  36
  37 /* FPGA Software Reset Control */
  38 #define SLCR_FPGA_RST_CTRL_OFFSET       0x240
  39 /* Level Shifters Enable */
  40 #define SLCR_LVL_SHFTR_EN_OFFSET        0x900
  41
  42 /* Constant Definitions */
  43
  44 /* Control Register */
  45 #define CTRL_OFFSET                     0x00
  46 /* Lock Register */
  47 #define LOCK_OFFSET                     0x04
  48 /* Interrupt Status Register */
  49 #define INT_STS_OFFSET                  0x0c
  50 /* Interrupt Mask Register */
  51 #define INT_MASK_OFFSET                 0x10
  52 /* Status Register */
  53 #define STATUS_OFFSET                   0x14
  54 /* DMA Source Address Register */
  55 #define DMA_SRC_ADDR_OFFSET             0x18
  56 /* DMA Destination Address Reg */
  57 #define DMA_DST_ADDR_OFFSET             0x1c
  58 /* DMA Source Transfer Length */
  59 #define DMA_SRC_LEN_OFFSET              0x20
  60 /* DMA Destination Transfer */
  61 #define DMA_DEST_LEN_OFFSET             0x24
  62 /* Unlock Register */
  63 #define UNLOCK_OFFSET                   0x34
  64 /* Misc. Control Register */
  65 #define MCTRL_OFFSET                    0x80
  66
  67 /* Control Register Bit definitions */
  68
  69 /* Signal to reset FPGA */
  70 #define CTRL_PCFG_PROG_B_MASK           BIT(30)
  71 /* Enable PCAP for PR */
  72 #define CTRL_PCAP_PR_MASK               BIT(27)
  73 /* Enable PCAP */
  74 #define CTRL_PCAP_MODE_MASK             BIT(26)
  75
  76 /* Miscellaneous Control Register bit definitions */
  77 /* Internal PCAP loopback */
  78 #define MCTRL_PCAP_LPBK_MASK            BIT(4)
  79
  80 /* Status register bit definitions */
  81
  82 /* FPGA init status */
  83 #define STATUS_DMA_Q_F                  BIT(31)
  84 #define STATUS_DMA_Q_E                  BIT(30)
  85 #define STATUS_PCFG_INIT_MASK           BIT(4)
  86
  87 /* Interrupt Status/Mask Register Bit definitions */
  88 /* DMA command done */
  89 #define IXR_DMA_DONE_MASK               BIT(13)
  90 /* DMA and PCAP cmd done */
  91 #define IXR_D_P_DONE_MASK               BIT(12)
  92  /* FPGA programmed */
  93 #define IXR_PCFG_DONE_MASK              BIT(2)
  94 #define IXR_ERROR_FLAGS_MASK            0x00F0C860
  95 #define IXR_ALL_MASK                    0xF8F7F87F
  96
  97 /* Miscellaneous constant values */
  98
  99 /* Invalid DMA addr */
 100 #define DMA_INVALID_ADDRESS             GENMASK(31, 0)
 101 /* Used to unlock the dev */
 102 #define UNLOCK_MASK                     0x757bdf0d
 103 /* Timeout for polling reset bits */
 104 #define INIT_POLL_TIMEOUT               2500000
 105 /* Delay for polling reset bits */
 106 #define INIT_POLL_DELAY                 20
 107 /* Signal this is the last DMA transfer, wait for the AXI and PCAP before
 108  * interrupting
 109  */
 110 #define DMA_SRC_LAST_TRANSFER           1
 111 /* Timeout for DMA completion */
 112 #define DMA_TIMEOUT_MS                  5000
 113
 114 /* Masks for controlling stuff in SLCR */
 115 /* Disable all Level shifters */
 116 #define LVL_SHFTR_DISABLE_ALL_MASK      0x0
 117 /* Enable Level shifters from PS to PL */
 118 #define LVL_SHFTR_ENABLE_PS_TO_PL       0xa
 119 /* Enable Level shifters from PL to PS */
 120 #define LVL_SHFTR_ENABLE_PL_TO_PS       0xf
 121 /* Enable global resets */
 122 #define FPGA_RST_ALL_MASK               0xf
 123 /* Disable global resets */
 124 #define FPGA_RST_NONE_MASK              0x0
 125
 126 struct zynq_fpga_priv {
 127         int irq;
 128         struct clk *clk;
 129
 130         void __iomem *io_base;
 131         struct regmap *slcr;
 132
 133         spinlock_t dma_lock;
 134         unsigned int dma_elm;
 135         unsigned int dma_nelms;
 136         struct scatterlist *cur_sg;
 137
 138         struct completion dma_done;
 139 };
 140
 141 static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset,
 142                                    u32 val)
 143 {
 144         writel(val, priv->io_base + offset);
 145 }
 146
 147 static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv,
 148                                  u32 offset)
 149 {
 150         return readl(priv->io_base + offset);
 151 }
 152
 153 #define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
 154         readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
 155                            timeout_us)
 156
 157 /* Cause the specified irq mask bits to generate IRQs */
 158 static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable)
 159 {
 160         zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable);
 161 }
 162
 163 /* Must be called with dma_lock held */
 164 static void zynq_step_dma(struct zynq_fpga_priv *priv)
 165 {
 166         u32 addr;
 167         u32 len;
 168         bool first;
 169
 170         first = priv->dma_elm == 0;
 171         while (priv->cur_sg) {
 172                 /* Feed the DMA queue until it is full. */
 173                 if (zynq_fpga_read(priv, STATUS_OFFSET) & STATUS_DMA_Q_F)
 174                         break;
 175
 176                 addr = sg_dma_address(priv->cur_sg);
 177                 len = sg_dma_len(priv->cur_sg);
 178                 if (priv->dma_elm + 1 == priv->dma_nelms) {
 179                         /* The last transfer waits for the PCAP to finish too,
 180                          * notice this also changes the irq_mask to ignore
 181                          * IXR_DMA_DONE_MASK which ensures we do not trigger
 182                          * the completion too early.
 183                          */
 184                         addr |= DMA_SRC_LAST_TRANSFER;
 185                         priv->cur_sg = NULL;
 186                 } else {
 187                         priv->cur_sg = sg_next(priv->cur_sg);
 188                         priv->dma_elm++;
 189                 }
 190
 191                 zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, addr);
 192                 zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, DMA_INVALID_ADDRESS);
 193                 zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, len / 4);
 194                 zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);
 195         }
 196
 197         /* Once the first transfer is queued we can turn on the ISR, future
 198          * calls to zynq_step_dma will happen from the ISR context. The
 199          * dma_lock spinlock guarentees this handover is done coherently, the
 200          * ISR enable is put at the end to avoid another CPU spinning in the
 201          * ISR on this lock.
 202          */
 203         if (first && priv->cur_sg) {
 204                 zynq_fpga_set_irq(priv,
 205                                   IXR_DMA_DONE_MASK | IXR_ERROR_FLAGS_MASK);
 206         } else if (!priv->cur_sg) {
 207                 /* The last transfer changes to DMA & PCAP mode since we do
 208                  * not want to continue until everything has been flushed into
 209                  * the PCAP.
 210                  */
 211                 zynq_fpga_set_irq(priv,
 212                                   IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK);
 213         }
 214 }
 215
 216 static irqreturn_t zynq_fpga_isr(int irq, void *data)
 217 {
 218         struct zynq_fpga_priv *priv = data;
 219         u32 intr_status;
 220
 221         /* If anything other than DMA completion is reported stop and hand
 222          * control back to zynq_fpga_ops_write, something went wrong,
 223          * otherwise progress the DMA.
 224          */
 225         spin_lock(&priv->dma_lock);
 226         intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
 227         if (!(intr_status & IXR_ERROR_FLAGS_MASK) &&
 228             (intr_status & IXR_DMA_DONE_MASK) && priv->cur_sg) {
 229                 zynq_fpga_write(priv, INT_STS_OFFSET, IXR_DMA_DONE_MASK);
 230                 zynq_step_dma(priv);
 231                 spin_unlock(&priv->dma_lock);
 232                 return IRQ_HANDLED;
 233         }
 234         spin_unlock(&priv->dma_lock);
 235
 236         zynq_fpga_set_irq(priv, 0);
 237         complete(&priv->dma_done);
 238
 239         return IRQ_HANDLED;
 240 }
 241
 242 /* Sanity check the proposed bitstream. It must start with the sync word in
 243  * the correct byte order, and be dword aligned. The input is a Xilinx .bin
 244  * file with every 32 bit quantity swapped.
 245  */
 246 static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
 247 {
 248         for (; count >= 4; buf += 4, count -= 4)
 249                 if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&
 250                     buf[3] == 0xaa)
 251                         return true;
 252         return false;
 253 }
 254
 255 static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
 256                                     struct fpga_image_info *info,
 257                                     const char *buf, size_t count)
 258 {
 259         struct zynq_fpga_priv *priv;
 260         u32 ctrl, status;
 261         int err;
 262
 263         priv = mgr->priv;
 264
 265         err = clk_enable(priv->clk);
 266         if (err)
 267                 return err;
 268
 269         /* don't globally reset PL if we're doing partial reconfig */
 270         if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
 271                 if (!zynq_fpga_has_sync(buf, count)) {
 272                         dev_err(&mgr->dev,
 273                                 "Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n");
 274                         err = -EINVAL;
 275                         goto out_err;
 276                 }
 277
 278                 /* assert AXI interface resets */
 279                 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
 280                              FPGA_RST_ALL_MASK);
 281
 282                 /* disable all level shifters */
 283                 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
 284                              LVL_SHFTR_DISABLE_ALL_MASK);
 285                 /* enable level shifters from PS to PL */
 286                 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
 287                              LVL_SHFTR_ENABLE_PS_TO_PL);
 288
 289                 /* create a rising edge on PCFG_INIT. PCFG_INIT follows
 290                  * PCFG_PROG_B, so we need to poll it after setting PCFG_PROG_B
 291                  * to make sure the rising edge actually happens.
 292                  * Note: PCFG_PROG_B is low active, sequence as described in
 293                  * UG585 v1.10 page 211
 294                  */
 295                 ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
 296                 ctrl |= CTRL_PCFG_PROG_B_MASK;
 297
 298                 zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
 299
 300                 err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
 301                                              status & STATUS_PCFG_INIT_MASK,
 302                                              INIT_POLL_DELAY,
 303                                              INIT_POLL_TIMEOUT);
 304                 if (err) {
 305                         dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
 306                         goto out_err;
 307                 }
 308
 309                 ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
 310                 ctrl &= ~CTRL_PCFG_PROG_B_MASK;
 311
 312                 zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
 313
 314                 err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
 315                                              !(status & STATUS_PCFG_INIT_MASK),
 316                                              INIT_POLL_DELAY,
 317                                              INIT_POLL_TIMEOUT);
 318                 if (err) {
 319                         dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
 320                         goto out_err;
 321                 }
 322
 323                 ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
 324                 ctrl |= CTRL_PCFG_PROG_B_MASK;
 325
 326                 zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
 327
 328                 err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
 329                                              status & STATUS_PCFG_INIT_MASK,
 330                                              INIT_POLL_DELAY,
 331                                              INIT_POLL_TIMEOUT);
 332                 if (err) {
 333                         dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
 334                         goto out_err;
 335                 }
 336         }
 337
 338         /* set configuration register with following options:
 339          * - enable PCAP interface
 340          * - set throughput for maximum speed
 341          * - set CPU in user mode
 342          */
 343         ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
 344         zynq_fpga_write(priv, CTRL_OFFSET,
 345                         (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK | ctrl));
 346
 347         /* We expect that the command queue is empty right now. */
 348         status = zynq_fpga_read(priv, STATUS_OFFSET);
 349         if ((status & STATUS_DMA_Q_F) ||
 350             (status & STATUS_DMA_Q_E) != STATUS_DMA_Q_E) {
 351                 dev_err(&mgr->dev, "DMA command queue not right\n");
 352                 err = -EBUSY;
 353                 goto out_err;
 354         }
 355
 356         /* ensure internal PCAP loopback is disabled */
 357         ctrl = zynq_fpga_read(priv, MCTRL_OFFSET);
 358         zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl));
 359
 360         clk_disable(priv->clk);
 361
 362         return 0;
 363
 364 out_err:
 365         clk_disable(priv->clk);
 366
 367         return err;
 368 }
 369
 370 static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
 371 {
 372         struct zynq_fpga_priv *priv;
 373         const char *why;
 374         int err;
 375         u32 intr_status;
 376         unsigned long timeout;
 377         unsigned long flags;
 378         struct scatterlist *sg;
 379         int i;
 380
 381         priv = mgr->priv;
 382
 383         /* The hardware can only DMA multiples of 4 bytes, and it requires the
 384          * starting addresses to be aligned to 64 bits (UG585 pg 212).
 385          */
 386         for_each_sg(sgt->sgl, sg, sgt->nents, i) {
 387                 if ((sg->offset % 8) || (sg->length % 4)) {
 388                         dev_err(&mgr->dev,
 389                             "Invalid bitstream, chunks must be aligned\n");
 390                         return -EINVAL;
 391                 }
 392         }
 393
 394         priv->dma_nelms =
 395             dma_map_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
 396         if (priv->dma_nelms == 0) {
 397                 dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
 398                 return -ENOMEM;
 399         }
 400
 401         /* enable clock */
 402         err = clk_enable(priv->clk);
 403         if (err)
 404                 goto out_free;
 405
 406         zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
 407         reinit_completion(&priv->dma_done);
 408
 409         /* zynq_step_dma will turn on interrupts */
 410         spin_lock_irqsave(&priv->dma_lock, flags);
 411         priv->dma_elm = 0;
 412         priv->cur_sg = sgt->sgl;
 413         zynq_step_dma(priv);
 414         spin_unlock_irqrestore(&priv->dma_lock, flags);
 415
 416         timeout = wait_for_completion_timeout(&priv->dma_done,
 417                                               msecs_to_jiffies(DMA_TIMEOUT_MS));
 418
 419         spin_lock_irqsave(&priv->dma_lock, flags);
 420         zynq_fpga_set_irq(priv, 0);
 421         priv->cur_sg = NULL;
 422         spin_unlock_irqrestore(&priv->dma_lock, flags);
 423
 424         intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
 425         zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
 426
 427         /* There doesn't seem to be a way to force cancel any DMA, so if
 428          * something went wrong we are relying on the hardware to have halted
 429          * the DMA before we get here, if there was we could use
 430          * wait_for_completion_interruptible too.
 431          */
 432
 433         if (intr_status & IXR_ERROR_FLAGS_MASK) {
 434                 why = "DMA reported error";
 435                 err = -EIO;
 436                 goto out_report;
 437         }
 438
 439         if (priv->cur_sg ||
 440             !((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
 441                 if (timeout == 0)
 442                         why = "DMA timed out";
 443                 else
 444                         why = "DMA did not complete";
 445                 err = -EIO;
 446                 goto out_report;
 447         }
 448
 449         err = 0;
 450         goto out_clk;
 451
 452 out_report:
 453         dev_err(&mgr->dev,
 454                 "%s: INT_STS:0x%x CTRL:0x%x LOCK:0x%x INT_MASK:0x%x STATUS:0x%x MCTRL:0x%x\n",
 455                 why,
 456                 intr_status,
 457                 zynq_fpga_read(priv, CTRL_OFFSET),
 458                 zynq_fpga_read(priv, LOCK_OFFSET),
 459                 zynq_fpga_read(priv, INT_MASK_OFFSET),
 460                 zynq_fpga_read(priv, STATUS_OFFSET),
 461                 zynq_fpga_read(priv, MCTRL_OFFSET));
 462
 463 out_clk:
 464         clk_disable(priv->clk);
 465
 466 out_free:
 467         dma_unmap_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
 468         return err;
 469 }
 470
 471 static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
 472                                         struct fpga_image_info *info)
 473 {
 474         struct zynq_fpga_priv *priv = mgr->priv;
 475         int err;
 476         u32 intr_status;
 477
 478         err = clk_enable(priv->clk);
 479         if (err)
 480                 return err;
 481
 482         err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
 483                                      intr_status & IXR_PCFG_DONE_MASK,
 484                                      INIT_POLL_DELAY,
 485                                      INIT_POLL_TIMEOUT);
 486
 487         clk_disable(priv->clk);
 488
 489         if (err)
 490                 return err;
 491
 492         /* for the partial reconfig case we didn't touch the level shifters */
 493         if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
 494                 /* enable level shifters from PL to PS */
 495                 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
 496                              LVL_SHFTR_ENABLE_PL_TO_PS);
 497
 498                 /* deassert AXI interface resets */
 499                 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
 500                              FPGA_RST_NONE_MASK);
 501         }
 502
 503         return 0;
 504 }
 505
 506 static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr)
 507 {
 508         int err;
 509         u32 intr_status;
 510         struct zynq_fpga_priv *priv;
 511
 512         priv = mgr->priv;
 513
 514         err = clk_enable(priv->clk);
 515         if (err)
 516                 return FPGA_MGR_STATE_UNKNOWN;
 517
 518         intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
 519         clk_disable(priv->clk);
 520
 521         if (intr_status & IXR_PCFG_DONE_MASK)
 522                 return FPGA_MGR_STATE_OPERATING;
 523
 524         return FPGA_MGR_STATE_UNKNOWN;
 525 }
 526
 527 static const struct fpga_manager_ops zynq_fpga_ops = {
 528         .initial_header_size = 128,
 529         .state = zynq_fpga_ops_state,
 530         .write_init = zynq_fpga_ops_write_init,
 531         .write_sg = zynq_fpga_ops_write,
 532         .write_complete = zynq_fpga_ops_write_complete,
 533 };
 534
 535 static int zynq_fpga_probe(struct platform_device *pdev)
 536 {
 537         struct device *dev = &pdev->dev;
 538         struct zynq_fpga_priv *priv;
 539         struct resource *res;
 540         int err;
 541
 542         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 543         if (!priv)
 544                 return -ENOMEM;
 545         spin_lock_init(&priv->dma_lock);
 546
 547         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 548         priv->io_base = devm_ioremap_resource(dev, res);
 549         if (IS_ERR(priv->io_base))
 550                 return PTR_ERR(priv->io_base);
 551
 552         priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
 553                 "syscon");
 554         if (IS_ERR(priv->slcr)) {
 555                 dev_err(dev, "unable to get zynq-slcr regmap\n");
 556                 return PTR_ERR(priv->slcr);
 557         }
 558
 559         init_completion(&priv->dma_done);
 560
 561         priv->irq = platform_get_irq(pdev, 0);
 562         if (priv->irq < 0) {
 563                 dev_err(dev, "No IRQ available\n");
 564                 return priv->irq;
 565         }
 566
 567         priv->clk = devm_clk_get(dev, "ref_clk");
 568         if (IS_ERR(priv->clk)) {
 569                 dev_err(dev, "input clock not found\n");
 570                 return PTR_ERR(priv->clk);
 571         }
 572
 573         err = clk_prepare_enable(priv->clk);
 574         if (err) {
 575                 dev_err(dev, "unable to enable clock\n");
 576                 return err;
 577         }
 578
 579         /* unlock the device */
 580         zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
 581
 582         zynq_fpga_set_irq(priv, 0);
 583         zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
 584         err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
 585                                priv);
 586         if (err) {
 587                 dev_err(dev, "unable to request IRQ\n");
 588                 clk_disable_unprepare(priv->clk);
 589                 return err;
 590         }
 591
 592         clk_disable(priv->clk);
 593
 594         err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",
 595                                 &zynq_fpga_ops, priv);
 596         if (err) {
 597                 dev_err(dev, "unable to register FPGA manager\n");
 598                 clk_unprepare(priv->clk);
 599                 return err;
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int zynq_fpga_remove(struct platform_device *pdev)
 606 {
 607         struct zynq_fpga_priv *priv;
 608         struct fpga_manager *mgr;
 609
 610         mgr = platform_get_drvdata(pdev);
 611         priv = mgr->priv;
 612
 613         fpga_mgr_unregister(&pdev->dev);
 614
 615         clk_unprepare(priv->clk);
 616
 617         return 0;
 618 }
 619
 620 #ifdef CONFIG_OF
 621 static const struct of_device_id zynq_fpga_of_match[] = {
 622         { .compatible = "xlnx,zynq-devcfg-1.0", },
 623         {},
 624 };
 625
 626 MODULE_DEVICE_TABLE(of, zynq_fpga_of_match);
 627 #endif
 628
 629 static struct platform_driver zynq_fpga_driver = {
 630         .probe = zynq_fpga_probe,
 631         .remove = zynq_fpga_remove,
 632         .driver = {
 633                 .name = "zynq_fpga_manager",
 634                 .of_match_table = of_match_ptr(zynq_fpga_of_match),
 635         },
 636 };
 637
 638 module_platform_driver(zynq_fpga_driver);
 639
 640 MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
 641 MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
 642 MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");
 643 MODULE_LICENSE("GPL v2");