drivers/gpio/gpio-104-dio-48e.c

   1 /*
   2  * GPIO driver for the ACCES 104-DIO-48E series
   3  * Copyright (C) 2016 William Breathitt Gray
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License, version 2, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * This driver supports the following ACCES devices: 104-DIO-48E and
  15  * 104-DIO-24E.
  16  */
  17 #include <linux/bitops.h>
  18 #include <linux/device.h>
  19 #include <linux/errno.h>
  20 #include <linux/gpio/driver.h>
  21 #include <linux/io.h>
  22 #include <linux/ioport.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irqdesc.h>
  25 #include <linux/isa.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/spinlock.h>
  30
  31 #define DIO48E_EXTENT 16
  32 #define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
  33
  34 static unsigned int base[MAX_NUM_DIO48E];
  35 static unsigned int num_dio48e;
  36 module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
  37 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
  38
  39 static unsigned int irq[MAX_NUM_DIO48E];
  40 module_param_hw_array(irq, uint, irq, NULL, 0);
  41 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
  42
  43 /**
  44  * struct dio48e_gpio - GPIO device private data structure
  45  * @chip:       instance of the gpio_chip
  46  * @io_state:   bit I/O state (whether bit is set to input or output)
  47  * @out_state:  output bits state
  48  * @control:    Control registers state
  49  * @lock:       synchronization lock to prevent I/O race conditions
  50  * @base:       base port address of the GPIO device
  51  * @irq_mask:   I/O bits affected by interrupts
  52  */
  53 struct dio48e_gpio {
  54         struct gpio_chip chip;
  55         unsigned char io_state[6];
  56         unsigned char out_state[6];
  57         unsigned char control[2];
  58         raw_spinlock_t lock;
  59         unsigned base;
  60         unsigned char irq_mask;
  61 };
  62
  63 static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  64 {
  65         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
  66         const unsigned port = offset / 8;
  67         const unsigned mask = BIT(offset % 8);
  68
  69         return !!(dio48egpio->io_state[port] & mask);
  70 }
  71
  72 static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  73 {
  74         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
  75         const unsigned io_port = offset / 8;
  76         const unsigned int control_port = io_port / 3;
  77         const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
  78         unsigned long flags;
  79         unsigned control;
  80
  81         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
  82
  83         /* Check if configuring Port C */
  84         if (io_port == 2 || io_port == 5) {
  85                 /* Port C can be configured by nibble */
  86                 if (offset % 8 > 3) {
  87                         dio48egpio->io_state[io_port] |= 0xF0;
  88                         dio48egpio->control[control_port] |= BIT(3);
  89                 } else {
  90                         dio48egpio->io_state[io_port] |= 0x0F;
  91                         dio48egpio->control[control_port] |= BIT(0);
  92                 }
  93         } else {
  94                 dio48egpio->io_state[io_port] |= 0xFF;
  95                 if (io_port == 0 || io_port == 3)
  96                         dio48egpio->control[control_port] |= BIT(4);
  97                 else
  98                         dio48egpio->control[control_port] |= BIT(1);
  99         }
 100
 101         control = BIT(7) | dio48egpio->control[control_port];
 102         outb(control, control_addr);
 103         control &= ~BIT(7);
 104         outb(control, control_addr);
 105
 106         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 107
 108         return 0;
 109 }
 110
 111 static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 112         int value)
 113 {
 114         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 115         const unsigned io_port = offset / 8;
 116         const unsigned int control_port = io_port / 3;
 117         const unsigned mask = BIT(offset % 8);
 118         const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
 119         const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port;
 120         unsigned long flags;
 121         unsigned control;
 122
 123         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 124
 125         /* Check if configuring Port C */
 126         if (io_port == 2 || io_port == 5) {
 127                 /* Port C can be configured by nibble */
 128                 if (offset % 8 > 3) {
 129                         dio48egpio->io_state[io_port] &= 0x0F;
 130                         dio48egpio->control[control_port] &= ~BIT(3);
 131                 } else {
 132                         dio48egpio->io_state[io_port] &= 0xF0;
 133                         dio48egpio->control[control_port] &= ~BIT(0);
 134                 }
 135         } else {
 136                 dio48egpio->io_state[io_port] &= 0x00;
 137                 if (io_port == 0 || io_port == 3)
 138                         dio48egpio->control[control_port] &= ~BIT(4);
 139                 else
 140                         dio48egpio->control[control_port] &= ~BIT(1);
 141         }
 142
 143         if (value)
 144                 dio48egpio->out_state[io_port] |= mask;
 145         else
 146                 dio48egpio->out_state[io_port] &= ~mask;
 147
 148         control = BIT(7) | dio48egpio->control[control_port];
 149         outb(control, control_addr);
 150
 151         outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
 152
 153         control &= ~BIT(7);
 154         outb(control, control_addr);
 155
 156         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 157
 158         return 0;
 159 }
 160
 161 static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset)
 162 {
 163         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 164         const unsigned port = offset / 8;
 165         const unsigned mask = BIT(offset % 8);
 166         const unsigned in_port = (port > 2) ? port + 1 : port;
 167         unsigned long flags;
 168         unsigned port_state;
 169
 170         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 171
 172         /* ensure that GPIO is set for input */
 173         if (!(dio48egpio->io_state[port] & mask)) {
 174                 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 175                 return -EINVAL;
 176         }
 177
 178         port_state = inb(dio48egpio->base + in_port);
 179
 180         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 181
 182         return !!(port_state & mask);
 183 }
 184
 185 static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 186 {
 187         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 188         const unsigned port = offset / 8;
 189         const unsigned mask = BIT(offset % 8);
 190         const unsigned out_port = (port > 2) ? port + 1 : port;
 191         unsigned long flags;
 192
 193         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 194
 195         if (value)
 196                 dio48egpio->out_state[port] |= mask;
 197         else
 198                 dio48egpio->out_state[port] &= ~mask;
 199
 200         outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
 201
 202         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 203 }
 204
 205 static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
 206         unsigned long *mask, unsigned long *bits)
 207 {
 208         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 209         unsigned int i;
 210         const unsigned int gpio_reg_size = 8;
 211         unsigned int port;
 212         unsigned int out_port;
 213         unsigned int bitmask;
 214         unsigned long flags;
 215
 216         /* set bits are evaluated a gpio register size at a time */
 217         for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
 218                 /* no more set bits in this mask word; skip to the next word */
 219                 if (!mask[BIT_WORD(i)]) {
 220                         i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
 221                         continue;
 222                 }
 223
 224                 port = i / gpio_reg_size;
 225                 out_port = (port > 2) ? port + 1 : port;
 226                 bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)];
 227
 228                 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 229
 230                 /* update output state data and set device gpio register */
 231                 dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)];
 232                 dio48egpio->out_state[port] |= bitmask;
 233                 outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
 234
 235                 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 236
 237                 /* prepare for next gpio register set */
 238                 mask[BIT_WORD(i)] >>= gpio_reg_size;
 239                 bits[BIT_WORD(i)] >>= gpio_reg_size;
 240         }
 241 }
 242
 243 static void dio48e_irq_ack(struct irq_data *data)
 244 {
 245 }
 246
 247 static void dio48e_irq_mask(struct irq_data *data)
 248 {
 249         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 250         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 251         const unsigned long offset = irqd_to_hwirq(data);
 252         unsigned long flags;
 253
 254         /* only bit 3 on each respective Port C supports interrupts */
 255         if (offset != 19 && offset != 43)
 256                 return;
 257
 258         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 259
 260         if (offset == 19)
 261                 dio48egpio->irq_mask &= ~BIT(0);
 262         else
 263                 dio48egpio->irq_mask &= ~BIT(1);
 264
 265         if (!dio48egpio->irq_mask)
 266                 /* disable interrupts */
 267                 inb(dio48egpio->base + 0xB);
 268
 269         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 270 }
 271
 272 static void dio48e_irq_unmask(struct irq_data *data)
 273 {
 274         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 275         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 276         const unsigned long offset = irqd_to_hwirq(data);
 277         unsigned long flags;
 278
 279         /* only bit 3 on each respective Port C supports interrupts */
 280         if (offset != 19 && offset != 43)
 281                 return;
 282
 283         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 284
 285         if (!dio48egpio->irq_mask) {
 286                 /* enable interrupts */
 287                 outb(0x00, dio48egpio->base + 0xF);
 288                 outb(0x00, dio48egpio->base + 0xB);
 289         }
 290
 291         if (offset == 19)
 292                 dio48egpio->irq_mask |= BIT(0);
 293         else
 294                 dio48egpio->irq_mask |= BIT(1);
 295
 296         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 297 }
 298
 299 static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
 300 {
 301         const unsigned long offset = irqd_to_hwirq(data);
 302
 303         /* only bit 3 on each respective Port C supports interrupts */
 304         if (offset != 19 && offset != 43)
 305                 return -EINVAL;
 306
 307         if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
 308                 return -EINVAL;
 309
 310         return 0;
 311 }
 312
 313 static struct irq_chip dio48e_irqchip = {
 314         .name = "104-dio-48e",
 315         .irq_ack = dio48e_irq_ack,
 316         .irq_mask = dio48e_irq_mask,
 317         .irq_unmask = dio48e_irq_unmask,
 318         .irq_set_type = dio48e_irq_set_type
 319 };
 320
 321 static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
 322 {
 323         struct dio48e_gpio *const dio48egpio = dev_id;
 324         struct gpio_chip *const chip = &dio48egpio->chip;
 325         const unsigned long irq_mask = dio48egpio->irq_mask;
 326         unsigned long gpio;
 327
 328         for_each_set_bit(gpio, &irq_mask, 2)
 329                 generic_handle_irq(irq_find_mapping(chip->irqdomain,
 330                         19 + gpio*24));
 331
 332         raw_spin_lock(&dio48egpio->lock);
 333
 334         outb(0x00, dio48egpio->base + 0xF);
 335
 336         raw_spin_unlock(&dio48egpio->lock);
 337
 338         return IRQ_HANDLED;
 339 }
 340
 341 #define DIO48E_NGPIO 48
 342 static const char *dio48e_names[DIO48E_NGPIO] = {
 343         "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
 344         "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
 345         "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
 346         "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
 347         "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
 348         "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
 349         "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
 350         "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
 351         "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
 352         "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
 353         "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
 354         "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
 355         "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
 356         "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
 357         "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
 358         "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
 359 };
 360
 361 static int dio48e_probe(struct device *dev, unsigned int id)
 362 {
 363         struct dio48e_gpio *dio48egpio;
 364         const char *const name = dev_name(dev);
 365         int err;
 366
 367         dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
 368         if (!dio48egpio)
 369                 return -ENOMEM;
 370
 371         if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
 372                 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
 373                         base[id], base[id] + DIO48E_EXTENT);
 374                 return -EBUSY;
 375         }
 376
 377         dio48egpio->chip.label = name;
 378         dio48egpio->chip.parent = dev;
 379         dio48egpio->chip.owner = THIS_MODULE;
 380         dio48egpio->chip.base = -1;
 381         dio48egpio->chip.ngpio = DIO48E_NGPIO;
 382         dio48egpio->chip.names = dio48e_names;
 383         dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
 384         dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
 385         dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
 386         dio48egpio->chip.get = dio48e_gpio_get;
 387         dio48egpio->chip.set = dio48e_gpio_set;
 388         dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
 389         dio48egpio->base = base[id];
 390
 391         raw_spin_lock_init(&dio48egpio->lock);
 392
 393         err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
 394         if (err) {
 395                 dev_err(dev, "GPIO registering failed (%d)\n", err);
 396                 return err;
 397         }
 398
 399         /* initialize all GPIO as output */
 400         outb(0x80, base[id] + 3);
 401         outb(0x00, base[id]);
 402         outb(0x00, base[id] + 1);
 403         outb(0x00, base[id] + 2);
 404         outb(0x00, base[id] + 3);
 405         outb(0x80, base[id] + 7);
 406         outb(0x00, base[id] + 4);
 407         outb(0x00, base[id] + 5);
 408         outb(0x00, base[id] + 6);
 409         outb(0x00, base[id] + 7);
 410
 411         /* disable IRQ by default */
 412         inb(base[id] + 0xB);
 413
 414         err = gpiochip_irqchip_add(&dio48egpio->chip, &dio48e_irqchip, 0,
 415                 handle_edge_irq, IRQ_TYPE_NONE);
 416         if (err) {
 417                 dev_err(dev, "Could not add irqchip (%d)\n", err);
 418                 return err;
 419         }
 420
 421         err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
 422                 dio48egpio);
 423         if (err) {
 424                 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
 425                 return err;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static struct isa_driver dio48e_driver = {
 432         .probe = dio48e_probe,
 433         .driver = {
 434                 .name = "104-dio-48e"
 435         },
 436 };
 437 module_isa_driver(dio48e_driver, num_dio48e);
 438
 439 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
 440 MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
 441 MODULE_LICENSE("GPL v2");