drivers/gpio/gpio-aspeed.c

   1 /*
   2  * Copyright 2015 IBM Corp.
   3  *
   4  * Joel Stanley <joel@jms.id.au>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <asm/div64.h>
  13 #include <linux/clk.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/hashtable.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/string.h>
  24
  25 struct aspeed_bank_props {
  26         unsigned int bank;
  27         u32 input;
  28         u32 output;
  29 };
  30
  31 struct aspeed_gpio_config {
  32         unsigned int nr_gpios;
  33         const struct aspeed_bank_props *props;
  34 };
  35
  36 /*
  37  * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
  38  * @timer_users: Tracks the number of users for each timer
  39  *
  40  * The @timer_users has four elements but the first element is unused. This is
  41  * to simplify accounting and indexing, as a zero value in @offset_timer
  42  * represents disabled debouncing for the GPIO. Any other value for an element
  43  * of @offset_timer is used as an index into @timer_users. This behaviour of
  44  * the zero value aligns with the behaviour of zero built from the timer
  45  * configuration registers (i.e. debouncing is disabled).
  46  */
  47 struct aspeed_gpio {
  48         struct gpio_chip chip;
  49         spinlock_t lock;
  50         void __iomem *base;
  51         int irq;
  52         const struct aspeed_gpio_config *config;
  53
  54         u8 *offset_timer;
  55         unsigned int timer_users[4];
  56         struct clk *clk;
  57 };
  58
  59 struct aspeed_gpio_bank {
  60         uint16_t        val_regs;
  61         uint16_t        irq_regs;
  62         uint16_t        debounce_regs;
  63         const char      names[4][3];
  64 };
  65
  66 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
  67
  68 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
  69         {
  70                 .val_regs = 0x0000,
  71                 .irq_regs = 0x0008,
  72                 .debounce_regs = 0x0040,
  73                 .names = { "A", "B", "C", "D" },
  74         },
  75         {
  76                 .val_regs = 0x0020,
  77                 .irq_regs = 0x0028,
  78                 .debounce_regs = 0x0048,
  79                 .names = { "E", "F", "G", "H" },
  80         },
  81         {
  82                 .val_regs = 0x0070,
  83                 .irq_regs = 0x0098,
  84                 .debounce_regs = 0x00b0,
  85                 .names = { "I", "J", "K", "L" },
  86         },
  87         {
  88                 .val_regs = 0x0078,
  89                 .irq_regs = 0x00e8,
  90                 .debounce_regs = 0x0100,
  91                 .names = { "M", "N", "O", "P" },
  92         },
  93         {
  94                 .val_regs = 0x0080,
  95                 .irq_regs = 0x0118,
  96                 .debounce_regs = 0x0130,
  97                 .names = { "Q", "R", "S", "T" },
  98         },
  99         {
 100                 .val_regs = 0x0088,
 101                 .irq_regs = 0x0148,
 102                 .debounce_regs = 0x0160,
 103                 .names = { "U", "V", "W", "X" },
 104         },
 105         {
 106                 .val_regs = 0x01E0,
 107                 .irq_regs = 0x0178,
 108                 .debounce_regs = 0x0190,
 109                 .names = { "Y", "Z", "AA", "AB" },
 110         },
 111         {
 112                 .val_regs = 0x01E8,
 113                 .irq_regs = 0x01A8,
 114                 .debounce_regs = 0x01c0,
 115                 .names = { "AC", "", "", "" },
 116         },
 117 };
 118
 119 #define GPIO_BANK(x)    ((x) >> 5)
 120 #define GPIO_OFFSET(x)  ((x) & 0x1f)
 121 #define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
 122
 123 #define GPIO_DATA       0x00
 124 #define GPIO_DIR        0x04
 125
 126 #define GPIO_IRQ_ENABLE 0x00
 127 #define GPIO_IRQ_TYPE0  0x04
 128 #define GPIO_IRQ_TYPE1  0x08
 129 #define GPIO_IRQ_TYPE2  0x0c
 130 #define GPIO_IRQ_STATUS 0x10
 131
 132 #define GPIO_DEBOUNCE_SEL1 0x00
 133 #define GPIO_DEBOUNCE_SEL2 0x04
 134
 135 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
 136 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
 137 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
 138
 139 static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
 140 {
 141         unsigned int bank = GPIO_BANK(offset);
 142
 143         WARN_ON(bank > ARRAY_SIZE(aspeed_gpio_banks));
 144         return &aspeed_gpio_banks[bank];
 145 }
 146
 147 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
 148 {
 149         return !(props->input || props->output);
 150 }
 151
 152 static inline const struct aspeed_bank_props *find_bank_props(
 153                 struct aspeed_gpio *gpio, unsigned int offset)
 154 {
 155         const struct aspeed_bank_props *props = gpio->config->props;
 156
 157         while (!is_bank_props_sentinel(props)) {
 158                 if (props->bank == GPIO_BANK(offset))
 159                         return props;
 160                 props++;
 161         }
 162
 163         return NULL;
 164 }
 165
 166 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
 167 {
 168         const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
 169         const struct aspeed_gpio_bank *bank = to_bank(offset);
 170         unsigned int group = GPIO_OFFSET(offset) / 8;
 171
 172         return bank->names[group][0] != '\0' &&
 173                 (!props || ((props->input | props->output) & GPIO_BIT(offset)));
 174 }
 175
 176 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
 177 {
 178         const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
 179
 180         return !props || (props->input & GPIO_BIT(offset));
 181 }
 182
 183 #define have_irq(g, o) have_input((g), (o))
 184 #define have_debounce(g, o) have_input((g), (o))
 185
 186 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
 187 {
 188         const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
 189
 190         return !props || (props->output & GPIO_BIT(offset));
 191 }
 192
 193 static void __iomem *bank_val_reg(struct aspeed_gpio *gpio,
 194                 const struct aspeed_gpio_bank *bank,
 195                 unsigned int reg)
 196 {
 197         return gpio->base + bank->val_regs + reg;
 198 }
 199
 200 static void __iomem *bank_irq_reg(struct aspeed_gpio *gpio,
 201                 const struct aspeed_gpio_bank *bank,
 202                 unsigned int reg)
 203 {
 204         return gpio->base + bank->irq_regs + reg;
 205 }
 206
 207 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
 208 {
 209         struct aspeed_gpio *gpio = gpiochip_get_data(gc);
 210         const struct aspeed_gpio_bank *bank = to_bank(offset);
 211
 212         return !!(ioread32(bank_val_reg(gpio, bank, GPIO_DATA))
 213                         & GPIO_BIT(offset));
 214 }
 215
 216 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
 217                               int val)
 218 {
 219         struct aspeed_gpio *gpio = gpiochip_get_data(gc);
 220         const struct aspeed_gpio_bank *bank = to_bank(offset);
 221         void __iomem *addr;
 222         u32 reg;
 223
 224         addr = bank_val_reg(gpio, bank, GPIO_DATA);
 225         reg = ioread32(addr);
 226
 227         if (val)
 228                 reg |= GPIO_BIT(offset);
 229         else
 230                 reg &= ~GPIO_BIT(offset);
 231
 232         iowrite32(reg, addr);
 233 }
 234
 235 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
 236                             int val)
 237 {
 238         struct aspeed_gpio *gpio = gpiochip_get_data(gc);
 239         unsigned long flags;
 240
 241         spin_lock_irqsave(&gpio->lock, flags);
 242
 243         __aspeed_gpio_set(gc, offset, val);
 244
 245         spin_unlock_irqrestore(&gpio->lock, flags);
 246 }
 247
 248 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
 249 {
 250         struct aspeed_gpio *gpio = gpiochip_get_data(gc);
 251         const struct aspeed_gpio_bank *bank = to_bank(offset);
 252         unsigned long flags;
 253         u32 reg;
 254
 255         if (!have_input(gpio, offset))
 256                 return -ENOTSUPP;
 257
 258         spin_lock_irqsave(&gpio->lock, flags);
 259
 260         reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
 261         iowrite32(reg & ~GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR));
 262
 263         spin_unlock_irqrestore(&gpio->lock, flags);
 264
 265         return 0;
 266 }
 267
 268 static int aspeed_gpio_dir_out(struct gpio_chip *gc,
 269                                unsigned int offset, int val)
 270 {
 271         struct aspeed_gpio *gpio = gpiochip_get_data(gc);
 272         const struct aspeed_gpio_bank *bank = to_bank(offset);
 273         unsigned long flags;
 274         u32 reg;
 275
 276         if (!have_output(gpio, offset))
 277                 return -ENOTSUPP;
 278
 279         spin_lock_irqsave(&gpio->lock, flags);
 280
 281         reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
 282         iowrite32(reg | GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR));
 283
 284         __aspeed_gpio_set(gc, offset, val);
 285
 286         spin_unlock_irqrestore(&gpio->lock, flags);
 287
 288         return 0;
 289 }
 290
 291 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 292 {
 293         struct aspeed_gpio *gpio = gpiochip_get_data(gc);
 294         const struct aspeed_gpio_bank *bank = to_bank(offset);
 295         unsigned long flags;
 296         u32 val;
 297
 298         if (!have_input(gpio, offset))
 299                 return 0;
 300
 301         if (!have_output(gpio, offset))
 302                 return 1;
 303
 304         spin_lock_irqsave(&gpio->lock, flags);
 305
 306         val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset);
 307
 308         spin_unlock_irqrestore(&gpio->lock, flags);
 309
 310         return !val;
 311
 312 }
 313
 314 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
 315                 struct aspeed_gpio **gpio,
 316                 const struct aspeed_gpio_bank **bank,
 317                 u32 *bit)
 318 {
 319         int offset;
 320         struct aspeed_gpio *internal;
 321
 322         offset = irqd_to_hwirq(d);
 323
 324         internal = irq_data_get_irq_chip_data(d);
 325
 326         /* This might be a bit of a questionable place to check */
 327         if (!have_irq(internal, offset))
 328                 return -ENOTSUPP;
 329
 330         *gpio = internal;
 331         *bank = to_bank(offset);
 332         *bit = GPIO_BIT(offset);
 333
 334         return 0;
 335 }
 336
 337 static void aspeed_gpio_irq_ack(struct irq_data *d)
 338 {
 339         const struct aspeed_gpio_bank *bank;
 340         struct aspeed_gpio *gpio;
 341         unsigned long flags;
 342         void __iomem *status_addr;
 343         u32 bit;
 344         int rc;
 345
 346         rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
 347         if (rc)
 348                 return;
 349
 350         status_addr = bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS);
 351
 352         spin_lock_irqsave(&gpio->lock, flags);
 353         iowrite32(bit, status_addr);
 354         spin_unlock_irqrestore(&gpio->lock, flags);
 355 }
 356
 357 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
 358 {
 359         const struct aspeed_gpio_bank *bank;
 360         struct aspeed_gpio *gpio;
 361         unsigned long flags;
 362         u32 reg, bit;
 363         void __iomem *addr;
 364         int rc;
 365
 366         rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
 367         if (rc)
 368                 return;
 369
 370         addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE);
 371
 372         spin_lock_irqsave(&gpio->lock, flags);
 373
 374         reg = ioread32(addr);
 375         if (set)
 376                 reg |= bit;
 377         else
 378                 reg &= bit;
 379         iowrite32(reg, addr);
 380
 381         spin_unlock_irqrestore(&gpio->lock, flags);
 382 }
 383
 384 static void aspeed_gpio_irq_mask(struct irq_data *d)
 385 {
 386         aspeed_gpio_irq_set_mask(d, false);
 387 }
 388
 389 static void aspeed_gpio_irq_unmask(struct irq_data *d)
 390 {
 391         aspeed_gpio_irq_set_mask(d, true);
 392 }
 393
 394 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
 395 {
 396         u32 type0 = 0;
 397         u32 type1 = 0;
 398         u32 type2 = 0;
 399         u32 bit, reg;
 400         const struct aspeed_gpio_bank *bank;
 401         irq_flow_handler_t handler;
 402         struct aspeed_gpio *gpio;
 403         unsigned long flags;
 404         void __iomem *addr;
 405         int rc;
 406
 407         rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
 408         if (rc)
 409                 return -EINVAL;
 410
 411         switch (type & IRQ_TYPE_SENSE_MASK) {
 412         case IRQ_TYPE_EDGE_BOTH:
 413                 type2 |= bit;
 414         case IRQ_TYPE_EDGE_RISING:
 415                 type0 |= bit;
 416         case IRQ_TYPE_EDGE_FALLING:
 417                 handler = handle_edge_irq;
 418                 break;
 419         case IRQ_TYPE_LEVEL_HIGH:
 420                 type0 |= bit;
 421         case IRQ_TYPE_LEVEL_LOW:
 422                 type1 |= bit;
 423                 handler = handle_level_irq;
 424                 break;
 425         default:
 426                 return -EINVAL;
 427         }
 428
 429         spin_lock_irqsave(&gpio->lock, flags);
 430
 431         addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0);
 432         reg = ioread32(addr);
 433         reg = (reg & ~bit) | type0;
 434         iowrite32(reg, addr);
 435
 436         addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1);
 437         reg = ioread32(addr);
 438         reg = (reg & ~bit) | type1;
 439         iowrite32(reg, addr);
 440
 441         addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2);
 442         reg = ioread32(addr);
 443         reg = (reg & ~bit) | type2;
 444         iowrite32(reg, addr);
 445
 446         spin_unlock_irqrestore(&gpio->lock, flags);
 447
 448         irq_set_handler_locked(d, handler);
 449
 450         return 0;
 451 }
 452
 453 static void aspeed_gpio_irq_handler(struct irq_desc *desc)
 454 {
 455         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 456         struct irq_chip *ic = irq_desc_get_chip(desc);
 457         struct aspeed_gpio *data = gpiochip_get_data(gc);
 458         unsigned int i, p, girq;
 459         unsigned long reg;
 460
 461         chained_irq_enter(ic, desc);
 462
 463         for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) {
 464                 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
 465
 466                 reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS));
 467
 468                 for_each_set_bit(p, &reg, 32) {
 469                         girq = irq_find_mapping(gc->irqdomain, i * 32 + p);
 470                         generic_handle_irq(girq);
 471                 }
 472
 473         }
 474
 475         chained_irq_exit(ic, desc);
 476 }
 477
 478 static struct irq_chip aspeed_gpio_irqchip = {
 479         .name           = "aspeed-gpio",
 480         .irq_ack        = aspeed_gpio_irq_ack,
 481         .irq_mask       = aspeed_gpio_irq_mask,
 482         .irq_unmask     = aspeed_gpio_irq_unmask,
 483         .irq_set_type   = aspeed_gpio_set_type,
 484 };
 485
 486 static void set_irq_valid_mask(struct aspeed_gpio *gpio)
 487 {
 488         const struct aspeed_bank_props *props = gpio->config->props;
 489
 490         while (!is_bank_props_sentinel(props)) {
 491                 unsigned int offset;
 492                 const unsigned long int input = props->input;
 493
 494                 /* Pretty crummy approach, but similar to GPIO core */
 495                 for_each_clear_bit(offset, &input, 32) {
 496                         unsigned int i = props->bank * 32 + offset;
 497
 498                         if (i >= gpio->config->nr_gpios)
 499                                 break;
 500
 501                         clear_bit(i, gpio->chip.irq_valid_mask);
 502                 }
 503
 504                 props++;
 505         }
 506 }
 507
 508 static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
 509                 struct platform_device *pdev)
 510 {
 511         int rc;
 512
 513         rc = platform_get_irq(pdev, 0);
 514         if (rc < 0)
 515                 return rc;
 516
 517         gpio->irq = rc;
 518
 519         set_irq_valid_mask(gpio);
 520
 521         rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip,
 522                         0, handle_bad_irq, IRQ_TYPE_NONE);
 523         if (rc) {
 524                 dev_info(&pdev->dev, "Could not add irqchip\n");
 525                 return rc;
 526         }
 527
 528         gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip,
 529                                      gpio->irq, aspeed_gpio_irq_handler);
 530
 531         return 0;
 532 }
 533
 534 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
 535 {
 536         if (!have_gpio(gpiochip_get_data(chip), offset))
 537                 return -ENODEV;
 538
 539         return pinctrl_request_gpio(chip->base + offset);
 540 }
 541
 542 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
 543 {
 544         pinctrl_free_gpio(chip->base + offset);
 545 }
 546
 547 static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio,
 548                 const struct aspeed_gpio_bank *bank,
 549                 unsigned int reg)
 550 {
 551         return gpio->base + bank->debounce_regs + reg;
 552 }
 553
 554 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
 555                 u32 *cycles)
 556 {
 557         u64 rate;
 558         u64 n;
 559         u32 r;
 560
 561         rate = clk_get_rate(gpio->clk);
 562         if (!rate)
 563                 return -ENOTSUPP;
 564
 565         n = rate * usecs;
 566         r = do_div(n, 1000000);
 567
 568         if (n >= U32_MAX)
 569                 return -ERANGE;
 570
 571         /* At least as long as the requested time */
 572         *cycles = n + (!!r);
 573
 574         return 0;
 575 }
 576
 577 /* Call under gpio->lock */
 578 static int register_allocated_timer(struct aspeed_gpio *gpio,
 579                 unsigned int offset, unsigned int timer)
 580 {
 581         if (WARN(gpio->offset_timer[offset] != 0,
 582                                 "Offset %d already allocated timer %d\n",
 583                                 offset, gpio->offset_timer[offset]))
 584                 return -EINVAL;
 585
 586         if (WARN(gpio->timer_users[timer] == UINT_MAX,
 587                                 "Timer user count would overflow\n"))
 588                 return -EPERM;
 589
 590         gpio->offset_timer[offset] = timer;
 591         gpio->timer_users[timer]++;
 592
 593         return 0;
 594 }
 595
 596 /* Call under gpio->lock */
 597 static int unregister_allocated_timer(struct aspeed_gpio *gpio,
 598                 unsigned int offset)
 599 {
 600         if (WARN(gpio->offset_timer[offset] == 0,
 601                                 "No timer allocated to offset %d\n", offset))
 602                 return -EINVAL;
 603
 604         if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
 605                                 "No users recorded for timer %d\n",
 606                                 gpio->offset_timer[offset]))
 607                 return -EINVAL;
 608
 609         gpio->timer_users[gpio->offset_timer[offset]]--;
 610         gpio->offset_timer[offset] = 0;
 611
 612         return 0;
 613 }
 614
 615 /* Call under gpio->lock */
 616 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
 617                 unsigned int offset)
 618 {
 619         return gpio->offset_timer[offset] > 0;
 620 }
 621
 622 /* Call under gpio->lock */
 623 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
 624                 unsigned int timer)
 625 {
 626         const struct aspeed_gpio_bank *bank = to_bank(offset);
 627         const u32 mask = GPIO_BIT(offset);
 628         void __iomem *addr;
 629         u32 val;
 630
 631         addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL1);
 632         val = ioread32(addr);
 633         iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
 634
 635         addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL2);
 636         val = ioread32(addr);
 637         iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
 638 }
 639
 640 static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
 641                                     unsigned long usecs)
 642 {
 643         struct aspeed_gpio *gpio = gpiochip_get_data(chip);
 644         u32 requested_cycles;
 645         unsigned long flags;
 646         int rc;
 647         int i;
 648
 649         rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
 650         if (rc < 0) {
 651                 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
 652                                 usecs, clk_get_rate(gpio->clk), rc);
 653                 return rc;
 654         }
 655
 656         spin_lock_irqsave(&gpio->lock, flags);
 657
 658         if (timer_allocation_registered(gpio, offset)) {
 659                 rc = unregister_allocated_timer(gpio, offset);
 660                 if (rc < 0)
 661                         goto out;
 662         }
 663
 664         /* Try to find a timer already configured for the debounce period */
 665         for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
 666                 u32 cycles;
 667
 668                 cycles = ioread32(gpio->base + debounce_timers[i]);
 669                 if (requested_cycles == cycles)
 670                         break;
 671         }
 672
 673         if (i == ARRAY_SIZE(debounce_timers)) {
 674                 int j;
 675
 676                 /*
 677                  * As there are no timers configured for the requested debounce
 678                  * period, find an unused timer instead
 679                  */
 680                 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
 681                         if (gpio->timer_users[j] == 0)
 682                                 break;
 683                 }
 684
 685                 if (j == ARRAY_SIZE(gpio->timer_users)) {
 686                         dev_warn(chip->parent,
 687                                         "Debounce timers exhausted, cannot debounce for period %luus\n",
 688                                         usecs);
 689
 690                         rc = -EPERM;
 691
 692                         /*
 693                          * We already adjusted the accounting to remove @offset
 694                          * as a user of its previous timer, so also configure
 695                          * the hardware so @offset has timers disabled for
 696                          * consistency.
 697                          */
 698                         configure_timer(gpio, offset, 0);
 699                         goto out;
 700                 }
 701
 702                 i = j;
 703
 704                 iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
 705         }
 706
 707         if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
 708                 rc = -EINVAL;
 709                 goto out;
 710         }
 711
 712         register_allocated_timer(gpio, offset, i);
 713         configure_timer(gpio, offset, i);
 714
 715 out:
 716         spin_unlock_irqrestore(&gpio->lock, flags);
 717
 718         return rc;
 719 }
 720
 721 static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
 722 {
 723         struct aspeed_gpio *gpio = gpiochip_get_data(chip);
 724         unsigned long flags;
 725         int rc;
 726
 727         spin_lock_irqsave(&gpio->lock, flags);
 728
 729         rc = unregister_allocated_timer(gpio, offset);
 730         if (!rc)
 731                 configure_timer(gpio, offset, 0);
 732
 733         spin_unlock_irqrestore(&gpio->lock, flags);
 734
 735         return rc;
 736 }
 737
 738 static int set_debounce(struct gpio_chip *chip, unsigned int offset,
 739                                     unsigned long usecs)
 740 {
 741         struct aspeed_gpio *gpio = gpiochip_get_data(chip);
 742
 743         if (!have_debounce(gpio, offset))
 744                 return -ENOTSUPP;
 745
 746         if (usecs)
 747                 return enable_debounce(chip, offset, usecs);
 748
 749         return disable_debounce(chip, offset);
 750 }
 751
 752 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
 753                                   unsigned long config)
 754 {
 755         unsigned long param = pinconf_to_config_param(config);
 756         u32 arg = pinconf_to_config_argument(config);
 757
 758         if (param == PIN_CONFIG_INPUT_DEBOUNCE)
 759                 return set_debounce(chip, offset, arg);
 760         else if (param == PIN_CONFIG_BIAS_DISABLE ||
 761                         param == PIN_CONFIG_BIAS_PULL_DOWN ||
 762                         param == PIN_CONFIG_DRIVE_STRENGTH)
 763                 return pinctrl_gpio_set_config(offset, config);
 764         else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
 765                         param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
 766                 /* Return -ENOTSUPP to trigger emulation, as per datasheet */
 767                 return -ENOTSUPP;
 768
 769         return -ENOTSUPP;
 770 }
 771
 772 /*
 773  * Any banks not specified in a struct aspeed_bank_props array are assumed to
 774  * have the properties:
 775  *
 776  *     { .input = 0xffffffff, .output = 0xffffffff }
 777  */
 778
 779 static const struct aspeed_bank_props ast2400_bank_props[] = {
 780         /*     input      output   */
 781         { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
 782         { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
 783         { },
 784 };
 785
 786 static const struct aspeed_gpio_config ast2400_config =
 787         /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
 788         { .nr_gpios = 220, .props = ast2400_bank_props, };
 789
 790 static const struct aspeed_bank_props ast2500_bank_props[] = {
 791         /*     input      output   */
 792         { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
 793         { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
 794         { 7, 0x000000ff, 0x000000ff }, /* AC */
 795         { },
 796 };
 797
 798 static const struct aspeed_gpio_config ast2500_config =
 799         /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
 800         { .nr_gpios = 232, .props = ast2500_bank_props, };
 801
 802 static const struct of_device_id aspeed_gpio_of_table[] = {
 803         { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
 804         { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
 805         {}
 806 };
 807 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
 808
 809 static int __init aspeed_gpio_probe(struct platform_device *pdev)
 810 {
 811         const struct of_device_id *gpio_id;
 812         struct aspeed_gpio *gpio;
 813         struct resource *res;
 814         int rc;
 815
 816         gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 817         if (!gpio)
 818                 return -ENOMEM;
 819
 820         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 821         gpio->base = devm_ioremap_resource(&pdev->dev, res);
 822         if (IS_ERR(gpio->base))
 823                 return PTR_ERR(gpio->base);
 824
 825         spin_lock_init(&gpio->lock);
 826
 827         gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
 828         if (!gpio_id)
 829                 return -EINVAL;
 830
 831         gpio->clk = of_clk_get(pdev->dev.of_node, 0);
 832         if (IS_ERR(gpio->clk)) {
 833                 dev_warn(&pdev->dev,
 834                                 "No HPLL clock phandle provided, debouncing disabled\n");
 835                 gpio->clk = NULL;
 836         }
 837
 838         gpio->config = gpio_id->data;
 839
 840         gpio->chip.parent = &pdev->dev;
 841         gpio->chip.ngpio = gpio->config->nr_gpios;
 842         gpio->chip.parent = &pdev->dev;
 843         gpio->chip.direction_input = aspeed_gpio_dir_in;
 844         gpio->chip.direction_output = aspeed_gpio_dir_out;
 845         gpio->chip.get_direction = aspeed_gpio_get_direction;
 846         gpio->chip.request = aspeed_gpio_request;
 847         gpio->chip.free = aspeed_gpio_free;
 848         gpio->chip.get = aspeed_gpio_get;
 849         gpio->chip.set = aspeed_gpio_set;
 850         gpio->chip.set_config = aspeed_gpio_set_config;
 851         gpio->chip.label = dev_name(&pdev->dev);
 852         gpio->chip.base = -1;
 853         gpio->chip.irq_need_valid_mask = true;
 854
 855         rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
 856         if (rc < 0)
 857                 return rc;
 858
 859         gpio->offset_timer =
 860                 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
 861
 862         return aspeed_gpio_setup_irqs(gpio, pdev);
 863 }
 864
 865 static struct platform_driver aspeed_gpio_driver = {
 866         .driver = {
 867                 .name = KBUILD_MODNAME,
 868                 .of_match_table = aspeed_gpio_of_table,
 869         },
 870 };
 871
 872 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
 873
 874 MODULE_DESCRIPTION("Aspeed GPIO Driver");
 875 MODULE_LICENSE("GPL");