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Merge tag 'for-linus-5.15-1' of git://github.com/cminyard/linux-ipmi
[mirror_ubuntu-jammy-kernel.git] / drivers / gpio / gpio-aspeed.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2015 IBM Corp.
4 *
5 * Joel Stanley <joel@jms.id.au>
6 */
7
8 #include <asm/div64.h>
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/aspeed.h>
12 #include <linux/hashtable.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
21
22 /*
23 * These two headers aren't meant to be used by GPIO drivers. We need
24 * them in order to access gpio_chip_hwgpio() which we need to implement
25 * the aspeed specific API which allows the coprocessor to request
26 * access to some GPIOs and to arbitrate between coprocessor and ARM.
27 */
28 #include <linux/gpio/consumer.h>
29 #include "gpiolib.h"
30
31 struct aspeed_bank_props {
32 unsigned int bank;
33 u32 input;
34 u32 output;
35 };
36
37 struct aspeed_gpio_config {
38 unsigned int nr_gpios;
39 const struct aspeed_bank_props *props;
40 };
41
42 /*
43 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
44 * @timer_users: Tracks the number of users for each timer
45 *
46 * The @timer_users has four elements but the first element is unused. This is
47 * to simplify accounting and indexing, as a zero value in @offset_timer
48 * represents disabled debouncing for the GPIO. Any other value for an element
49 * of @offset_timer is used as an index into @timer_users. This behaviour of
50 * the zero value aligns with the behaviour of zero built from the timer
51 * configuration registers (i.e. debouncing is disabled).
52 */
53 struct aspeed_gpio {
54 struct gpio_chip chip;
55 struct irq_chip irqc;
56 spinlock_t lock;
57 void __iomem *base;
58 int irq;
59 const struct aspeed_gpio_config *config;
60
61 u8 *offset_timer;
62 unsigned int timer_users[4];
63 struct clk *clk;
64
65 u32 *dcache;
66 u8 *cf_copro_bankmap;
67 };
68
69 struct aspeed_gpio_bank {
70 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
71 * +4: Rd/Wr: Direction (0=in, 1=out)
72 */
73 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
74 uint16_t irq_regs;
75 uint16_t debounce_regs;
76 uint16_t tolerance_regs;
77 uint16_t cmdsrc_regs;
78 const char names[4][3];
79 };
80
81 /*
82 * Note: The "value" register returns the input value sampled on the
83 * line even when the GPIO is configured as an output. Since
84 * that input goes through synchronizers, writing, then reading
85 * back may not return the written value right away.
86 *
87 * The "rdata" register returns the content of the write latch
88 * and thus can be used to read back what was last written
89 * reliably.
90 */
91
92 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
93
94 static const struct aspeed_gpio_copro_ops *copro_ops;
95 static void *copro_data;
96
97 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
98 {
99 .val_regs = 0x0000,
100 .rdata_reg = 0x00c0,
101 .irq_regs = 0x0008,
102 .debounce_regs = 0x0040,
103 .tolerance_regs = 0x001c,
104 .cmdsrc_regs = 0x0060,
105 .names = { "A", "B", "C", "D" },
106 },
107 {
108 .val_regs = 0x0020,
109 .rdata_reg = 0x00c4,
110 .irq_regs = 0x0028,
111 .debounce_regs = 0x0048,
112 .tolerance_regs = 0x003c,
113 .cmdsrc_regs = 0x0068,
114 .names = { "E", "F", "G", "H" },
115 },
116 {
117 .val_regs = 0x0070,
118 .rdata_reg = 0x00c8,
119 .irq_regs = 0x0098,
120 .debounce_regs = 0x00b0,
121 .tolerance_regs = 0x00ac,
122 .cmdsrc_regs = 0x0090,
123 .names = { "I", "J", "K", "L" },
124 },
125 {
126 .val_regs = 0x0078,
127 .rdata_reg = 0x00cc,
128 .irq_regs = 0x00e8,
129 .debounce_regs = 0x0100,
130 .tolerance_regs = 0x00fc,
131 .cmdsrc_regs = 0x00e0,
132 .names = { "M", "N", "O", "P" },
133 },
134 {
135 .val_regs = 0x0080,
136 .rdata_reg = 0x00d0,
137 .irq_regs = 0x0118,
138 .debounce_regs = 0x0130,
139 .tolerance_regs = 0x012c,
140 .cmdsrc_regs = 0x0110,
141 .names = { "Q", "R", "S", "T" },
142 },
143 {
144 .val_regs = 0x0088,
145 .rdata_reg = 0x00d4,
146 .irq_regs = 0x0148,
147 .debounce_regs = 0x0160,
148 .tolerance_regs = 0x015c,
149 .cmdsrc_regs = 0x0140,
150 .names = { "U", "V", "W", "X" },
151 },
152 {
153 .val_regs = 0x01E0,
154 .rdata_reg = 0x00d8,
155 .irq_regs = 0x0178,
156 .debounce_regs = 0x0190,
157 .tolerance_regs = 0x018c,
158 .cmdsrc_regs = 0x0170,
159 .names = { "Y", "Z", "AA", "AB" },
160 },
161 {
162 .val_regs = 0x01e8,
163 .rdata_reg = 0x00dc,
164 .irq_regs = 0x01a8,
165 .debounce_regs = 0x01c0,
166 .tolerance_regs = 0x01bc,
167 .cmdsrc_regs = 0x01a0,
168 .names = { "AC", "", "", "" },
169 },
170 };
171
172 enum aspeed_gpio_reg {
173 reg_val,
174 reg_rdata,
175 reg_dir,
176 reg_irq_enable,
177 reg_irq_type0,
178 reg_irq_type1,
179 reg_irq_type2,
180 reg_irq_status,
181 reg_debounce_sel1,
182 reg_debounce_sel2,
183 reg_tolerance,
184 reg_cmdsrc0,
185 reg_cmdsrc1,
186 };
187
188 #define GPIO_VAL_VALUE 0x00
189 #define GPIO_VAL_DIR 0x04
190
191 #define GPIO_IRQ_ENABLE 0x00
192 #define GPIO_IRQ_TYPE0 0x04
193 #define GPIO_IRQ_TYPE1 0x08
194 #define GPIO_IRQ_TYPE2 0x0c
195 #define GPIO_IRQ_STATUS 0x10
196
197 #define GPIO_DEBOUNCE_SEL1 0x00
198 #define GPIO_DEBOUNCE_SEL2 0x04
199
200 #define GPIO_CMDSRC_0 0x00
201 #define GPIO_CMDSRC_1 0x04
202 #define GPIO_CMDSRC_ARM 0
203 #define GPIO_CMDSRC_LPC 1
204 #define GPIO_CMDSRC_COLDFIRE 2
205 #define GPIO_CMDSRC_RESERVED 3
206
207 /* This will be resolved at compile time */
208 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
209 const struct aspeed_gpio_bank *bank,
210 const enum aspeed_gpio_reg reg)
211 {
212 switch (reg) {
213 case reg_val:
214 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
215 case reg_rdata:
216 return gpio->base + bank->rdata_reg;
217 case reg_dir:
218 return gpio->base + bank->val_regs + GPIO_VAL_DIR;
219 case reg_irq_enable:
220 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
221 case reg_irq_type0:
222 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
223 case reg_irq_type1:
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
225 case reg_irq_type2:
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
227 case reg_irq_status:
228 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
229 case reg_debounce_sel1:
230 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
231 case reg_debounce_sel2:
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
233 case reg_tolerance:
234 return gpio->base + bank->tolerance_regs;
235 case reg_cmdsrc0:
236 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
237 case reg_cmdsrc1:
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
239 }
240 BUG();
241 }
242
243 #define GPIO_BANK(x) ((x) >> 5)
244 #define GPIO_OFFSET(x) ((x) & 0x1f)
245 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
246
247 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
248 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
249 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
250
251 static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
252 {
253 unsigned int bank = GPIO_BANK(offset);
254
255 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
256 return &aspeed_gpio_banks[bank];
257 }
258
259 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
260 {
261 return !(props->input || props->output);
262 }
263
264 static inline const struct aspeed_bank_props *find_bank_props(
265 struct aspeed_gpio *gpio, unsigned int offset)
266 {
267 const struct aspeed_bank_props *props = gpio->config->props;
268
269 while (!is_bank_props_sentinel(props)) {
270 if (props->bank == GPIO_BANK(offset))
271 return props;
272 props++;
273 }
274
275 return NULL;
276 }
277
278 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
279 {
280 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
281 const struct aspeed_gpio_bank *bank = to_bank(offset);
282 unsigned int group = GPIO_OFFSET(offset) / 8;
283
284 return bank->names[group][0] != '\0' &&
285 (!props || ((props->input | props->output) & GPIO_BIT(offset)));
286 }
287
288 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
289 {
290 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
291
292 return !props || (props->input & GPIO_BIT(offset));
293 }
294
295 #define have_irq(g, o) have_input((g), (o))
296 #define have_debounce(g, o) have_input((g), (o))
297
298 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
299 {
300 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
301
302 return !props || (props->output & GPIO_BIT(offset));
303 }
304
305 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
306 const struct aspeed_gpio_bank *bank,
307 int bindex, int cmdsrc)
308 {
309 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
310 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
311 u32 bit, reg;
312
313 /*
314 * Each register controls 4 banks, so take the bottom 2
315 * bits of the bank index, and use them to select the
316 * right control bit (0, 8, 16 or 24).
317 */
318 bit = BIT((bindex & 3) << 3);
319
320 /* Source 1 first to avoid illegal 11 combination */
321 reg = ioread32(c1);
322 if (cmdsrc & 2)
323 reg |= bit;
324 else
325 reg &= ~bit;
326 iowrite32(reg, c1);
327
328 /* Then Source 0 */
329 reg = ioread32(c0);
330 if (cmdsrc & 1)
331 reg |= bit;
332 else
333 reg &= ~bit;
334 iowrite32(reg, c0);
335 }
336
337 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
338 unsigned int offset)
339 {
340 const struct aspeed_gpio_bank *bank = to_bank(offset);
341
342 if (!copro_ops || !gpio->cf_copro_bankmap)
343 return false;
344 if (!gpio->cf_copro_bankmap[offset >> 3])
345 return false;
346 if (!copro_ops->request_access)
347 return false;
348
349 /* Pause the coprocessor */
350 copro_ops->request_access(copro_data);
351
352 /* Change command source back to ARM */
353 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
354
355 /* Update cache */
356 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
357
358 return true;
359 }
360
361 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
362 unsigned int offset)
363 {
364 const struct aspeed_gpio_bank *bank = to_bank(offset);
365
366 if (!copro_ops || !gpio->cf_copro_bankmap)
367 return;
368 if (!gpio->cf_copro_bankmap[offset >> 3])
369 return;
370 if (!copro_ops->release_access)
371 return;
372
373 /* Change command source back to ColdFire */
374 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
375 GPIO_CMDSRC_COLDFIRE);
376
377 /* Restart the coprocessor */
378 copro_ops->release_access(copro_data);
379 }
380
381 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
382 {
383 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
384 const struct aspeed_gpio_bank *bank = to_bank(offset);
385
386 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
387 }
388
389 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
390 int val)
391 {
392 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
393 const struct aspeed_gpio_bank *bank = to_bank(offset);
394 void __iomem *addr;
395 u32 reg;
396
397 addr = bank_reg(gpio, bank, reg_val);
398 reg = gpio->dcache[GPIO_BANK(offset)];
399
400 if (val)
401 reg |= GPIO_BIT(offset);
402 else
403 reg &= ~GPIO_BIT(offset);
404 gpio->dcache[GPIO_BANK(offset)] = reg;
405
406 iowrite32(reg, addr);
407 }
408
409 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
410 int val)
411 {
412 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
413 unsigned long flags;
414 bool copro;
415
416 spin_lock_irqsave(&gpio->lock, flags);
417 copro = aspeed_gpio_copro_request(gpio, offset);
418
419 __aspeed_gpio_set(gc, offset, val);
420
421 if (copro)
422 aspeed_gpio_copro_release(gpio, offset);
423 spin_unlock_irqrestore(&gpio->lock, flags);
424 }
425
426 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
427 {
428 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
429 const struct aspeed_gpio_bank *bank = to_bank(offset);
430 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
431 unsigned long flags;
432 bool copro;
433 u32 reg;
434
435 if (!have_input(gpio, offset))
436 return -ENOTSUPP;
437
438 spin_lock_irqsave(&gpio->lock, flags);
439
440 reg = ioread32(addr);
441 reg &= ~GPIO_BIT(offset);
442
443 copro = aspeed_gpio_copro_request(gpio, offset);
444 iowrite32(reg, addr);
445 if (copro)
446 aspeed_gpio_copro_release(gpio, offset);
447
448 spin_unlock_irqrestore(&gpio->lock, flags);
449
450 return 0;
451 }
452
453 static int aspeed_gpio_dir_out(struct gpio_chip *gc,
454 unsigned int offset, int val)
455 {
456 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
457 const struct aspeed_gpio_bank *bank = to_bank(offset);
458 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
459 unsigned long flags;
460 bool copro;
461 u32 reg;
462
463 if (!have_output(gpio, offset))
464 return -ENOTSUPP;
465
466 spin_lock_irqsave(&gpio->lock, flags);
467
468 reg = ioread32(addr);
469 reg |= GPIO_BIT(offset);
470
471 copro = aspeed_gpio_copro_request(gpio, offset);
472 __aspeed_gpio_set(gc, offset, val);
473 iowrite32(reg, addr);
474
475 if (copro)
476 aspeed_gpio_copro_release(gpio, offset);
477 spin_unlock_irqrestore(&gpio->lock, flags);
478
479 return 0;
480 }
481
482 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
483 {
484 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
485 const struct aspeed_gpio_bank *bank = to_bank(offset);
486 unsigned long flags;
487 u32 val;
488
489 if (!have_input(gpio, offset))
490 return GPIO_LINE_DIRECTION_OUT;
491
492 if (!have_output(gpio, offset))
493 return GPIO_LINE_DIRECTION_IN;
494
495 spin_lock_irqsave(&gpio->lock, flags);
496
497 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
498
499 spin_unlock_irqrestore(&gpio->lock, flags);
500
501 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
502 }
503
504 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
505 struct aspeed_gpio **gpio,
506 const struct aspeed_gpio_bank **bank,
507 u32 *bit, int *offset)
508 {
509 struct aspeed_gpio *internal;
510
511 *offset = irqd_to_hwirq(d);
512
513 internal = irq_data_get_irq_chip_data(d);
514
515 /* This might be a bit of a questionable place to check */
516 if (!have_irq(internal, *offset))
517 return -ENOTSUPP;
518
519 *gpio = internal;
520 *bank = to_bank(*offset);
521 *bit = GPIO_BIT(*offset);
522
523 return 0;
524 }
525
526 static void aspeed_gpio_irq_ack(struct irq_data *d)
527 {
528 const struct aspeed_gpio_bank *bank;
529 struct aspeed_gpio *gpio;
530 unsigned long flags;
531 void __iomem *status_addr;
532 int rc, offset;
533 bool copro;
534 u32 bit;
535
536 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
537 if (rc)
538 return;
539
540 status_addr = bank_reg(gpio, bank, reg_irq_status);
541
542 spin_lock_irqsave(&gpio->lock, flags);
543 copro = aspeed_gpio_copro_request(gpio, offset);
544
545 iowrite32(bit, status_addr);
546
547 if (copro)
548 aspeed_gpio_copro_release(gpio, offset);
549 spin_unlock_irqrestore(&gpio->lock, flags);
550 }
551
552 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
553 {
554 const struct aspeed_gpio_bank *bank;
555 struct aspeed_gpio *gpio;
556 unsigned long flags;
557 u32 reg, bit;
558 void __iomem *addr;
559 int rc, offset;
560 bool copro;
561
562 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
563 if (rc)
564 return;
565
566 addr = bank_reg(gpio, bank, reg_irq_enable);
567
568 spin_lock_irqsave(&gpio->lock, flags);
569 copro = aspeed_gpio_copro_request(gpio, offset);
570
571 reg = ioread32(addr);
572 if (set)
573 reg |= bit;
574 else
575 reg &= ~bit;
576 iowrite32(reg, addr);
577
578 if (copro)
579 aspeed_gpio_copro_release(gpio, offset);
580 spin_unlock_irqrestore(&gpio->lock, flags);
581 }
582
583 static void aspeed_gpio_irq_mask(struct irq_data *d)
584 {
585 aspeed_gpio_irq_set_mask(d, false);
586 }
587
588 static void aspeed_gpio_irq_unmask(struct irq_data *d)
589 {
590 aspeed_gpio_irq_set_mask(d, true);
591 }
592
593 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
594 {
595 u32 type0 = 0;
596 u32 type1 = 0;
597 u32 type2 = 0;
598 u32 bit, reg;
599 const struct aspeed_gpio_bank *bank;
600 irq_flow_handler_t handler;
601 struct aspeed_gpio *gpio;
602 unsigned long flags;
603 void __iomem *addr;
604 int rc, offset;
605 bool copro;
606
607 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
608 if (rc)
609 return -EINVAL;
610
611 switch (type & IRQ_TYPE_SENSE_MASK) {
612 case IRQ_TYPE_EDGE_BOTH:
613 type2 |= bit;
614 fallthrough;
615 case IRQ_TYPE_EDGE_RISING:
616 type0 |= bit;
617 fallthrough;
618 case IRQ_TYPE_EDGE_FALLING:
619 handler = handle_edge_irq;
620 break;
621 case IRQ_TYPE_LEVEL_HIGH:
622 type0 |= bit;
623 fallthrough;
624 case IRQ_TYPE_LEVEL_LOW:
625 type1 |= bit;
626 handler = handle_level_irq;
627 break;
628 default:
629 return -EINVAL;
630 }
631
632 spin_lock_irqsave(&gpio->lock, flags);
633 copro = aspeed_gpio_copro_request(gpio, offset);
634
635 addr = bank_reg(gpio, bank, reg_irq_type0);
636 reg = ioread32(addr);
637 reg = (reg & ~bit) | type0;
638 iowrite32(reg, addr);
639
640 addr = bank_reg(gpio, bank, reg_irq_type1);
641 reg = ioread32(addr);
642 reg = (reg & ~bit) | type1;
643 iowrite32(reg, addr);
644
645 addr = bank_reg(gpio, bank, reg_irq_type2);
646 reg = ioread32(addr);
647 reg = (reg & ~bit) | type2;
648 iowrite32(reg, addr);
649
650 if (copro)
651 aspeed_gpio_copro_release(gpio, offset);
652 spin_unlock_irqrestore(&gpio->lock, flags);
653
654 irq_set_handler_locked(d, handler);
655
656 return 0;
657 }
658
659 static void aspeed_gpio_irq_handler(struct irq_desc *desc)
660 {
661 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
662 struct irq_chip *ic = irq_desc_get_chip(desc);
663 struct aspeed_gpio *data = gpiochip_get_data(gc);
664 unsigned int i, p, banks;
665 unsigned long reg;
666 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
667
668 chained_irq_enter(ic, desc);
669
670 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
671 for (i = 0; i < banks; i++) {
672 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
673
674 reg = ioread32(bank_reg(data, bank, reg_irq_status));
675
676 for_each_set_bit(p, &reg, 32)
677 generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
678 }
679
680 chained_irq_exit(ic, desc);
681 }
682
683 static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
684 unsigned long *valid_mask,
685 unsigned int ngpios)
686 {
687 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
688 const struct aspeed_bank_props *props = gpio->config->props;
689
690 while (!is_bank_props_sentinel(props)) {
691 unsigned int offset;
692 const unsigned long int input = props->input;
693
694 /* Pretty crummy approach, but similar to GPIO core */
695 for_each_clear_bit(offset, &input, 32) {
696 unsigned int i = props->bank * 32 + offset;
697
698 if (i >= gpio->chip.ngpio)
699 break;
700
701 clear_bit(i, valid_mask);
702 }
703
704 props++;
705 }
706 }
707
708 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
709 unsigned int offset, bool enable)
710 {
711 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
712 unsigned long flags;
713 void __iomem *treg;
714 bool copro;
715 u32 val;
716
717 treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
718
719 spin_lock_irqsave(&gpio->lock, flags);
720 copro = aspeed_gpio_copro_request(gpio, offset);
721
722 val = readl(treg);
723
724 if (enable)
725 val |= GPIO_BIT(offset);
726 else
727 val &= ~GPIO_BIT(offset);
728
729 writel(val, treg);
730
731 if (copro)
732 aspeed_gpio_copro_release(gpio, offset);
733 spin_unlock_irqrestore(&gpio->lock, flags);
734
735 return 0;
736 }
737
738 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
739 {
740 if (!have_gpio(gpiochip_get_data(chip), offset))
741 return -ENODEV;
742
743 return pinctrl_gpio_request(chip->base + offset);
744 }
745
746 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
747 {
748 pinctrl_gpio_free(chip->base + offset);
749 }
750
751 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
752 u32 *cycles)
753 {
754 u64 rate;
755 u64 n;
756 u32 r;
757
758 rate = clk_get_rate(gpio->clk);
759 if (!rate)
760 return -ENOTSUPP;
761
762 n = rate * usecs;
763 r = do_div(n, 1000000);
764
765 if (n >= U32_MAX)
766 return -ERANGE;
767
768 /* At least as long as the requested time */
769 *cycles = n + (!!r);
770
771 return 0;
772 }
773
774 /* Call under gpio->lock */
775 static int register_allocated_timer(struct aspeed_gpio *gpio,
776 unsigned int offset, unsigned int timer)
777 {
778 if (WARN(gpio->offset_timer[offset] != 0,
779 "Offset %d already allocated timer %d\n",
780 offset, gpio->offset_timer[offset]))
781 return -EINVAL;
782
783 if (WARN(gpio->timer_users[timer] == UINT_MAX,
784 "Timer user count would overflow\n"))
785 return -EPERM;
786
787 gpio->offset_timer[offset] = timer;
788 gpio->timer_users[timer]++;
789
790 return 0;
791 }
792
793 /* Call under gpio->lock */
794 static int unregister_allocated_timer(struct aspeed_gpio *gpio,
795 unsigned int offset)
796 {
797 if (WARN(gpio->offset_timer[offset] == 0,
798 "No timer allocated to offset %d\n", offset))
799 return -EINVAL;
800
801 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
802 "No users recorded for timer %d\n",
803 gpio->offset_timer[offset]))
804 return -EINVAL;
805
806 gpio->timer_users[gpio->offset_timer[offset]]--;
807 gpio->offset_timer[offset] = 0;
808
809 return 0;
810 }
811
812 /* Call under gpio->lock */
813 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
814 unsigned int offset)
815 {
816 return gpio->offset_timer[offset] > 0;
817 }
818
819 /* Call under gpio->lock */
820 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
821 unsigned int timer)
822 {
823 const struct aspeed_gpio_bank *bank = to_bank(offset);
824 const u32 mask = GPIO_BIT(offset);
825 void __iomem *addr;
826 u32 val;
827
828 /* Note: Debounce timer isn't under control of the command
829 * source registers, so no need to sync with the coprocessor
830 */
831 addr = bank_reg(gpio, bank, reg_debounce_sel1);
832 val = ioread32(addr);
833 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
834
835 addr = bank_reg(gpio, bank, reg_debounce_sel2);
836 val = ioread32(addr);
837 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
838 }
839
840 static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
841 unsigned long usecs)
842 {
843 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
844 u32 requested_cycles;
845 unsigned long flags;
846 int rc;
847 int i;
848
849 if (!gpio->clk)
850 return -EINVAL;
851
852 rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
853 if (rc < 0) {
854 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
855 usecs, clk_get_rate(gpio->clk), rc);
856 return rc;
857 }
858
859 spin_lock_irqsave(&gpio->lock, flags);
860
861 if (timer_allocation_registered(gpio, offset)) {
862 rc = unregister_allocated_timer(gpio, offset);
863 if (rc < 0)
864 goto out;
865 }
866
867 /* Try to find a timer already configured for the debounce period */
868 for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
869 u32 cycles;
870
871 cycles = ioread32(gpio->base + debounce_timers[i]);
872 if (requested_cycles == cycles)
873 break;
874 }
875
876 if (i == ARRAY_SIZE(debounce_timers)) {
877 int j;
878
879 /*
880 * As there are no timers configured for the requested debounce
881 * period, find an unused timer instead
882 */
883 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
884 if (gpio->timer_users[j] == 0)
885 break;
886 }
887
888 if (j == ARRAY_SIZE(gpio->timer_users)) {
889 dev_warn(chip->parent,
890 "Debounce timers exhausted, cannot debounce for period %luus\n",
891 usecs);
892
893 rc = -EPERM;
894
895 /*
896 * We already adjusted the accounting to remove @offset
897 * as a user of its previous timer, so also configure
898 * the hardware so @offset has timers disabled for
899 * consistency.
900 */
901 configure_timer(gpio, offset, 0);
902 goto out;
903 }
904
905 i = j;
906
907 iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
908 }
909
910 if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
911 rc = -EINVAL;
912 goto out;
913 }
914
915 register_allocated_timer(gpio, offset, i);
916 configure_timer(gpio, offset, i);
917
918 out:
919 spin_unlock_irqrestore(&gpio->lock, flags);
920
921 return rc;
922 }
923
924 static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
925 {
926 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
927 unsigned long flags;
928 int rc;
929
930 spin_lock_irqsave(&gpio->lock, flags);
931
932 rc = unregister_allocated_timer(gpio, offset);
933 if (!rc)
934 configure_timer(gpio, offset, 0);
935
936 spin_unlock_irqrestore(&gpio->lock, flags);
937
938 return rc;
939 }
940
941 static int set_debounce(struct gpio_chip *chip, unsigned int offset,
942 unsigned long usecs)
943 {
944 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
945
946 if (!have_debounce(gpio, offset))
947 return -ENOTSUPP;
948
949 if (usecs)
950 return enable_debounce(chip, offset, usecs);
951
952 return disable_debounce(chip, offset);
953 }
954
955 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
956 unsigned long config)
957 {
958 unsigned long param = pinconf_to_config_param(config);
959 u32 arg = pinconf_to_config_argument(config);
960
961 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
962 return set_debounce(chip, offset, arg);
963 else if (param == PIN_CONFIG_BIAS_DISABLE ||
964 param == PIN_CONFIG_BIAS_PULL_DOWN ||
965 param == PIN_CONFIG_DRIVE_STRENGTH)
966 return pinctrl_gpio_set_config(offset, config);
967 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
968 param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
969 /* Return -ENOTSUPP to trigger emulation, as per datasheet */
970 return -ENOTSUPP;
971 else if (param == PIN_CONFIG_PERSIST_STATE)
972 return aspeed_gpio_reset_tolerance(chip, offset, arg);
973
974 return -ENOTSUPP;
975 }
976
977 /**
978 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
979 * the coprocessor for shared GPIO banks
980 * @ops: The callbacks
981 * @data: Pointer passed back to the callbacks
982 */
983 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
984 {
985 copro_data = data;
986 copro_ops = ops;
987
988 return 0;
989 }
990 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
991
992 /**
993 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
994 * bank gets marked and any access from the ARM will
995 * result in handshaking via callbacks.
996 * @desc: The GPIO to be marked
997 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
998 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
999 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1000 */
1001 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
1002 u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
1003 {
1004 struct gpio_chip *chip = gpiod_to_chip(desc);
1005 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1006 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1007 const struct aspeed_gpio_bank *bank = to_bank(offset);
1008 unsigned long flags;
1009
1010 if (!gpio->cf_copro_bankmap)
1011 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
1012 if (!gpio->cf_copro_bankmap)
1013 return -ENOMEM;
1014 if (offset < 0 || offset > gpio->chip.ngpio)
1015 return -EINVAL;
1016 bindex = offset >> 3;
1017
1018 spin_lock_irqsave(&gpio->lock, flags);
1019
1020 /* Sanity check, this shouldn't happen */
1021 if (gpio->cf_copro_bankmap[bindex] == 0xff) {
1022 rc = -EIO;
1023 goto bail;
1024 }
1025 gpio->cf_copro_bankmap[bindex]++;
1026
1027 /* Switch command source */
1028 if (gpio->cf_copro_bankmap[bindex] == 1)
1029 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1030 GPIO_CMDSRC_COLDFIRE);
1031
1032 if (vreg_offset)
1033 *vreg_offset = bank->val_regs;
1034 if (dreg_offset)
1035 *dreg_offset = bank->rdata_reg;
1036 if (bit)
1037 *bit = GPIO_OFFSET(offset);
1038 bail:
1039 spin_unlock_irqrestore(&gpio->lock, flags);
1040 return rc;
1041 }
1042 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
1043
1044 /**
1045 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1046 * @desc: The GPIO to be marked
1047 */
1048 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
1049 {
1050 struct gpio_chip *chip = gpiod_to_chip(desc);
1051 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1052 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1053 const struct aspeed_gpio_bank *bank = to_bank(offset);
1054 unsigned long flags;
1055
1056 if (!gpio->cf_copro_bankmap)
1057 return -ENXIO;
1058
1059 if (offset < 0 || offset > gpio->chip.ngpio)
1060 return -EINVAL;
1061 bindex = offset >> 3;
1062
1063 spin_lock_irqsave(&gpio->lock, flags);
1064
1065 /* Sanity check, this shouldn't happen */
1066 if (gpio->cf_copro_bankmap[bindex] == 0) {
1067 rc = -EIO;
1068 goto bail;
1069 }
1070 gpio->cf_copro_bankmap[bindex]--;
1071
1072 /* Switch command source */
1073 if (gpio->cf_copro_bankmap[bindex] == 0)
1074 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1075 GPIO_CMDSRC_ARM);
1076 bail:
1077 spin_unlock_irqrestore(&gpio->lock, flags);
1078 return rc;
1079 }
1080 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
1081
1082 /*
1083 * Any banks not specified in a struct aspeed_bank_props array are assumed to
1084 * have the properties:
1085 *
1086 * { .input = 0xffffffff, .output = 0xffffffff }
1087 */
1088
1089 static const struct aspeed_bank_props ast2400_bank_props[] = {
1090 /* input output */
1091 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1092 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1093 { },
1094 };
1095
1096 static const struct aspeed_gpio_config ast2400_config =
1097 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1098 { .nr_gpios = 220, .props = ast2400_bank_props, };
1099
1100 static const struct aspeed_bank_props ast2500_bank_props[] = {
1101 /* input output */
1102 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1103 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1104 { 7, 0x000000ff, 0x000000ff }, /* AC */
1105 { },
1106 };
1107
1108 static const struct aspeed_gpio_config ast2500_config =
1109 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1110 { .nr_gpios = 232, .props = ast2500_bank_props, };
1111
1112 static const struct aspeed_bank_props ast2600_bank_props[] = {
1113 /* input output */
1114 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */
1115 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
1116 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
1117 { },
1118 };
1119
1120 static const struct aspeed_gpio_config ast2600_config =
1121 /*
1122 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
1123 * We expect ngpio being set in the device tree and this is a fallback
1124 * option.
1125 */
1126 { .nr_gpios = 208, .props = ast2600_bank_props, };
1127
1128 static const struct of_device_id aspeed_gpio_of_table[] = {
1129 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1130 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1131 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1132 {}
1133 };
1134 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
1135
1136 static int __init aspeed_gpio_probe(struct platform_device *pdev)
1137 {
1138 const struct of_device_id *gpio_id;
1139 struct aspeed_gpio *gpio;
1140 int rc, i, banks, err;
1141 u32 ngpio;
1142
1143 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
1144 if (!gpio)
1145 return -ENOMEM;
1146
1147 gpio->base = devm_platform_ioremap_resource(pdev, 0);
1148 if (IS_ERR(gpio->base))
1149 return PTR_ERR(gpio->base);
1150
1151 spin_lock_init(&gpio->lock);
1152
1153 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
1154 if (!gpio_id)
1155 return -EINVAL;
1156
1157 gpio->clk = of_clk_get(pdev->dev.of_node, 0);
1158 if (IS_ERR(gpio->clk)) {
1159 dev_warn(&pdev->dev,
1160 "Failed to get clock from devicetree, debouncing disabled\n");
1161 gpio->clk = NULL;
1162 }
1163
1164 gpio->config = gpio_id->data;
1165
1166 gpio->chip.parent = &pdev->dev;
1167 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
1168 gpio->chip.ngpio = (u16) ngpio;
1169 if (err)
1170 gpio->chip.ngpio = gpio->config->nr_gpios;
1171 gpio->chip.direction_input = aspeed_gpio_dir_in;
1172 gpio->chip.direction_output = aspeed_gpio_dir_out;
1173 gpio->chip.get_direction = aspeed_gpio_get_direction;
1174 gpio->chip.request = aspeed_gpio_request;
1175 gpio->chip.free = aspeed_gpio_free;
1176 gpio->chip.get = aspeed_gpio_get;
1177 gpio->chip.set = aspeed_gpio_set;
1178 gpio->chip.set_config = aspeed_gpio_set_config;
1179 gpio->chip.label = dev_name(&pdev->dev);
1180 gpio->chip.base = -1;
1181
1182 /* Allocate a cache of the output registers */
1183 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
1184 gpio->dcache = devm_kcalloc(&pdev->dev,
1185 banks, sizeof(u32), GFP_KERNEL);
1186 if (!gpio->dcache)
1187 return -ENOMEM;
1188
1189 /*
1190 * Populate it with initial values read from the HW and switch
1191 * all command sources to the ARM by default
1192 */
1193 for (i = 0; i < banks; i++) {
1194 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
1195 void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
1196 gpio->dcache[i] = ioread32(addr);
1197 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
1198 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
1199 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
1200 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
1201 }
1202
1203 /* Optionally set up an irqchip if there is an IRQ */
1204 rc = platform_get_irq(pdev, 0);
1205 if (rc > 0) {
1206 struct gpio_irq_chip *girq;
1207
1208 gpio->irq = rc;
1209 girq = &gpio->chip.irq;
1210 girq->chip = &gpio->irqc;
1211 girq->chip->name = dev_name(&pdev->dev);
1212 girq->chip->irq_ack = aspeed_gpio_irq_ack;
1213 girq->chip->irq_mask = aspeed_gpio_irq_mask;
1214 girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
1215 girq->chip->irq_set_type = aspeed_gpio_set_type;
1216 girq->parent_handler = aspeed_gpio_irq_handler;
1217 girq->num_parents = 1;
1218 girq->parents = devm_kcalloc(&pdev->dev, 1,
1219 sizeof(*girq->parents),
1220 GFP_KERNEL);
1221 if (!girq->parents)
1222 return -ENOMEM;
1223 girq->parents[0] = gpio->irq;
1224 girq->default_type = IRQ_TYPE_NONE;
1225 girq->handler = handle_bad_irq;
1226 girq->init_valid_mask = aspeed_init_irq_valid_mask;
1227 }
1228
1229 gpio->offset_timer =
1230 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
1231 if (!gpio->offset_timer)
1232 return -ENOMEM;
1233
1234 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
1235 if (rc < 0)
1236 return rc;
1237
1238 return 0;
1239 }
1240
1241 static struct platform_driver aspeed_gpio_driver = {
1242 .driver = {
1243 .name = KBUILD_MODNAME,
1244 .of_match_table = aspeed_gpio_of_table,
1245 },
1246 };
1247
1248 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
1249
1250 MODULE_DESCRIPTION("Aspeed GPIO Driver");
1251 MODULE_LICENSE("GPL");
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