1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015 IBM Corp.
5 * Joel Stanley <joel@jms.id.au>
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/aspeed.h>
12 #include <linux/hashtable.h>
13 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
23 * These two headers aren't meant to be used by GPIO drivers. We need
24 * them in order to access gpio_chip_hwgpio() which we need to implement
25 * the aspeed specific API which allows the coprocessor to request
26 * access to some GPIOs and to arbitrate between coprocessor and ARM.
28 #include <linux/gpio/consumer.h>
31 struct aspeed_bank_props
{
37 struct aspeed_gpio_config
{
38 unsigned int nr_gpios
;
39 const struct aspeed_bank_props
*props
;
43 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
44 * @timer_users: Tracks the number of users for each timer
46 * The @timer_users has four elements but the first element is unused. This is
47 * to simplify accounting and indexing, as a zero value in @offset_timer
48 * represents disabled debouncing for the GPIO. Any other value for an element
49 * of @offset_timer is used as an index into @timer_users. This behaviour of
50 * the zero value aligns with the behaviour of zero built from the timer
51 * configuration registers (i.e. debouncing is disabled).
54 struct gpio_chip chip
;
59 const struct aspeed_gpio_config
*config
;
62 unsigned int timer_users
[4];
69 struct aspeed_gpio_bank
{
70 uint16_t val_regs
; /* +0: Rd: read input value, Wr: set write latch
71 * +4: Rd/Wr: Direction (0=in, 1=out)
73 uint16_t rdata_reg
; /* Rd: read write latch, Wr: <none> */
75 uint16_t debounce_regs
;
76 uint16_t tolerance_regs
;
78 const char names
[4][3];
82 * Note: The "value" register returns the input value sampled on the
83 * line even when the GPIO is configured as an output. Since
84 * that input goes through synchronizers, writing, then reading
85 * back may not return the written value right away.
87 * The "rdata" register returns the content of the write latch
88 * and thus can be used to read back what was last written
92 static const int debounce_timers
[4] = { 0x00, 0x50, 0x54, 0x58 };
94 static const struct aspeed_gpio_copro_ops
*copro_ops
;
95 static void *copro_data
;
97 static const struct aspeed_gpio_bank aspeed_gpio_banks
[] = {
102 .debounce_regs
= 0x0040,
103 .tolerance_regs
= 0x001c,
104 .cmdsrc_regs
= 0x0060,
105 .names
= { "A", "B", "C", "D" },
111 .debounce_regs
= 0x0048,
112 .tolerance_regs
= 0x003c,
113 .cmdsrc_regs
= 0x0068,
114 .names
= { "E", "F", "G", "H" },
120 .debounce_regs
= 0x00b0,
121 .tolerance_regs
= 0x00ac,
122 .cmdsrc_regs
= 0x0090,
123 .names
= { "I", "J", "K", "L" },
129 .debounce_regs
= 0x0100,
130 .tolerance_regs
= 0x00fc,
131 .cmdsrc_regs
= 0x00e0,
132 .names
= { "M", "N", "O", "P" },
138 .debounce_regs
= 0x0130,
139 .tolerance_regs
= 0x012c,
140 .cmdsrc_regs
= 0x0110,
141 .names
= { "Q", "R", "S", "T" },
147 .debounce_regs
= 0x0160,
148 .tolerance_regs
= 0x015c,
149 .cmdsrc_regs
= 0x0140,
150 .names
= { "U", "V", "W", "X" },
156 .debounce_regs
= 0x0190,
157 .tolerance_regs
= 0x018c,
158 .cmdsrc_regs
= 0x0170,
159 .names
= { "Y", "Z", "AA", "AB" },
165 .debounce_regs
= 0x01c0,
166 .tolerance_regs
= 0x01bc,
167 .cmdsrc_regs
= 0x01a0,
168 .names
= { "AC", "", "", "" },
172 enum aspeed_gpio_reg
{
188 #define GPIO_VAL_VALUE 0x00
189 #define GPIO_VAL_DIR 0x04
191 #define GPIO_IRQ_ENABLE 0x00
192 #define GPIO_IRQ_TYPE0 0x04
193 #define GPIO_IRQ_TYPE1 0x08
194 #define GPIO_IRQ_TYPE2 0x0c
195 #define GPIO_IRQ_STATUS 0x10
197 #define GPIO_DEBOUNCE_SEL1 0x00
198 #define GPIO_DEBOUNCE_SEL2 0x04
200 #define GPIO_CMDSRC_0 0x00
201 #define GPIO_CMDSRC_1 0x04
202 #define GPIO_CMDSRC_ARM 0
203 #define GPIO_CMDSRC_LPC 1
204 #define GPIO_CMDSRC_COLDFIRE 2
205 #define GPIO_CMDSRC_RESERVED 3
207 /* This will be resolved at compile time */
208 static inline void __iomem
*bank_reg(struct aspeed_gpio
*gpio
,
209 const struct aspeed_gpio_bank
*bank
,
210 const enum aspeed_gpio_reg reg
)
214 return gpio
->base
+ bank
->val_regs
+ GPIO_VAL_VALUE
;
216 return gpio
->base
+ bank
->rdata_reg
;
218 return gpio
->base
+ bank
->val_regs
+ GPIO_VAL_DIR
;
220 return gpio
->base
+ bank
->irq_regs
+ GPIO_IRQ_ENABLE
;
222 return gpio
->base
+ bank
->irq_regs
+ GPIO_IRQ_TYPE0
;
224 return gpio
->base
+ bank
->irq_regs
+ GPIO_IRQ_TYPE1
;
226 return gpio
->base
+ bank
->irq_regs
+ GPIO_IRQ_TYPE2
;
228 return gpio
->base
+ bank
->irq_regs
+ GPIO_IRQ_STATUS
;
229 case reg_debounce_sel1
:
230 return gpio
->base
+ bank
->debounce_regs
+ GPIO_DEBOUNCE_SEL1
;
231 case reg_debounce_sel2
:
232 return gpio
->base
+ bank
->debounce_regs
+ GPIO_DEBOUNCE_SEL2
;
234 return gpio
->base
+ bank
->tolerance_regs
;
236 return gpio
->base
+ bank
->cmdsrc_regs
+ GPIO_CMDSRC_0
;
238 return gpio
->base
+ bank
->cmdsrc_regs
+ GPIO_CMDSRC_1
;
243 #define GPIO_BANK(x) ((x) >> 5)
244 #define GPIO_OFFSET(x) ((x) & 0x1f)
245 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
247 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
248 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
249 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
251 static const struct aspeed_gpio_bank
*to_bank(unsigned int offset
)
253 unsigned int bank
= GPIO_BANK(offset
);
255 WARN_ON(bank
>= ARRAY_SIZE(aspeed_gpio_banks
));
256 return &aspeed_gpio_banks
[bank
];
259 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props
*props
)
261 return !(props
->input
|| props
->output
);
264 static inline const struct aspeed_bank_props
*find_bank_props(
265 struct aspeed_gpio
*gpio
, unsigned int offset
)
267 const struct aspeed_bank_props
*props
= gpio
->config
->props
;
269 while (!is_bank_props_sentinel(props
)) {
270 if (props
->bank
== GPIO_BANK(offset
))
278 static inline bool have_gpio(struct aspeed_gpio
*gpio
, unsigned int offset
)
280 const struct aspeed_bank_props
*props
= find_bank_props(gpio
, offset
);
281 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
282 unsigned int group
= GPIO_OFFSET(offset
) / 8;
284 return bank
->names
[group
][0] != '\0' &&
285 (!props
|| ((props
->input
| props
->output
) & GPIO_BIT(offset
)));
288 static inline bool have_input(struct aspeed_gpio
*gpio
, unsigned int offset
)
290 const struct aspeed_bank_props
*props
= find_bank_props(gpio
, offset
);
292 return !props
|| (props
->input
& GPIO_BIT(offset
));
295 #define have_irq(g, o) have_input((g), (o))
296 #define have_debounce(g, o) have_input((g), (o))
298 static inline bool have_output(struct aspeed_gpio
*gpio
, unsigned int offset
)
300 const struct aspeed_bank_props
*props
= find_bank_props(gpio
, offset
);
302 return !props
|| (props
->output
& GPIO_BIT(offset
));
305 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio
*gpio
,
306 const struct aspeed_gpio_bank
*bank
,
307 int bindex
, int cmdsrc
)
309 void __iomem
*c0
= bank_reg(gpio
, bank
, reg_cmdsrc0
);
310 void __iomem
*c1
= bank_reg(gpio
, bank
, reg_cmdsrc1
);
314 * Each register controls 4 banks, so take the bottom 2
315 * bits of the bank index, and use them to select the
316 * right control bit (0, 8, 16 or 24).
318 bit
= BIT((bindex
& 3) << 3);
320 /* Source 1 first to avoid illegal 11 combination */
337 static bool aspeed_gpio_copro_request(struct aspeed_gpio
*gpio
,
340 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
342 if (!copro_ops
|| !gpio
->cf_copro_bankmap
)
344 if (!gpio
->cf_copro_bankmap
[offset
>> 3])
346 if (!copro_ops
->request_access
)
349 /* Pause the coprocessor */
350 copro_ops
->request_access(copro_data
);
352 /* Change command source back to ARM */
353 aspeed_gpio_change_cmd_source(gpio
, bank
, offset
>> 3, GPIO_CMDSRC_ARM
);
356 gpio
->dcache
[GPIO_BANK(offset
)] = ioread32(bank_reg(gpio
, bank
, reg_rdata
));
361 static void aspeed_gpio_copro_release(struct aspeed_gpio
*gpio
,
364 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
366 if (!copro_ops
|| !gpio
->cf_copro_bankmap
)
368 if (!gpio
->cf_copro_bankmap
[offset
>> 3])
370 if (!copro_ops
->release_access
)
373 /* Change command source back to ColdFire */
374 aspeed_gpio_change_cmd_source(gpio
, bank
, offset
>> 3,
375 GPIO_CMDSRC_COLDFIRE
);
377 /* Restart the coprocessor */
378 copro_ops
->release_access(copro_data
);
381 static int aspeed_gpio_get(struct gpio_chip
*gc
, unsigned int offset
)
383 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
384 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
386 return !!(ioread32(bank_reg(gpio
, bank
, reg_val
)) & GPIO_BIT(offset
));
389 static void __aspeed_gpio_set(struct gpio_chip
*gc
, unsigned int offset
,
392 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
393 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
397 addr
= bank_reg(gpio
, bank
, reg_val
);
398 reg
= gpio
->dcache
[GPIO_BANK(offset
)];
401 reg
|= GPIO_BIT(offset
);
403 reg
&= ~GPIO_BIT(offset
);
404 gpio
->dcache
[GPIO_BANK(offset
)] = reg
;
406 iowrite32(reg
, addr
);
409 static void aspeed_gpio_set(struct gpio_chip
*gc
, unsigned int offset
,
412 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
416 spin_lock_irqsave(&gpio
->lock
, flags
);
417 copro
= aspeed_gpio_copro_request(gpio
, offset
);
419 __aspeed_gpio_set(gc
, offset
, val
);
422 aspeed_gpio_copro_release(gpio
, offset
);
423 spin_unlock_irqrestore(&gpio
->lock
, flags
);
426 static int aspeed_gpio_dir_in(struct gpio_chip
*gc
, unsigned int offset
)
428 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
429 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
430 void __iomem
*addr
= bank_reg(gpio
, bank
, reg_dir
);
435 if (!have_input(gpio
, offset
))
438 spin_lock_irqsave(&gpio
->lock
, flags
);
440 reg
= ioread32(addr
);
441 reg
&= ~GPIO_BIT(offset
);
443 copro
= aspeed_gpio_copro_request(gpio
, offset
);
444 iowrite32(reg
, addr
);
446 aspeed_gpio_copro_release(gpio
, offset
);
448 spin_unlock_irqrestore(&gpio
->lock
, flags
);
453 static int aspeed_gpio_dir_out(struct gpio_chip
*gc
,
454 unsigned int offset
, int val
)
456 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
457 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
458 void __iomem
*addr
= bank_reg(gpio
, bank
, reg_dir
);
463 if (!have_output(gpio
, offset
))
466 spin_lock_irqsave(&gpio
->lock
, flags
);
468 reg
= ioread32(addr
);
469 reg
|= GPIO_BIT(offset
);
471 copro
= aspeed_gpio_copro_request(gpio
, offset
);
472 __aspeed_gpio_set(gc
, offset
, val
);
473 iowrite32(reg
, addr
);
476 aspeed_gpio_copro_release(gpio
, offset
);
477 spin_unlock_irqrestore(&gpio
->lock
, flags
);
482 static int aspeed_gpio_get_direction(struct gpio_chip
*gc
, unsigned int offset
)
484 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
485 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
489 if (!have_input(gpio
, offset
))
490 return GPIO_LINE_DIRECTION_OUT
;
492 if (!have_output(gpio
, offset
))
493 return GPIO_LINE_DIRECTION_IN
;
495 spin_lock_irqsave(&gpio
->lock
, flags
);
497 val
= ioread32(bank_reg(gpio
, bank
, reg_dir
)) & GPIO_BIT(offset
);
499 spin_unlock_irqrestore(&gpio
->lock
, flags
);
501 return val
? GPIO_LINE_DIRECTION_OUT
: GPIO_LINE_DIRECTION_IN
;
504 static inline int irqd_to_aspeed_gpio_data(struct irq_data
*d
,
505 struct aspeed_gpio
**gpio
,
506 const struct aspeed_gpio_bank
**bank
,
507 u32
*bit
, int *offset
)
509 struct aspeed_gpio
*internal
;
511 *offset
= irqd_to_hwirq(d
);
513 internal
= irq_data_get_irq_chip_data(d
);
515 /* This might be a bit of a questionable place to check */
516 if (!have_irq(internal
, *offset
))
520 *bank
= to_bank(*offset
);
521 *bit
= GPIO_BIT(*offset
);
526 static void aspeed_gpio_irq_ack(struct irq_data
*d
)
528 const struct aspeed_gpio_bank
*bank
;
529 struct aspeed_gpio
*gpio
;
531 void __iomem
*status_addr
;
536 rc
= irqd_to_aspeed_gpio_data(d
, &gpio
, &bank
, &bit
, &offset
);
540 status_addr
= bank_reg(gpio
, bank
, reg_irq_status
);
542 spin_lock_irqsave(&gpio
->lock
, flags
);
543 copro
= aspeed_gpio_copro_request(gpio
, offset
);
545 iowrite32(bit
, status_addr
);
548 aspeed_gpio_copro_release(gpio
, offset
);
549 spin_unlock_irqrestore(&gpio
->lock
, flags
);
552 static void aspeed_gpio_irq_set_mask(struct irq_data
*d
, bool set
)
554 const struct aspeed_gpio_bank
*bank
;
555 struct aspeed_gpio
*gpio
;
562 rc
= irqd_to_aspeed_gpio_data(d
, &gpio
, &bank
, &bit
, &offset
);
566 addr
= bank_reg(gpio
, bank
, reg_irq_enable
);
568 spin_lock_irqsave(&gpio
->lock
, flags
);
569 copro
= aspeed_gpio_copro_request(gpio
, offset
);
571 reg
= ioread32(addr
);
576 iowrite32(reg
, addr
);
579 aspeed_gpio_copro_release(gpio
, offset
);
580 spin_unlock_irqrestore(&gpio
->lock
, flags
);
583 static void aspeed_gpio_irq_mask(struct irq_data
*d
)
585 aspeed_gpio_irq_set_mask(d
, false);
588 static void aspeed_gpio_irq_unmask(struct irq_data
*d
)
590 aspeed_gpio_irq_set_mask(d
, true);
593 static int aspeed_gpio_set_type(struct irq_data
*d
, unsigned int type
)
599 const struct aspeed_gpio_bank
*bank
;
600 irq_flow_handler_t handler
;
601 struct aspeed_gpio
*gpio
;
607 rc
= irqd_to_aspeed_gpio_data(d
, &gpio
, &bank
, &bit
, &offset
);
611 switch (type
& IRQ_TYPE_SENSE_MASK
) {
612 case IRQ_TYPE_EDGE_BOTH
:
615 case IRQ_TYPE_EDGE_RISING
:
618 case IRQ_TYPE_EDGE_FALLING
:
619 handler
= handle_edge_irq
;
621 case IRQ_TYPE_LEVEL_HIGH
:
624 case IRQ_TYPE_LEVEL_LOW
:
626 handler
= handle_level_irq
;
632 spin_lock_irqsave(&gpio
->lock
, flags
);
633 copro
= aspeed_gpio_copro_request(gpio
, offset
);
635 addr
= bank_reg(gpio
, bank
, reg_irq_type0
);
636 reg
= ioread32(addr
);
637 reg
= (reg
& ~bit
) | type0
;
638 iowrite32(reg
, addr
);
640 addr
= bank_reg(gpio
, bank
, reg_irq_type1
);
641 reg
= ioread32(addr
);
642 reg
= (reg
& ~bit
) | type1
;
643 iowrite32(reg
, addr
);
645 addr
= bank_reg(gpio
, bank
, reg_irq_type2
);
646 reg
= ioread32(addr
);
647 reg
= (reg
& ~bit
) | type2
;
648 iowrite32(reg
, addr
);
651 aspeed_gpio_copro_release(gpio
, offset
);
652 spin_unlock_irqrestore(&gpio
->lock
, flags
);
654 irq_set_handler_locked(d
, handler
);
659 static void aspeed_gpio_irq_handler(struct irq_desc
*desc
)
661 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
662 struct irq_chip
*ic
= irq_desc_get_chip(desc
);
663 struct aspeed_gpio
*data
= gpiochip_get_data(gc
);
664 unsigned int i
, p
, banks
;
666 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
668 chained_irq_enter(ic
, desc
);
670 banks
= DIV_ROUND_UP(gpio
->chip
.ngpio
, 32);
671 for (i
= 0; i
< banks
; i
++) {
672 const struct aspeed_gpio_bank
*bank
= &aspeed_gpio_banks
[i
];
674 reg
= ioread32(bank_reg(data
, bank
, reg_irq_status
));
676 for_each_set_bit(p
, ®
, 32)
677 generic_handle_domain_irq(gc
->irq
.domain
, i
* 32 + p
);
680 chained_irq_exit(ic
, desc
);
683 static void aspeed_init_irq_valid_mask(struct gpio_chip
*gc
,
684 unsigned long *valid_mask
,
687 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
688 const struct aspeed_bank_props
*props
= gpio
->config
->props
;
690 while (!is_bank_props_sentinel(props
)) {
692 const unsigned long int input
= props
->input
;
694 /* Pretty crummy approach, but similar to GPIO core */
695 for_each_clear_bit(offset
, &input
, 32) {
696 unsigned int i
= props
->bank
* 32 + offset
;
698 if (i
>= gpio
->chip
.ngpio
)
701 clear_bit(i
, valid_mask
);
708 static int aspeed_gpio_reset_tolerance(struct gpio_chip
*chip
,
709 unsigned int offset
, bool enable
)
711 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
717 treg
= bank_reg(gpio
, to_bank(offset
), reg_tolerance
);
719 spin_lock_irqsave(&gpio
->lock
, flags
);
720 copro
= aspeed_gpio_copro_request(gpio
, offset
);
725 val
|= GPIO_BIT(offset
);
727 val
&= ~GPIO_BIT(offset
);
732 aspeed_gpio_copro_release(gpio
, offset
);
733 spin_unlock_irqrestore(&gpio
->lock
, flags
);
738 static int aspeed_gpio_request(struct gpio_chip
*chip
, unsigned int offset
)
740 if (!have_gpio(gpiochip_get_data(chip
), offset
))
743 return pinctrl_gpio_request(chip
->base
+ offset
);
746 static void aspeed_gpio_free(struct gpio_chip
*chip
, unsigned int offset
)
748 pinctrl_gpio_free(chip
->base
+ offset
);
751 static int usecs_to_cycles(struct aspeed_gpio
*gpio
, unsigned long usecs
,
758 rate
= clk_get_rate(gpio
->clk
);
763 r
= do_div(n
, 1000000);
768 /* At least as long as the requested time */
774 /* Call under gpio->lock */
775 static int register_allocated_timer(struct aspeed_gpio
*gpio
,
776 unsigned int offset
, unsigned int timer
)
778 if (WARN(gpio
->offset_timer
[offset
] != 0,
779 "Offset %d already allocated timer %d\n",
780 offset
, gpio
->offset_timer
[offset
]))
783 if (WARN(gpio
->timer_users
[timer
] == UINT_MAX
,
784 "Timer user count would overflow\n"))
787 gpio
->offset_timer
[offset
] = timer
;
788 gpio
->timer_users
[timer
]++;
793 /* Call under gpio->lock */
794 static int unregister_allocated_timer(struct aspeed_gpio
*gpio
,
797 if (WARN(gpio
->offset_timer
[offset
] == 0,
798 "No timer allocated to offset %d\n", offset
))
801 if (WARN(gpio
->timer_users
[gpio
->offset_timer
[offset
]] == 0,
802 "No users recorded for timer %d\n",
803 gpio
->offset_timer
[offset
]))
806 gpio
->timer_users
[gpio
->offset_timer
[offset
]]--;
807 gpio
->offset_timer
[offset
] = 0;
812 /* Call under gpio->lock */
813 static inline bool timer_allocation_registered(struct aspeed_gpio
*gpio
,
816 return gpio
->offset_timer
[offset
] > 0;
819 /* Call under gpio->lock */
820 static void configure_timer(struct aspeed_gpio
*gpio
, unsigned int offset
,
823 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
824 const u32 mask
= GPIO_BIT(offset
);
828 /* Note: Debounce timer isn't under control of the command
829 * source registers, so no need to sync with the coprocessor
831 addr
= bank_reg(gpio
, bank
, reg_debounce_sel1
);
832 val
= ioread32(addr
);
833 iowrite32((val
& ~mask
) | GPIO_SET_DEBOUNCE1(timer
, offset
), addr
);
835 addr
= bank_reg(gpio
, bank
, reg_debounce_sel2
);
836 val
= ioread32(addr
);
837 iowrite32((val
& ~mask
) | GPIO_SET_DEBOUNCE2(timer
, offset
), addr
);
840 static int enable_debounce(struct gpio_chip
*chip
, unsigned int offset
,
843 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
844 u32 requested_cycles
;
852 rc
= usecs_to_cycles(gpio
, usecs
, &requested_cycles
);
854 dev_warn(chip
->parent
, "Failed to convert %luus to cycles at %luHz: %d\n",
855 usecs
, clk_get_rate(gpio
->clk
), rc
);
859 spin_lock_irqsave(&gpio
->lock
, flags
);
861 if (timer_allocation_registered(gpio
, offset
)) {
862 rc
= unregister_allocated_timer(gpio
, offset
);
867 /* Try to find a timer already configured for the debounce period */
868 for (i
= 1; i
< ARRAY_SIZE(debounce_timers
); i
++) {
871 cycles
= ioread32(gpio
->base
+ debounce_timers
[i
]);
872 if (requested_cycles
== cycles
)
876 if (i
== ARRAY_SIZE(debounce_timers
)) {
880 * As there are no timers configured for the requested debounce
881 * period, find an unused timer instead
883 for (j
= 1; j
< ARRAY_SIZE(gpio
->timer_users
); j
++) {
884 if (gpio
->timer_users
[j
] == 0)
888 if (j
== ARRAY_SIZE(gpio
->timer_users
)) {
889 dev_warn(chip
->parent
,
890 "Debounce timers exhausted, cannot debounce for period %luus\n",
896 * We already adjusted the accounting to remove @offset
897 * as a user of its previous timer, so also configure
898 * the hardware so @offset has timers disabled for
901 configure_timer(gpio
, offset
, 0);
907 iowrite32(requested_cycles
, gpio
->base
+ debounce_timers
[i
]);
910 if (WARN(i
== 0, "Cannot register index of disabled timer\n")) {
915 register_allocated_timer(gpio
, offset
, i
);
916 configure_timer(gpio
, offset
, i
);
919 spin_unlock_irqrestore(&gpio
->lock
, flags
);
924 static int disable_debounce(struct gpio_chip
*chip
, unsigned int offset
)
926 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
930 spin_lock_irqsave(&gpio
->lock
, flags
);
932 rc
= unregister_allocated_timer(gpio
, offset
);
934 configure_timer(gpio
, offset
, 0);
936 spin_unlock_irqrestore(&gpio
->lock
, flags
);
941 static int set_debounce(struct gpio_chip
*chip
, unsigned int offset
,
944 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
946 if (!have_debounce(gpio
, offset
))
950 return enable_debounce(chip
, offset
, usecs
);
952 return disable_debounce(chip
, offset
);
955 static int aspeed_gpio_set_config(struct gpio_chip
*chip
, unsigned int offset
,
956 unsigned long config
)
958 unsigned long param
= pinconf_to_config_param(config
);
959 u32 arg
= pinconf_to_config_argument(config
);
961 if (param
== PIN_CONFIG_INPUT_DEBOUNCE
)
962 return set_debounce(chip
, offset
, arg
);
963 else if (param
== PIN_CONFIG_BIAS_DISABLE
||
964 param
== PIN_CONFIG_BIAS_PULL_DOWN
||
965 param
== PIN_CONFIG_DRIVE_STRENGTH
)
966 return pinctrl_gpio_set_config(offset
, config
);
967 else if (param
== PIN_CONFIG_DRIVE_OPEN_DRAIN
||
968 param
== PIN_CONFIG_DRIVE_OPEN_SOURCE
)
969 /* Return -ENOTSUPP to trigger emulation, as per datasheet */
971 else if (param
== PIN_CONFIG_PERSIST_STATE
)
972 return aspeed_gpio_reset_tolerance(chip
, offset
, arg
);
978 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
979 * the coprocessor for shared GPIO banks
980 * @ops: The callbacks
981 * @data: Pointer passed back to the callbacks
983 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops
*ops
, void *data
)
990 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops
);
993 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
994 * bank gets marked and any access from the ARM will
995 * result in handshaking via callbacks.
996 * @desc: The GPIO to be marked
997 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
998 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
999 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1001 int aspeed_gpio_copro_grab_gpio(struct gpio_desc
*desc
,
1002 u16
*vreg_offset
, u16
*dreg_offset
, u8
*bit
)
1004 struct gpio_chip
*chip
= gpiod_to_chip(desc
);
1005 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
1006 int rc
= 0, bindex
, offset
= gpio_chip_hwgpio(desc
);
1007 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
1008 unsigned long flags
;
1010 if (!gpio
->cf_copro_bankmap
)
1011 gpio
->cf_copro_bankmap
= kzalloc(gpio
->chip
.ngpio
>> 3, GFP_KERNEL
);
1012 if (!gpio
->cf_copro_bankmap
)
1014 if (offset
< 0 || offset
> gpio
->chip
.ngpio
)
1016 bindex
= offset
>> 3;
1018 spin_lock_irqsave(&gpio
->lock
, flags
);
1020 /* Sanity check, this shouldn't happen */
1021 if (gpio
->cf_copro_bankmap
[bindex
] == 0xff) {
1025 gpio
->cf_copro_bankmap
[bindex
]++;
1027 /* Switch command source */
1028 if (gpio
->cf_copro_bankmap
[bindex
] == 1)
1029 aspeed_gpio_change_cmd_source(gpio
, bank
, bindex
,
1030 GPIO_CMDSRC_COLDFIRE
);
1033 *vreg_offset
= bank
->val_regs
;
1035 *dreg_offset
= bank
->rdata_reg
;
1037 *bit
= GPIO_OFFSET(offset
);
1039 spin_unlock_irqrestore(&gpio
->lock
, flags
);
1042 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio
);
1045 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1046 * @desc: The GPIO to be marked
1048 int aspeed_gpio_copro_release_gpio(struct gpio_desc
*desc
)
1050 struct gpio_chip
*chip
= gpiod_to_chip(desc
);
1051 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
1052 int rc
= 0, bindex
, offset
= gpio_chip_hwgpio(desc
);
1053 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
1054 unsigned long flags
;
1056 if (!gpio
->cf_copro_bankmap
)
1059 if (offset
< 0 || offset
> gpio
->chip
.ngpio
)
1061 bindex
= offset
>> 3;
1063 spin_lock_irqsave(&gpio
->lock
, flags
);
1065 /* Sanity check, this shouldn't happen */
1066 if (gpio
->cf_copro_bankmap
[bindex
] == 0) {
1070 gpio
->cf_copro_bankmap
[bindex
]--;
1072 /* Switch command source */
1073 if (gpio
->cf_copro_bankmap
[bindex
] == 0)
1074 aspeed_gpio_change_cmd_source(gpio
, bank
, bindex
,
1077 spin_unlock_irqrestore(&gpio
->lock
, flags
);
1080 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio
);
1083 * Any banks not specified in a struct aspeed_bank_props array are assumed to
1084 * have the properties:
1086 * { .input = 0xffffffff, .output = 0xffffffff }
1089 static const struct aspeed_bank_props ast2400_bank_props
[] = {
1091 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1092 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1096 static const struct aspeed_gpio_config ast2400_config
=
1097 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1098 { .nr_gpios
= 220, .props
= ast2400_bank_props
, };
1100 static const struct aspeed_bank_props ast2500_bank_props
[] = {
1102 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1103 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1104 { 7, 0x000000ff, 0x000000ff }, /* AC */
1108 static const struct aspeed_gpio_config ast2500_config
=
1109 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1110 { .nr_gpios
= 232, .props
= ast2500_bank_props
, };
1112 static const struct aspeed_bank_props ast2600_bank_props
[] = {
1114 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */
1115 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
1116 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
1120 static const struct aspeed_gpio_config ast2600_config
=
1122 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
1123 * We expect ngpio being set in the device tree and this is a fallback
1126 { .nr_gpios
= 208, .props
= ast2600_bank_props
, };
1128 static const struct of_device_id aspeed_gpio_of_table
[] = {
1129 { .compatible
= "aspeed,ast2400-gpio", .data
= &ast2400_config
, },
1130 { .compatible
= "aspeed,ast2500-gpio", .data
= &ast2500_config
, },
1131 { .compatible
= "aspeed,ast2600-gpio", .data
= &ast2600_config
, },
1134 MODULE_DEVICE_TABLE(of
, aspeed_gpio_of_table
);
1136 static int __init
aspeed_gpio_probe(struct platform_device
*pdev
)
1138 const struct of_device_id
*gpio_id
;
1139 struct aspeed_gpio
*gpio
;
1140 int rc
, i
, banks
, err
;
1143 gpio
= devm_kzalloc(&pdev
->dev
, sizeof(*gpio
), GFP_KERNEL
);
1147 gpio
->base
= devm_platform_ioremap_resource(pdev
, 0);
1148 if (IS_ERR(gpio
->base
))
1149 return PTR_ERR(gpio
->base
);
1151 spin_lock_init(&gpio
->lock
);
1153 gpio_id
= of_match_node(aspeed_gpio_of_table
, pdev
->dev
.of_node
);
1157 gpio
->clk
= of_clk_get(pdev
->dev
.of_node
, 0);
1158 if (IS_ERR(gpio
->clk
)) {
1159 dev_warn(&pdev
->dev
,
1160 "Failed to get clock from devicetree, debouncing disabled\n");
1164 gpio
->config
= gpio_id
->data
;
1166 gpio
->chip
.parent
= &pdev
->dev
;
1167 err
= of_property_read_u32(pdev
->dev
.of_node
, "ngpios", &ngpio
);
1168 gpio
->chip
.ngpio
= (u16
) ngpio
;
1170 gpio
->chip
.ngpio
= gpio
->config
->nr_gpios
;
1171 gpio
->chip
.direction_input
= aspeed_gpio_dir_in
;
1172 gpio
->chip
.direction_output
= aspeed_gpio_dir_out
;
1173 gpio
->chip
.get_direction
= aspeed_gpio_get_direction
;
1174 gpio
->chip
.request
= aspeed_gpio_request
;
1175 gpio
->chip
.free
= aspeed_gpio_free
;
1176 gpio
->chip
.get
= aspeed_gpio_get
;
1177 gpio
->chip
.set
= aspeed_gpio_set
;
1178 gpio
->chip
.set_config
= aspeed_gpio_set_config
;
1179 gpio
->chip
.label
= dev_name(&pdev
->dev
);
1180 gpio
->chip
.base
= -1;
1182 /* Allocate a cache of the output registers */
1183 banks
= DIV_ROUND_UP(gpio
->chip
.ngpio
, 32);
1184 gpio
->dcache
= devm_kcalloc(&pdev
->dev
,
1185 banks
, sizeof(u32
), GFP_KERNEL
);
1190 * Populate it with initial values read from the HW and switch
1191 * all command sources to the ARM by default
1193 for (i
= 0; i
< banks
; i
++) {
1194 const struct aspeed_gpio_bank
*bank
= &aspeed_gpio_banks
[i
];
1195 void __iomem
*addr
= bank_reg(gpio
, bank
, reg_rdata
);
1196 gpio
->dcache
[i
] = ioread32(addr
);
1197 aspeed_gpio_change_cmd_source(gpio
, bank
, 0, GPIO_CMDSRC_ARM
);
1198 aspeed_gpio_change_cmd_source(gpio
, bank
, 1, GPIO_CMDSRC_ARM
);
1199 aspeed_gpio_change_cmd_source(gpio
, bank
, 2, GPIO_CMDSRC_ARM
);
1200 aspeed_gpio_change_cmd_source(gpio
, bank
, 3, GPIO_CMDSRC_ARM
);
1203 /* Optionally set up an irqchip if there is an IRQ */
1204 rc
= platform_get_irq(pdev
, 0);
1206 struct gpio_irq_chip
*girq
;
1209 girq
= &gpio
->chip
.irq
;
1210 girq
->chip
= &gpio
->irqc
;
1211 girq
->chip
->name
= dev_name(&pdev
->dev
);
1212 girq
->chip
->irq_ack
= aspeed_gpio_irq_ack
;
1213 girq
->chip
->irq_mask
= aspeed_gpio_irq_mask
;
1214 girq
->chip
->irq_unmask
= aspeed_gpio_irq_unmask
;
1215 girq
->chip
->irq_set_type
= aspeed_gpio_set_type
;
1216 girq
->parent_handler
= aspeed_gpio_irq_handler
;
1217 girq
->num_parents
= 1;
1218 girq
->parents
= devm_kcalloc(&pdev
->dev
, 1,
1219 sizeof(*girq
->parents
),
1223 girq
->parents
[0] = gpio
->irq
;
1224 girq
->default_type
= IRQ_TYPE_NONE
;
1225 girq
->handler
= handle_bad_irq
;
1226 girq
->init_valid_mask
= aspeed_init_irq_valid_mask
;
1229 gpio
->offset_timer
=
1230 devm_kzalloc(&pdev
->dev
, gpio
->chip
.ngpio
, GFP_KERNEL
);
1231 if (!gpio
->offset_timer
)
1234 rc
= devm_gpiochip_add_data(&pdev
->dev
, &gpio
->chip
, gpio
);
1241 static struct platform_driver aspeed_gpio_driver
= {
1243 .name
= KBUILD_MODNAME
,
1244 .of_match_table
= aspeed_gpio_of_table
,
1248 module_platform_driver_probe(aspeed_gpio_driver
, aspeed_gpio_probe
);
1250 MODULE_DESCRIPTION("Aspeed GPIO Driver");
1251 MODULE_LICENSE("GPL");