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Merge tag 'docs-5.11' of git://git.lwn.net/linux
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-aspeed.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2015 IBM Corp.
4 *
5 * Joel Stanley <joel@jms.id.au>
6 */
7
8 #include <asm/div64.h>
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/aspeed.h>
12 #include <linux/hashtable.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
21
22 /*
23 * These two headers aren't meant to be used by GPIO drivers. We need
24 * them in order to access gpio_chip_hwgpio() which we need to implement
25 * the aspeed specific API which allows the coprocessor to request
26 * access to some GPIOs and to arbitrate between coprocessor and ARM.
27 */
28 #include <linux/gpio/consumer.h>
29 #include "gpiolib.h"
30
31 struct aspeed_bank_props {
32 unsigned int bank;
33 u32 input;
34 u32 output;
35 };
36
37 struct aspeed_gpio_config {
38 unsigned int nr_gpios;
39 const struct aspeed_bank_props *props;
40 };
41
42 /*
43 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
44 * @timer_users: Tracks the number of users for each timer
45 *
46 * The @timer_users has four elements but the first element is unused. This is
47 * to simplify accounting and indexing, as a zero value in @offset_timer
48 * represents disabled debouncing for the GPIO. Any other value for an element
49 * of @offset_timer is used as an index into @timer_users. This behaviour of
50 * the zero value aligns with the behaviour of zero built from the timer
51 * configuration registers (i.e. debouncing is disabled).
52 */
53 struct aspeed_gpio {
54 struct gpio_chip chip;
55 struct irq_chip irqc;
56 spinlock_t lock;
57 void __iomem *base;
58 int irq;
59 const struct aspeed_gpio_config *config;
60
61 u8 *offset_timer;
62 unsigned int timer_users[4];
63 struct clk *clk;
64
65 u32 *dcache;
66 u8 *cf_copro_bankmap;
67 };
68
69 struct aspeed_gpio_bank {
70 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
71 * +4: Rd/Wr: Direction (0=in, 1=out)
72 */
73 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
74 uint16_t irq_regs;
75 uint16_t debounce_regs;
76 uint16_t tolerance_regs;
77 uint16_t cmdsrc_regs;
78 const char names[4][3];
79 };
80
81 /*
82 * Note: The "value" register returns the input value sampled on the
83 * line even when the GPIO is configured as an output. Since
84 * that input goes through synchronizers, writing, then reading
85 * back may not return the written value right away.
86 *
87 * The "rdata" register returns the content of the write latch
88 * and thus can be used to read back what was last written
89 * reliably.
90 */
91
92 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
93
94 static const struct aspeed_gpio_copro_ops *copro_ops;
95 static void *copro_data;
96
97 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
98 {
99 .val_regs = 0x0000,
100 .rdata_reg = 0x00c0,
101 .irq_regs = 0x0008,
102 .debounce_regs = 0x0040,
103 .tolerance_regs = 0x001c,
104 .cmdsrc_regs = 0x0060,
105 .names = { "A", "B", "C", "D" },
106 },
107 {
108 .val_regs = 0x0020,
109 .rdata_reg = 0x00c4,
110 .irq_regs = 0x0028,
111 .debounce_regs = 0x0048,
112 .tolerance_regs = 0x003c,
113 .cmdsrc_regs = 0x0068,
114 .names = { "E", "F", "G", "H" },
115 },
116 {
117 .val_regs = 0x0070,
118 .rdata_reg = 0x00c8,
119 .irq_regs = 0x0098,
120 .debounce_regs = 0x00b0,
121 .tolerance_regs = 0x00ac,
122 .cmdsrc_regs = 0x0090,
123 .names = { "I", "J", "K", "L" },
124 },
125 {
126 .val_regs = 0x0078,
127 .rdata_reg = 0x00cc,
128 .irq_regs = 0x00e8,
129 .debounce_regs = 0x0100,
130 .tolerance_regs = 0x00fc,
131 .cmdsrc_regs = 0x00e0,
132 .names = { "M", "N", "O", "P" },
133 },
134 {
135 .val_regs = 0x0080,
136 .rdata_reg = 0x00d0,
137 .irq_regs = 0x0118,
138 .debounce_regs = 0x0130,
139 .tolerance_regs = 0x012c,
140 .cmdsrc_regs = 0x0110,
141 .names = { "Q", "R", "S", "T" },
142 },
143 {
144 .val_regs = 0x0088,
145 .rdata_reg = 0x00d4,
146 .irq_regs = 0x0148,
147 .debounce_regs = 0x0160,
148 .tolerance_regs = 0x015c,
149 .cmdsrc_regs = 0x0140,
150 .names = { "U", "V", "W", "X" },
151 },
152 {
153 .val_regs = 0x01E0,
154 .rdata_reg = 0x00d8,
155 .irq_regs = 0x0178,
156 .debounce_regs = 0x0190,
157 .tolerance_regs = 0x018c,
158 .cmdsrc_regs = 0x0170,
159 .names = { "Y", "Z", "AA", "AB" },
160 },
161 {
162 .val_regs = 0x01e8,
163 .rdata_reg = 0x00dc,
164 .irq_regs = 0x01a8,
165 .debounce_regs = 0x01c0,
166 .tolerance_regs = 0x01bc,
167 .cmdsrc_regs = 0x01a0,
168 .names = { "AC", "", "", "" },
169 },
170 };
171
172 enum aspeed_gpio_reg {
173 reg_val,
174 reg_rdata,
175 reg_dir,
176 reg_irq_enable,
177 reg_irq_type0,
178 reg_irq_type1,
179 reg_irq_type2,
180 reg_irq_status,
181 reg_debounce_sel1,
182 reg_debounce_sel2,
183 reg_tolerance,
184 reg_cmdsrc0,
185 reg_cmdsrc1,
186 };
187
188 #define GPIO_VAL_VALUE 0x00
189 #define GPIO_VAL_DIR 0x04
190
191 #define GPIO_IRQ_ENABLE 0x00
192 #define GPIO_IRQ_TYPE0 0x04
193 #define GPIO_IRQ_TYPE1 0x08
194 #define GPIO_IRQ_TYPE2 0x0c
195 #define GPIO_IRQ_STATUS 0x10
196
197 #define GPIO_DEBOUNCE_SEL1 0x00
198 #define GPIO_DEBOUNCE_SEL2 0x04
199
200 #define GPIO_CMDSRC_0 0x00
201 #define GPIO_CMDSRC_1 0x04
202 #define GPIO_CMDSRC_ARM 0
203 #define GPIO_CMDSRC_LPC 1
204 #define GPIO_CMDSRC_COLDFIRE 2
205 #define GPIO_CMDSRC_RESERVED 3
206
207 /* This will be resolved at compile time */
208 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
209 const struct aspeed_gpio_bank *bank,
210 const enum aspeed_gpio_reg reg)
211 {
212 switch (reg) {
213 case reg_val:
214 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
215 case reg_rdata:
216 return gpio->base + bank->rdata_reg;
217 case reg_dir:
218 return gpio->base + bank->val_regs + GPIO_VAL_DIR;
219 case reg_irq_enable:
220 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
221 case reg_irq_type0:
222 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
223 case reg_irq_type1:
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
225 case reg_irq_type2:
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
227 case reg_irq_status:
228 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
229 case reg_debounce_sel1:
230 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
231 case reg_debounce_sel2:
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
233 case reg_tolerance:
234 return gpio->base + bank->tolerance_regs;
235 case reg_cmdsrc0:
236 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
237 case reg_cmdsrc1:
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
239 }
240 BUG();
241 }
242
243 #define GPIO_BANK(x) ((x) >> 5)
244 #define GPIO_OFFSET(x) ((x) & 0x1f)
245 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
246
247 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
248 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
249 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
250
251 static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
252 {
253 unsigned int bank = GPIO_BANK(offset);
254
255 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
256 return &aspeed_gpio_banks[bank];
257 }
258
259 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
260 {
261 return !(props->input || props->output);
262 }
263
264 static inline const struct aspeed_bank_props *find_bank_props(
265 struct aspeed_gpio *gpio, unsigned int offset)
266 {
267 const struct aspeed_bank_props *props = gpio->config->props;
268
269 while (!is_bank_props_sentinel(props)) {
270 if (props->bank == GPIO_BANK(offset))
271 return props;
272 props++;
273 }
274
275 return NULL;
276 }
277
278 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
279 {
280 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
281 const struct aspeed_gpio_bank *bank = to_bank(offset);
282 unsigned int group = GPIO_OFFSET(offset) / 8;
283
284 return bank->names[group][0] != '\0' &&
285 (!props || ((props->input | props->output) & GPIO_BIT(offset)));
286 }
287
288 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
289 {
290 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
291
292 return !props || (props->input & GPIO_BIT(offset));
293 }
294
295 #define have_irq(g, o) have_input((g), (o))
296 #define have_debounce(g, o) have_input((g), (o))
297
298 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
299 {
300 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
301
302 return !props || (props->output & GPIO_BIT(offset));
303 }
304
305 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
306 const struct aspeed_gpio_bank *bank,
307 int bindex, int cmdsrc)
308 {
309 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
310 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
311 u32 bit, reg;
312
313 /*
314 * Each register controls 4 banks, so take the bottom 2
315 * bits of the bank index, and use them to select the
316 * right control bit (0, 8, 16 or 24).
317 */
318 bit = BIT((bindex & 3) << 3);
319
320 /* Source 1 first to avoid illegal 11 combination */
321 reg = ioread32(c1);
322 if (cmdsrc & 2)
323 reg |= bit;
324 else
325 reg &= ~bit;
326 iowrite32(reg, c1);
327
328 /* Then Source 0 */
329 reg = ioread32(c0);
330 if (cmdsrc & 1)
331 reg |= bit;
332 else
333 reg &= ~bit;
334 iowrite32(reg, c0);
335 }
336
337 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
338 unsigned int offset)
339 {
340 const struct aspeed_gpio_bank *bank = to_bank(offset);
341
342 if (!copro_ops || !gpio->cf_copro_bankmap)
343 return false;
344 if (!gpio->cf_copro_bankmap[offset >> 3])
345 return false;
346 if (!copro_ops->request_access)
347 return false;
348
349 /* Pause the coprocessor */
350 copro_ops->request_access(copro_data);
351
352 /* Change command source back to ARM */
353 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
354
355 /* Update cache */
356 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
357
358 return true;
359 }
360
361 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
362 unsigned int offset)
363 {
364 const struct aspeed_gpio_bank *bank = to_bank(offset);
365
366 if (!copro_ops || !gpio->cf_copro_bankmap)
367 return;
368 if (!gpio->cf_copro_bankmap[offset >> 3])
369 return;
370 if (!copro_ops->release_access)
371 return;
372
373 /* Change command source back to ColdFire */
374 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
375 GPIO_CMDSRC_COLDFIRE);
376
377 /* Restart the coprocessor */
378 copro_ops->release_access(copro_data);
379 }
380
381 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
382 {
383 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
384 const struct aspeed_gpio_bank *bank = to_bank(offset);
385
386 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
387 }
388
389 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
390 int val)
391 {
392 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
393 const struct aspeed_gpio_bank *bank = to_bank(offset);
394 void __iomem *addr;
395 u32 reg;
396
397 addr = bank_reg(gpio, bank, reg_val);
398 reg = gpio->dcache[GPIO_BANK(offset)];
399
400 if (val)
401 reg |= GPIO_BIT(offset);
402 else
403 reg &= ~GPIO_BIT(offset);
404 gpio->dcache[GPIO_BANK(offset)] = reg;
405
406 iowrite32(reg, addr);
407 }
408
409 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
410 int val)
411 {
412 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
413 unsigned long flags;
414 bool copro;
415
416 spin_lock_irqsave(&gpio->lock, flags);
417 copro = aspeed_gpio_copro_request(gpio, offset);
418
419 __aspeed_gpio_set(gc, offset, val);
420
421 if (copro)
422 aspeed_gpio_copro_release(gpio, offset);
423 spin_unlock_irqrestore(&gpio->lock, flags);
424 }
425
426 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
427 {
428 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
429 const struct aspeed_gpio_bank *bank = to_bank(offset);
430 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
431 unsigned long flags;
432 bool copro;
433 u32 reg;
434
435 if (!have_input(gpio, offset))
436 return -ENOTSUPP;
437
438 spin_lock_irqsave(&gpio->lock, flags);
439
440 reg = ioread32(addr);
441 reg &= ~GPIO_BIT(offset);
442
443 copro = aspeed_gpio_copro_request(gpio, offset);
444 iowrite32(reg, addr);
445 if (copro)
446 aspeed_gpio_copro_release(gpio, offset);
447
448 spin_unlock_irqrestore(&gpio->lock, flags);
449
450 return 0;
451 }
452
453 static int aspeed_gpio_dir_out(struct gpio_chip *gc,
454 unsigned int offset, int val)
455 {
456 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
457 const struct aspeed_gpio_bank *bank = to_bank(offset);
458 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
459 unsigned long flags;
460 bool copro;
461 u32 reg;
462
463 if (!have_output(gpio, offset))
464 return -ENOTSUPP;
465
466 spin_lock_irqsave(&gpio->lock, flags);
467
468 reg = ioread32(addr);
469 reg |= GPIO_BIT(offset);
470
471 copro = aspeed_gpio_copro_request(gpio, offset);
472 __aspeed_gpio_set(gc, offset, val);
473 iowrite32(reg, addr);
474
475 if (copro)
476 aspeed_gpio_copro_release(gpio, offset);
477 spin_unlock_irqrestore(&gpio->lock, flags);
478
479 return 0;
480 }
481
482 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
483 {
484 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
485 const struct aspeed_gpio_bank *bank = to_bank(offset);
486 unsigned long flags;
487 u32 val;
488
489 if (!have_input(gpio, offset))
490 return GPIO_LINE_DIRECTION_OUT;
491
492 if (!have_output(gpio, offset))
493 return GPIO_LINE_DIRECTION_IN;
494
495 spin_lock_irqsave(&gpio->lock, flags);
496
497 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
498
499 spin_unlock_irqrestore(&gpio->lock, flags);
500
501 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
502 }
503
504 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
505 struct aspeed_gpio **gpio,
506 const struct aspeed_gpio_bank **bank,
507 u32 *bit, int *offset)
508 {
509 struct aspeed_gpio *internal;
510
511 *offset = irqd_to_hwirq(d);
512
513 internal = irq_data_get_irq_chip_data(d);
514
515 /* This might be a bit of a questionable place to check */
516 if (!have_irq(internal, *offset))
517 return -ENOTSUPP;
518
519 *gpio = internal;
520 *bank = to_bank(*offset);
521 *bit = GPIO_BIT(*offset);
522
523 return 0;
524 }
525
526 static void aspeed_gpio_irq_ack(struct irq_data *d)
527 {
528 const struct aspeed_gpio_bank *bank;
529 struct aspeed_gpio *gpio;
530 unsigned long flags;
531 void __iomem *status_addr;
532 int rc, offset;
533 bool copro;
534 u32 bit;
535
536 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
537 if (rc)
538 return;
539
540 status_addr = bank_reg(gpio, bank, reg_irq_status);
541
542 spin_lock_irqsave(&gpio->lock, flags);
543 copro = aspeed_gpio_copro_request(gpio, offset);
544
545 iowrite32(bit, status_addr);
546
547 if (copro)
548 aspeed_gpio_copro_release(gpio, offset);
549 spin_unlock_irqrestore(&gpio->lock, flags);
550 }
551
552 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
553 {
554 const struct aspeed_gpio_bank *bank;
555 struct aspeed_gpio *gpio;
556 unsigned long flags;
557 u32 reg, bit;
558 void __iomem *addr;
559 int rc, offset;
560 bool copro;
561
562 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
563 if (rc)
564 return;
565
566 addr = bank_reg(gpio, bank, reg_irq_enable);
567
568 spin_lock_irqsave(&gpio->lock, flags);
569 copro = aspeed_gpio_copro_request(gpio, offset);
570
571 reg = ioread32(addr);
572 if (set)
573 reg |= bit;
574 else
575 reg &= ~bit;
576 iowrite32(reg, addr);
577
578 if (copro)
579 aspeed_gpio_copro_release(gpio, offset);
580 spin_unlock_irqrestore(&gpio->lock, flags);
581 }
582
583 static void aspeed_gpio_irq_mask(struct irq_data *d)
584 {
585 aspeed_gpio_irq_set_mask(d, false);
586 }
587
588 static void aspeed_gpio_irq_unmask(struct irq_data *d)
589 {
590 aspeed_gpio_irq_set_mask(d, true);
591 }
592
593 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
594 {
595 u32 type0 = 0;
596 u32 type1 = 0;
597 u32 type2 = 0;
598 u32 bit, reg;
599 const struct aspeed_gpio_bank *bank;
600 irq_flow_handler_t handler;
601 struct aspeed_gpio *gpio;
602 unsigned long flags;
603 void __iomem *addr;
604 int rc, offset;
605 bool copro;
606
607 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
608 if (rc)
609 return -EINVAL;
610
611 switch (type & IRQ_TYPE_SENSE_MASK) {
612 case IRQ_TYPE_EDGE_BOTH:
613 type2 |= bit;
614 fallthrough;
615 case IRQ_TYPE_EDGE_RISING:
616 type0 |= bit;
617 fallthrough;
618 case IRQ_TYPE_EDGE_FALLING:
619 handler = handle_edge_irq;
620 break;
621 case IRQ_TYPE_LEVEL_HIGH:
622 type0 |= bit;
623 fallthrough;
624 case IRQ_TYPE_LEVEL_LOW:
625 type1 |= bit;
626 handler = handle_level_irq;
627 break;
628 default:
629 return -EINVAL;
630 }
631
632 spin_lock_irqsave(&gpio->lock, flags);
633 copro = aspeed_gpio_copro_request(gpio, offset);
634
635 addr = bank_reg(gpio, bank, reg_irq_type0);
636 reg = ioread32(addr);
637 reg = (reg & ~bit) | type0;
638 iowrite32(reg, addr);
639
640 addr = bank_reg(gpio, bank, reg_irq_type1);
641 reg = ioread32(addr);
642 reg = (reg & ~bit) | type1;
643 iowrite32(reg, addr);
644
645 addr = bank_reg(gpio, bank, reg_irq_type2);
646 reg = ioread32(addr);
647 reg = (reg & ~bit) | type2;
648 iowrite32(reg, addr);
649
650 if (copro)
651 aspeed_gpio_copro_release(gpio, offset);
652 spin_unlock_irqrestore(&gpio->lock, flags);
653
654 irq_set_handler_locked(d, handler);
655
656 return 0;
657 }
658
659 static void aspeed_gpio_irq_handler(struct irq_desc *desc)
660 {
661 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
662 struct irq_chip *ic = irq_desc_get_chip(desc);
663 struct aspeed_gpio *data = gpiochip_get_data(gc);
664 unsigned int i, p, girq, banks;
665 unsigned long reg;
666 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
667
668 chained_irq_enter(ic, desc);
669
670 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
671 for (i = 0; i < banks; i++) {
672 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
673
674 reg = ioread32(bank_reg(data, bank, reg_irq_status));
675
676 for_each_set_bit(p, &reg, 32) {
677 girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
678 generic_handle_irq(girq);
679 }
680
681 }
682
683 chained_irq_exit(ic, desc);
684 }
685
686 static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
687 unsigned long *valid_mask,
688 unsigned int ngpios)
689 {
690 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
691 const struct aspeed_bank_props *props = gpio->config->props;
692
693 while (!is_bank_props_sentinel(props)) {
694 unsigned int offset;
695 const unsigned long int input = props->input;
696
697 /* Pretty crummy approach, but similar to GPIO core */
698 for_each_clear_bit(offset, &input, 32) {
699 unsigned int i = props->bank * 32 + offset;
700
701 if (i >= gpio->chip.ngpio)
702 break;
703
704 clear_bit(i, valid_mask);
705 }
706
707 props++;
708 }
709 }
710
711 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
712 unsigned int offset, bool enable)
713 {
714 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
715 unsigned long flags;
716 void __iomem *treg;
717 bool copro;
718 u32 val;
719
720 treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
721
722 spin_lock_irqsave(&gpio->lock, flags);
723 copro = aspeed_gpio_copro_request(gpio, offset);
724
725 val = readl(treg);
726
727 if (enable)
728 val |= GPIO_BIT(offset);
729 else
730 val &= ~GPIO_BIT(offset);
731
732 writel(val, treg);
733
734 if (copro)
735 aspeed_gpio_copro_release(gpio, offset);
736 spin_unlock_irqrestore(&gpio->lock, flags);
737
738 return 0;
739 }
740
741 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
742 {
743 if (!have_gpio(gpiochip_get_data(chip), offset))
744 return -ENODEV;
745
746 return pinctrl_gpio_request(chip->base + offset);
747 }
748
749 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
750 {
751 pinctrl_gpio_free(chip->base + offset);
752 }
753
754 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
755 u32 *cycles)
756 {
757 u64 rate;
758 u64 n;
759 u32 r;
760
761 rate = clk_get_rate(gpio->clk);
762 if (!rate)
763 return -ENOTSUPP;
764
765 n = rate * usecs;
766 r = do_div(n, 1000000);
767
768 if (n >= U32_MAX)
769 return -ERANGE;
770
771 /* At least as long as the requested time */
772 *cycles = n + (!!r);
773
774 return 0;
775 }
776
777 /* Call under gpio->lock */
778 static int register_allocated_timer(struct aspeed_gpio *gpio,
779 unsigned int offset, unsigned int timer)
780 {
781 if (WARN(gpio->offset_timer[offset] != 0,
782 "Offset %d already allocated timer %d\n",
783 offset, gpio->offset_timer[offset]))
784 return -EINVAL;
785
786 if (WARN(gpio->timer_users[timer] == UINT_MAX,
787 "Timer user count would overflow\n"))
788 return -EPERM;
789
790 gpio->offset_timer[offset] = timer;
791 gpio->timer_users[timer]++;
792
793 return 0;
794 }
795
796 /* Call under gpio->lock */
797 static int unregister_allocated_timer(struct aspeed_gpio *gpio,
798 unsigned int offset)
799 {
800 if (WARN(gpio->offset_timer[offset] == 0,
801 "No timer allocated to offset %d\n", offset))
802 return -EINVAL;
803
804 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
805 "No users recorded for timer %d\n",
806 gpio->offset_timer[offset]))
807 return -EINVAL;
808
809 gpio->timer_users[gpio->offset_timer[offset]]--;
810 gpio->offset_timer[offset] = 0;
811
812 return 0;
813 }
814
815 /* Call under gpio->lock */
816 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
817 unsigned int offset)
818 {
819 return gpio->offset_timer[offset] > 0;
820 }
821
822 /* Call under gpio->lock */
823 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
824 unsigned int timer)
825 {
826 const struct aspeed_gpio_bank *bank = to_bank(offset);
827 const u32 mask = GPIO_BIT(offset);
828 void __iomem *addr;
829 u32 val;
830
831 /* Note: Debounce timer isn't under control of the command
832 * source registers, so no need to sync with the coprocessor
833 */
834 addr = bank_reg(gpio, bank, reg_debounce_sel1);
835 val = ioread32(addr);
836 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
837
838 addr = bank_reg(gpio, bank, reg_debounce_sel2);
839 val = ioread32(addr);
840 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
841 }
842
843 static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
844 unsigned long usecs)
845 {
846 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
847 u32 requested_cycles;
848 unsigned long flags;
849 int rc;
850 int i;
851
852 if (!gpio->clk)
853 return -EINVAL;
854
855 rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
856 if (rc < 0) {
857 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
858 usecs, clk_get_rate(gpio->clk), rc);
859 return rc;
860 }
861
862 spin_lock_irqsave(&gpio->lock, flags);
863
864 if (timer_allocation_registered(gpio, offset)) {
865 rc = unregister_allocated_timer(gpio, offset);
866 if (rc < 0)
867 goto out;
868 }
869
870 /* Try to find a timer already configured for the debounce period */
871 for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
872 u32 cycles;
873
874 cycles = ioread32(gpio->base + debounce_timers[i]);
875 if (requested_cycles == cycles)
876 break;
877 }
878
879 if (i == ARRAY_SIZE(debounce_timers)) {
880 int j;
881
882 /*
883 * As there are no timers configured for the requested debounce
884 * period, find an unused timer instead
885 */
886 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
887 if (gpio->timer_users[j] == 0)
888 break;
889 }
890
891 if (j == ARRAY_SIZE(gpio->timer_users)) {
892 dev_warn(chip->parent,
893 "Debounce timers exhausted, cannot debounce for period %luus\n",
894 usecs);
895
896 rc = -EPERM;
897
898 /*
899 * We already adjusted the accounting to remove @offset
900 * as a user of its previous timer, so also configure
901 * the hardware so @offset has timers disabled for
902 * consistency.
903 */
904 configure_timer(gpio, offset, 0);
905 goto out;
906 }
907
908 i = j;
909
910 iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
911 }
912
913 if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
914 rc = -EINVAL;
915 goto out;
916 }
917
918 register_allocated_timer(gpio, offset, i);
919 configure_timer(gpio, offset, i);
920
921 out:
922 spin_unlock_irqrestore(&gpio->lock, flags);
923
924 return rc;
925 }
926
927 static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
928 {
929 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
930 unsigned long flags;
931 int rc;
932
933 spin_lock_irqsave(&gpio->lock, flags);
934
935 rc = unregister_allocated_timer(gpio, offset);
936 if (!rc)
937 configure_timer(gpio, offset, 0);
938
939 spin_unlock_irqrestore(&gpio->lock, flags);
940
941 return rc;
942 }
943
944 static int set_debounce(struct gpio_chip *chip, unsigned int offset,
945 unsigned long usecs)
946 {
947 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
948
949 if (!have_debounce(gpio, offset))
950 return -ENOTSUPP;
951
952 if (usecs)
953 return enable_debounce(chip, offset, usecs);
954
955 return disable_debounce(chip, offset);
956 }
957
958 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
959 unsigned long config)
960 {
961 unsigned long param = pinconf_to_config_param(config);
962 u32 arg = pinconf_to_config_argument(config);
963
964 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
965 return set_debounce(chip, offset, arg);
966 else if (param == PIN_CONFIG_BIAS_DISABLE ||
967 param == PIN_CONFIG_BIAS_PULL_DOWN ||
968 param == PIN_CONFIG_DRIVE_STRENGTH)
969 return pinctrl_gpio_set_config(offset, config);
970 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
971 param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
972 /* Return -ENOTSUPP to trigger emulation, as per datasheet */
973 return -ENOTSUPP;
974 else if (param == PIN_CONFIG_PERSIST_STATE)
975 return aspeed_gpio_reset_tolerance(chip, offset, arg);
976
977 return -ENOTSUPP;
978 }
979
980 /**
981 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
982 * the coprocessor for shared GPIO banks
983 * @ops: The callbacks
984 * @data: Pointer passed back to the callbacks
985 */
986 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
987 {
988 copro_data = data;
989 copro_ops = ops;
990
991 return 0;
992 }
993 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
994
995 /**
996 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
997 * bank gets marked and any access from the ARM will
998 * result in handshaking via callbacks.
999 * @desc: The GPIO to be marked
1000 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
1001 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
1002 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1003 */
1004 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
1005 u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
1006 {
1007 struct gpio_chip *chip = gpiod_to_chip(desc);
1008 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1009 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1010 const struct aspeed_gpio_bank *bank = to_bank(offset);
1011 unsigned long flags;
1012
1013 if (!gpio->cf_copro_bankmap)
1014 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
1015 if (!gpio->cf_copro_bankmap)
1016 return -ENOMEM;
1017 if (offset < 0 || offset > gpio->chip.ngpio)
1018 return -EINVAL;
1019 bindex = offset >> 3;
1020
1021 spin_lock_irqsave(&gpio->lock, flags);
1022
1023 /* Sanity check, this shouldn't happen */
1024 if (gpio->cf_copro_bankmap[bindex] == 0xff) {
1025 rc = -EIO;
1026 goto bail;
1027 }
1028 gpio->cf_copro_bankmap[bindex]++;
1029
1030 /* Switch command source */
1031 if (gpio->cf_copro_bankmap[bindex] == 1)
1032 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1033 GPIO_CMDSRC_COLDFIRE);
1034
1035 if (vreg_offset)
1036 *vreg_offset = bank->val_regs;
1037 if (dreg_offset)
1038 *dreg_offset = bank->rdata_reg;
1039 if (bit)
1040 *bit = GPIO_OFFSET(offset);
1041 bail:
1042 spin_unlock_irqrestore(&gpio->lock, flags);
1043 return rc;
1044 }
1045 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
1046
1047 /**
1048 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1049 * @desc: The GPIO to be marked
1050 */
1051 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
1052 {
1053 struct gpio_chip *chip = gpiod_to_chip(desc);
1054 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1055 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1056 const struct aspeed_gpio_bank *bank = to_bank(offset);
1057 unsigned long flags;
1058
1059 if (!gpio->cf_copro_bankmap)
1060 return -ENXIO;
1061
1062 if (offset < 0 || offset > gpio->chip.ngpio)
1063 return -EINVAL;
1064 bindex = offset >> 3;
1065
1066 spin_lock_irqsave(&gpio->lock, flags);
1067
1068 /* Sanity check, this shouldn't happen */
1069 if (gpio->cf_copro_bankmap[bindex] == 0) {
1070 rc = -EIO;
1071 goto bail;
1072 }
1073 gpio->cf_copro_bankmap[bindex]--;
1074
1075 /* Switch command source */
1076 if (gpio->cf_copro_bankmap[bindex] == 0)
1077 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1078 GPIO_CMDSRC_ARM);
1079 bail:
1080 spin_unlock_irqrestore(&gpio->lock, flags);
1081 return rc;
1082 }
1083 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
1084
1085 /*
1086 * Any banks not specified in a struct aspeed_bank_props array are assumed to
1087 * have the properties:
1088 *
1089 * { .input = 0xffffffff, .output = 0xffffffff }
1090 */
1091
1092 static const struct aspeed_bank_props ast2400_bank_props[] = {
1093 /* input output */
1094 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1095 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1096 { },
1097 };
1098
1099 static const struct aspeed_gpio_config ast2400_config =
1100 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1101 { .nr_gpios = 220, .props = ast2400_bank_props, };
1102
1103 static const struct aspeed_bank_props ast2500_bank_props[] = {
1104 /* input output */
1105 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1106 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1107 { 7, 0x000000ff, 0x000000ff }, /* AC */
1108 { },
1109 };
1110
1111 static const struct aspeed_gpio_config ast2500_config =
1112 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1113 { .nr_gpios = 232, .props = ast2500_bank_props, };
1114
1115 static const struct aspeed_bank_props ast2600_bank_props[] = {
1116 /* input output */
1117 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */
1118 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
1119 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
1120 { },
1121 };
1122
1123 static const struct aspeed_gpio_config ast2600_config =
1124 /*
1125 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
1126 * We expect ngpio being set in the device tree and this is a fallback
1127 * option.
1128 */
1129 { .nr_gpios = 208, .props = ast2600_bank_props, };
1130
1131 static const struct of_device_id aspeed_gpio_of_table[] = {
1132 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1133 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1134 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1135 {}
1136 };
1137 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
1138
1139 static int __init aspeed_gpio_probe(struct platform_device *pdev)
1140 {
1141 const struct of_device_id *gpio_id;
1142 struct aspeed_gpio *gpio;
1143 int rc, i, banks, err;
1144 u32 ngpio;
1145
1146 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
1147 if (!gpio)
1148 return -ENOMEM;
1149
1150 gpio->base = devm_platform_ioremap_resource(pdev, 0);
1151 if (IS_ERR(gpio->base))
1152 return PTR_ERR(gpio->base);
1153
1154 spin_lock_init(&gpio->lock);
1155
1156 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
1157 if (!gpio_id)
1158 return -EINVAL;
1159
1160 gpio->clk = of_clk_get(pdev->dev.of_node, 0);
1161 if (IS_ERR(gpio->clk)) {
1162 dev_warn(&pdev->dev,
1163 "Failed to get clock from devicetree, debouncing disabled\n");
1164 gpio->clk = NULL;
1165 }
1166
1167 gpio->config = gpio_id->data;
1168
1169 gpio->chip.parent = &pdev->dev;
1170 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
1171 gpio->chip.ngpio = (u16) ngpio;
1172 if (err)
1173 gpio->chip.ngpio = gpio->config->nr_gpios;
1174 gpio->chip.direction_input = aspeed_gpio_dir_in;
1175 gpio->chip.direction_output = aspeed_gpio_dir_out;
1176 gpio->chip.get_direction = aspeed_gpio_get_direction;
1177 gpio->chip.request = aspeed_gpio_request;
1178 gpio->chip.free = aspeed_gpio_free;
1179 gpio->chip.get = aspeed_gpio_get;
1180 gpio->chip.set = aspeed_gpio_set;
1181 gpio->chip.set_config = aspeed_gpio_set_config;
1182 gpio->chip.label = dev_name(&pdev->dev);
1183 gpio->chip.base = -1;
1184
1185 /* Allocate a cache of the output registers */
1186 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
1187 gpio->dcache = devm_kcalloc(&pdev->dev,
1188 banks, sizeof(u32), GFP_KERNEL);
1189 if (!gpio->dcache)
1190 return -ENOMEM;
1191
1192 /*
1193 * Populate it with initial values read from the HW and switch
1194 * all command sources to the ARM by default
1195 */
1196 for (i = 0; i < banks; i++) {
1197 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
1198 void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
1199 gpio->dcache[i] = ioread32(addr);
1200 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
1201 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
1202 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
1203 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
1204 }
1205
1206 /* Optionally set up an irqchip if there is an IRQ */
1207 rc = platform_get_irq(pdev, 0);
1208 if (rc > 0) {
1209 struct gpio_irq_chip *girq;
1210
1211 gpio->irq = rc;
1212 girq = &gpio->chip.irq;
1213 girq->chip = &gpio->irqc;
1214 girq->chip->name = dev_name(&pdev->dev);
1215 girq->chip->irq_ack = aspeed_gpio_irq_ack;
1216 girq->chip->irq_mask = aspeed_gpio_irq_mask;
1217 girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
1218 girq->chip->irq_set_type = aspeed_gpio_set_type;
1219 girq->parent_handler = aspeed_gpio_irq_handler;
1220 girq->num_parents = 1;
1221 girq->parents = devm_kcalloc(&pdev->dev, 1,
1222 sizeof(*girq->parents),
1223 GFP_KERNEL);
1224 if (!girq->parents)
1225 return -ENOMEM;
1226 girq->parents[0] = gpio->irq;
1227 girq->default_type = IRQ_TYPE_NONE;
1228 girq->handler = handle_bad_irq;
1229 girq->init_valid_mask = aspeed_init_irq_valid_mask;
1230 }
1231
1232 gpio->offset_timer =
1233 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
1234 if (!gpio->offset_timer)
1235 return -ENOMEM;
1236
1237 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
1238 if (rc < 0)
1239 return rc;
1240
1241 return 0;
1242 }
1243
1244 static struct platform_driver aspeed_gpio_driver = {
1245 .driver = {
1246 .name = KBUILD_MODNAME,
1247 .of_match_table = aspeed_gpio_of_table,
1248 },
1249 };
1250
1251 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
1252
1253 MODULE_DESCRIPTION("Aspeed GPIO Driver");
1254 MODULE_LICENSE("GPL");
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