drivers/gpio/gpio-brcmstb.c

   1 /*
   2  * Copyright (C) 2015-2017 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/bitops.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/module.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/irqchip/chained_irq.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/bitops.h>
  23
  24 enum gio_reg_index {
  25         GIO_REG_ODEN = 0,
  26         GIO_REG_DATA,
  27         GIO_REG_IODIR,
  28         GIO_REG_EC,
  29         GIO_REG_EI,
  30         GIO_REG_MASK,
  31         GIO_REG_LEVEL,
  32         GIO_REG_STAT,
  33         NUMBER_OF_GIO_REGISTERS
  34 };
  35
  36 #define GIO_BANK_SIZE           (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
  37 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
  38 #define GIO_ODEN(bank)          GIO_BANK_OFF(bank, GIO_REG_ODEN)
  39 #define GIO_DATA(bank)          GIO_BANK_OFF(bank, GIO_REG_DATA)
  40 #define GIO_IODIR(bank)         GIO_BANK_OFF(bank, GIO_REG_IODIR)
  41 #define GIO_EC(bank)            GIO_BANK_OFF(bank, GIO_REG_EC)
  42 #define GIO_EI(bank)            GIO_BANK_OFF(bank, GIO_REG_EI)
  43 #define GIO_MASK(bank)          GIO_BANK_OFF(bank, GIO_REG_MASK)
  44 #define GIO_LEVEL(bank)         GIO_BANK_OFF(bank, GIO_REG_LEVEL)
  45 #define GIO_STAT(bank)          GIO_BANK_OFF(bank, GIO_REG_STAT)
  46
  47 struct brcmstb_gpio_bank {
  48         struct list_head node;
  49         int id;
  50         struct gpio_chip gc;
  51         struct brcmstb_gpio_priv *parent_priv;
  52         u32 width;
  53         u32 wake_active;
  54         u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
  55 };
  56
  57 struct brcmstb_gpio_priv {
  58         struct list_head bank_list;
  59         void __iomem *reg_base;
  60         struct platform_device *pdev;
  61         struct irq_domain *irq_domain;
  62         struct irq_chip irq_chip;
  63         int parent_irq;
  64         int gpio_base;
  65         int num_gpios;
  66         int parent_wake_irq;
  67 };
  68
  69 #define MAX_GPIO_PER_BANK       32
  70 #define GPIO_BANK(gpio)         ((gpio) >> 5)
  71 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
  72 #define GPIO_BIT(gpio)          ((gpio) & (MAX_GPIO_PER_BANK - 1))
  73
  74 static inline struct brcmstb_gpio_priv *
  75 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
  76 {
  77         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  78         return bank->parent_priv;
  79 }
  80
  81 static unsigned long
  82 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
  83 {
  84         void __iomem *reg_base = bank->parent_priv->reg_base;
  85
  86         return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
  87                bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
  88 }
  89
  90 static unsigned long
  91 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
  92 {
  93         unsigned long status;
  94         unsigned long flags;
  95
  96         spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
  97         status = __brcmstb_gpio_get_active_irqs(bank);
  98         spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
  99
 100         return status;
 101 }
 102
 103 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
 104                                         struct brcmstb_gpio_bank *bank)
 105 {
 106         return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
 107 }
 108
 109 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
 110                 unsigned int hwirq, bool enable)
 111 {
 112         struct gpio_chip *gc = &bank->gc;
 113         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 114         u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
 115         u32 imask;
 116         unsigned long flags;
 117
 118         spin_lock_irqsave(&gc->bgpio_lock, flags);
 119         imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
 120         if (enable)
 121                 imask |= mask;
 122         else
 123                 imask &= ~mask;
 124         gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
 125         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 126 }
 127
 128 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 129 {
 130         struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
 131         /* gc_offset is relative to this gpio_chip; want real offset */
 132         int hwirq = offset + (gc->base - priv->gpio_base);
 133
 134         if (hwirq >= priv->num_gpios)
 135                 return -ENXIO;
 136         return irq_create_mapping(priv->irq_domain, hwirq);
 137 }
 138
 139 /* -------------------- IRQ chip functions -------------------- */
 140
 141 static void brcmstb_gpio_irq_mask(struct irq_data *d)
 142 {
 143         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 144         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 145
 146         brcmstb_gpio_set_imask(bank, d->hwirq, false);
 147 }
 148
 149 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
 150 {
 151         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 152         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 153
 154         brcmstb_gpio_set_imask(bank, d->hwirq, true);
 155 }
 156
 157 static void brcmstb_gpio_irq_ack(struct irq_data *d)
 158 {
 159         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 160         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 161         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 162         u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
 163
 164         gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
 165 }
 166
 167 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 168 {
 169         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 170         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 171         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 172         u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
 173         u32 edge_insensitive, iedge_insensitive;
 174         u32 edge_config, iedge_config;
 175         u32 level, ilevel;
 176         unsigned long flags;
 177
 178         switch (type) {
 179         case IRQ_TYPE_LEVEL_LOW:
 180                 level = mask;
 181                 edge_config = 0;
 182                 edge_insensitive = 0;
 183                 break;
 184         case IRQ_TYPE_LEVEL_HIGH:
 185                 level = mask;
 186                 edge_config = mask;
 187                 edge_insensitive = 0;
 188                 break;
 189         case IRQ_TYPE_EDGE_FALLING:
 190                 level = 0;
 191                 edge_config = 0;
 192                 edge_insensitive = 0;
 193                 break;
 194         case IRQ_TYPE_EDGE_RISING:
 195                 level = 0;
 196                 edge_config = mask;
 197                 edge_insensitive = 0;
 198                 break;
 199         case IRQ_TYPE_EDGE_BOTH:
 200                 level = 0;
 201                 edge_config = 0;  /* don't care, but want known value */
 202                 edge_insensitive = mask;
 203                 break;
 204         default:
 205                 return -EINVAL;
 206         }
 207
 208         spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
 209
 210         iedge_config = bank->gc.read_reg(priv->reg_base +
 211                         GIO_EC(bank->id)) & ~mask;
 212         iedge_insensitive = bank->gc.read_reg(priv->reg_base +
 213                         GIO_EI(bank->id)) & ~mask;
 214         ilevel = bank->gc.read_reg(priv->reg_base +
 215                         GIO_LEVEL(bank->id)) & ~mask;
 216
 217         bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
 218                         iedge_config | edge_config);
 219         bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
 220                         iedge_insensitive | edge_insensitive);
 221         bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
 222                         ilevel | level);
 223
 224         spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
 225         return 0;
 226 }
 227
 228 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
 229                 unsigned int enable)
 230 {
 231         int ret = 0;
 232
 233         if (enable)
 234                 ret = enable_irq_wake(priv->parent_wake_irq);
 235         else
 236                 ret = disable_irq_wake(priv->parent_wake_irq);
 237         if (ret)
 238                 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
 239                                 enable ? "enable" : "disable");
 240         return ret;
 241 }
 242
 243 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 244 {
 245         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 246         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 247         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 248         u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
 249
 250         /*
 251          * Do not do anything specific for now, suspend/resume callbacks will
 252          * configure the interrupt mask appropriately
 253          */
 254         if (enable)
 255                 bank->wake_active |= mask;
 256         else
 257                 bank->wake_active &= ~mask;
 258
 259         return brcmstb_gpio_priv_set_wake(priv, enable);
 260 }
 261
 262 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
 263 {
 264         struct brcmstb_gpio_priv *priv = data;
 265
 266         if (!priv || irq != priv->parent_wake_irq)
 267                 return IRQ_NONE;
 268
 269         /* Nothing to do */
 270         return IRQ_HANDLED;
 271 }
 272
 273 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
 274 {
 275         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 276         struct irq_domain *domain = priv->irq_domain;
 277         int hwbase = bank->gc.base - priv->gpio_base;
 278         unsigned long status;
 279
 280         while ((status = brcmstb_gpio_get_active_irqs(bank))) {
 281                 unsigned int irq, offset;
 282
 283                 for_each_set_bit(offset, &status, 32) {
 284                         if (offset >= bank->width)
 285                                 dev_warn(&priv->pdev->dev,
 286                                          "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
 287                                          bank->id, offset);
 288                         irq = irq_linear_revmap(domain, hwbase + offset);
 289                         generic_handle_irq(irq);
 290                 }
 291         }
 292 }
 293
 294 /* Each UPG GIO block has one IRQ for all banks */
 295 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
 296 {
 297         struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
 298         struct irq_chip *chip = irq_desc_get_chip(desc);
 299         struct brcmstb_gpio_bank *bank;
 300
 301         /* Interrupts weren't properly cleared during probe */
 302         BUG_ON(!priv || !chip);
 303
 304         chained_irq_enter(chip, desc);
 305         list_for_each_entry(bank, &priv->bank_list, node)
 306                 brcmstb_gpio_irq_bank_handler(bank);
 307         chained_irq_exit(chip, desc);
 308 }
 309
 310 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
 311                 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
 312 {
 313         struct brcmstb_gpio_bank *bank;
 314         int i = 0;
 315
 316         /* banks are in descending order */
 317         list_for_each_entry_reverse(bank, &priv->bank_list, node) {
 318                 i += bank->gc.ngpio;
 319                 if (hwirq < i)
 320                         return bank;
 321         }
 322         return NULL;
 323 }
 324
 325 /*
 326  * This lock class tells lockdep that GPIO irqs are in a different
 327  * category than their parents, so it won't report false recursion.
 328  */
 329 static struct lock_class_key brcmstb_gpio_irq_lock_class;
 330 static struct lock_class_key brcmstb_gpio_irq_request_class;
 331
 332
 333 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 334                 irq_hw_number_t hwirq)
 335 {
 336         struct brcmstb_gpio_priv *priv = d->host_data;
 337         struct brcmstb_gpio_bank *bank =
 338                 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
 339         struct platform_device *pdev = priv->pdev;
 340         int ret;
 341
 342         if (!bank)
 343                 return -EINVAL;
 344
 345         dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
 346                 irq, (int)hwirq, bank->id);
 347         ret = irq_set_chip_data(irq, &bank->gc);
 348         if (ret < 0)
 349                 return ret;
 350         irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
 351                               &brcmstb_gpio_irq_request_class);
 352         irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
 353         irq_set_noprobe(irq);
 354         return 0;
 355 }
 356
 357 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
 358 {
 359         irq_set_chip_and_handler(irq, NULL, NULL);
 360         irq_set_chip_data(irq, NULL);
 361 }
 362
 363 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
 364         .map = brcmstb_gpio_irq_map,
 365         .unmap = brcmstb_gpio_irq_unmap,
 366         .xlate = irq_domain_xlate_twocell,
 367 };
 368
 369 /* Make sure that the number of banks matches up between properties */
 370 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
 371                 struct device_node *np, struct resource *res)
 372 {
 373         int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
 374         int num_banks =
 375                 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
 376
 377         if (res_num_banks != num_banks) {
 378                 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
 379                                 res_num_banks, num_banks);
 380                 return -EINVAL;
 381         } else {
 382                 return 0;
 383         }
 384 }
 385
 386 static int brcmstb_gpio_remove(struct platform_device *pdev)
 387 {
 388         struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
 389         struct brcmstb_gpio_bank *bank;
 390         int offset, ret = 0, virq;
 391
 392         if (!priv) {
 393                 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
 394                 return -EFAULT;
 395         }
 396
 397         if (priv->parent_irq > 0)
 398                 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
 399
 400         /* Remove all IRQ mappings and delete the domain */
 401         if (priv->irq_domain) {
 402                 for (offset = 0; offset < priv->num_gpios; offset++) {
 403                         virq = irq_find_mapping(priv->irq_domain, offset);
 404                         irq_dispose_mapping(virq);
 405                 }
 406                 irq_domain_remove(priv->irq_domain);
 407         }
 408
 409         /*
 410          * You can lose return values below, but we report all errors, and it's
 411          * more important to actually perform all of the steps.
 412          */
 413         list_for_each_entry(bank, &priv->bank_list, node)
 414                 gpiochip_remove(&bank->gc);
 415
 416         return ret;
 417 }
 418
 419 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
 420                 const struct of_phandle_args *gpiospec, u32 *flags)
 421 {
 422         struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
 423         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 424         int offset;
 425
 426         if (gc->of_gpio_n_cells != 2) {
 427                 WARN_ON(1);
 428                 return -EINVAL;
 429         }
 430
 431         if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
 432                 return -EINVAL;
 433
 434         offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
 435         if (offset >= gc->ngpio || offset < 0)
 436                 return -EINVAL;
 437
 438         if (unlikely(offset >= bank->width)) {
 439                 dev_warn_ratelimited(&priv->pdev->dev,
 440                         "Received request for invalid GPIO offset %d\n",
 441                         gpiospec->args[0]);
 442         }
 443
 444         if (flags)
 445                 *flags = gpiospec->args[1];
 446
 447         return offset;
 448 }
 449
 450 /* priv->parent_irq and priv->num_gpios must be set before calling */
 451 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
 452                 struct brcmstb_gpio_priv *priv)
 453 {
 454         struct device *dev = &pdev->dev;
 455         struct device_node *np = dev->of_node;
 456         int err;
 457
 458         priv->irq_domain =
 459                 irq_domain_add_linear(np, priv->num_gpios,
 460                                       &brcmstb_gpio_irq_domain_ops,
 461                                       priv);
 462         if (!priv->irq_domain) {
 463                 dev_err(dev, "Couldn't allocate IRQ domain\n");
 464                 return -ENXIO;
 465         }
 466
 467         if (of_property_read_bool(np, "wakeup-source")) {
 468                 priv->parent_wake_irq = platform_get_irq(pdev, 1);
 469                 if (priv->parent_wake_irq < 0) {
 470                         priv->parent_wake_irq = 0;
 471                         dev_warn(dev,
 472                                 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
 473                 } else {
 474                         /*
 475                          * Set wakeup capability so we can process boot-time
 476                          * "wakeups" (e.g., from S5 cold boot)
 477                          */
 478                         device_set_wakeup_capable(dev, true);
 479                         device_wakeup_enable(dev);
 480                         err = devm_request_irq(dev, priv->parent_wake_irq,
 481                                                brcmstb_gpio_wake_irq_handler,
 482                                                IRQF_SHARED,
 483                                                "brcmstb-gpio-wake", priv);
 484
 485                         if (err < 0) {
 486                                 dev_err(dev, "Couldn't request wake IRQ");
 487                                 goto out_free_domain;
 488                         }
 489                 }
 490         }
 491
 492         priv->irq_chip.name = dev_name(dev);
 493         priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
 494         priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
 495         priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
 496         priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
 497         priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
 498
 499         if (priv->parent_wake_irq)
 500                 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
 501
 502         irq_set_chained_handler_and_data(priv->parent_irq,
 503                                          brcmstb_gpio_irq_handler, priv);
 504         irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
 505
 506         return 0;
 507
 508 out_free_domain:
 509         irq_domain_remove(priv->irq_domain);
 510
 511         return err;
 512 }
 513
 514 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
 515                                    struct brcmstb_gpio_bank *bank)
 516 {
 517         struct gpio_chip *gc = &bank->gc;
 518         unsigned int i;
 519
 520         for (i = 0; i < GIO_REG_STAT; i++)
 521                 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
 522                                                    GIO_BANK_OFF(bank->id, i));
 523 }
 524
 525 static void brcmstb_gpio_quiesce(struct device *dev, bool save)
 526 {
 527         struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
 528         struct brcmstb_gpio_bank *bank;
 529         struct gpio_chip *gc;
 530         u32 imask;
 531
 532         /* disable non-wake interrupt */
 533         if (priv->parent_irq >= 0)
 534                 disable_irq(priv->parent_irq);
 535
 536         list_for_each_entry(bank, &priv->bank_list, node) {
 537                 gc = &bank->gc;
 538
 539                 if (save)
 540                         brcmstb_gpio_bank_save(priv, bank);
 541
 542                 /* Unmask GPIOs which have been flagged as wake-up sources */
 543                 if (priv->parent_wake_irq)
 544                         imask = bank->wake_active;
 545                 else
 546                         imask = 0;
 547                 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
 548                                imask);
 549         }
 550 }
 551
 552 static void brcmstb_gpio_shutdown(struct platform_device *pdev)
 553 {
 554         /* Enable GPIO for S5 cold boot */
 555         brcmstb_gpio_quiesce(&pdev->dev, false);
 556 }
 557
 558 #ifdef CONFIG_PM_SLEEP
 559 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
 560                                       struct brcmstb_gpio_bank *bank)
 561 {
 562         struct gpio_chip *gc = &bank->gc;
 563         unsigned int i;
 564
 565         for (i = 0; i < GIO_REG_STAT; i++)
 566                 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
 567                               bank->saved_regs[i]);
 568 }
 569
 570 static int brcmstb_gpio_suspend(struct device *dev)
 571 {
 572         brcmstb_gpio_quiesce(dev, true);
 573         return 0;
 574 }
 575
 576 static int brcmstb_gpio_resume(struct device *dev)
 577 {
 578         struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
 579         struct brcmstb_gpio_bank *bank;
 580         bool need_wakeup_event = false;
 581
 582         list_for_each_entry(bank, &priv->bank_list, node) {
 583                 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
 584                 brcmstb_gpio_bank_restore(priv, bank);
 585         }
 586
 587         if (priv->parent_wake_irq && need_wakeup_event)
 588                 pm_wakeup_event(dev, 0);
 589
 590         /* enable non-wake interrupt */
 591         if (priv->parent_irq >= 0)
 592                 enable_irq(priv->parent_irq);
 593
 594         return 0;
 595 }
 596
 597 #else
 598 #define brcmstb_gpio_suspend    NULL
 599 #define brcmstb_gpio_resume     NULL
 600 #endif /* CONFIG_PM_SLEEP */
 601
 602 static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
 603         .suspend_noirq  = brcmstb_gpio_suspend,
 604         .resume_noirq = brcmstb_gpio_resume,
 605 };
 606
 607 static int brcmstb_gpio_probe(struct platform_device *pdev)
 608 {
 609         struct device *dev = &pdev->dev;
 610         struct device_node *np = dev->of_node;
 611         void __iomem *reg_base;
 612         struct brcmstb_gpio_priv *priv;
 613         struct resource *res;
 614         struct property *prop;
 615         const __be32 *p;
 616         u32 bank_width;
 617         int num_banks = 0;
 618         int err;
 619         static int gpio_base;
 620         unsigned long flags = 0;
 621         bool need_wakeup_event = false;
 622
 623         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 624         if (!priv)
 625                 return -ENOMEM;
 626         platform_set_drvdata(pdev, priv);
 627         INIT_LIST_HEAD(&priv->bank_list);
 628
 629         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 630         reg_base = devm_ioremap_resource(dev, res);
 631         if (IS_ERR(reg_base))
 632                 return PTR_ERR(reg_base);
 633
 634         priv->gpio_base = gpio_base;
 635         priv->reg_base = reg_base;
 636         priv->pdev = pdev;
 637
 638         if (of_property_read_bool(np, "interrupt-controller")) {
 639                 priv->parent_irq = platform_get_irq(pdev, 0);
 640                 if (priv->parent_irq <= 0) {
 641                         dev_err(dev, "Couldn't get IRQ");
 642                         return -ENOENT;
 643                 }
 644         } else {
 645                 priv->parent_irq = -ENOENT;
 646         }
 647
 648         if (brcmstb_gpio_sanity_check_banks(dev, np, res))
 649                 return -EINVAL;
 650
 651         /*
 652          * MIPS endianness is configured by boot strap, which also reverses all
 653          * bus endianness (i.e., big-endian CPU + big endian bus ==> native
 654          * endian I/O).
 655          *
 656          * Other architectures (e.g., ARM) either do not support big endian, or
 657          * else leave I/O in little endian mode.
 658          */
 659 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
 660         flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
 661 #endif
 662
 663         of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
 664                         bank_width) {
 665                 struct brcmstb_gpio_bank *bank;
 666                 struct gpio_chip *gc;
 667
 668                 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
 669                 if (!bank) {
 670                         err = -ENOMEM;
 671                         goto fail;
 672                 }
 673
 674                 bank->parent_priv = priv;
 675                 bank->id = num_banks;
 676                 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
 677                         dev_err(dev, "Invalid bank width %d\n", bank_width);
 678                         err = -EINVAL;
 679                         goto fail;
 680                 } else {
 681                         bank->width = bank_width;
 682                 }
 683
 684                 /*
 685                  * Regs are 4 bytes wide, have data reg, no set/clear regs,
 686                  * and direction bits have 0 = output and 1 = input
 687                  */
 688                 gc = &bank->gc;
 689                 err = bgpio_init(gc, dev, 4,
 690                                 reg_base + GIO_DATA(bank->id),
 691                                 NULL, NULL, NULL,
 692                                 reg_base + GIO_IODIR(bank->id), flags);
 693                 if (err) {
 694                         dev_err(dev, "bgpio_init() failed\n");
 695                         goto fail;
 696                 }
 697
 698                 gc->of_node = np;
 699                 gc->owner = THIS_MODULE;
 700                 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
 701                 if (!gc->label) {
 702                         err = -ENOMEM;
 703                         goto fail;
 704                 }
 705                 gc->base = gpio_base;
 706                 gc->of_gpio_n_cells = 2;
 707                 gc->of_xlate = brcmstb_gpio_of_xlate;
 708                 /* not all ngpio lines are valid, will use bank width later */
 709                 gc->ngpio = MAX_GPIO_PER_BANK;
 710                 if (priv->parent_irq > 0)
 711                         gc->to_irq = brcmstb_gpio_to_irq;
 712
 713                 /*
 714                  * Mask all interrupts by default, since wakeup interrupts may
 715                  * be retained from S5 cold boot
 716                  */
 717                 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
 718                 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
 719
 720                 err = gpiochip_add_data(gc, bank);
 721                 if (err) {
 722                         dev_err(dev, "Could not add gpiochip for bank %d\n",
 723                                         bank->id);
 724                         goto fail;
 725                 }
 726                 gpio_base += gc->ngpio;
 727
 728                 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
 729                         gc->base, gc->ngpio, bank->width);
 730
 731                 /* Everything looks good, so add bank to list */
 732                 list_add(&bank->node, &priv->bank_list);
 733
 734                 num_banks++;
 735         }
 736
 737         priv->num_gpios = gpio_base - priv->gpio_base;
 738         if (priv->parent_irq > 0) {
 739                 err = brcmstb_gpio_irq_setup(pdev, priv);
 740                 if (err)
 741                         goto fail;
 742         }
 743
 744         dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
 745                         num_banks, priv->gpio_base, gpio_base - 1);
 746
 747         if (priv->parent_wake_irq && need_wakeup_event)
 748                 pm_wakeup_event(dev, 0);
 749
 750         return 0;
 751
 752 fail:
 753         (void) brcmstb_gpio_remove(pdev);
 754         return err;
 755 }
 756
 757 static const struct of_device_id brcmstb_gpio_of_match[] = {
 758         { .compatible = "brcm,brcmstb-gpio" },
 759         {},
 760 };
 761
 762 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
 763
 764 static struct platform_driver brcmstb_gpio_driver = {
 765         .driver = {
 766                 .name = "brcmstb-gpio",
 767                 .of_match_table = brcmstb_gpio_of_match,
 768                 .pm = &brcmstb_gpio_pm_ops,
 769         },
 770         .probe = brcmstb_gpio_probe,
 771         .remove = brcmstb_gpio_remove,
 772         .shutdown = brcmstb_gpio_shutdown,
 773 };
 774 module_platform_driver(brcmstb_gpio_driver);
 775
 776 MODULE_AUTHOR("Gregory Fong");
 777 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
 778 MODULE_LICENSE("GPL v2");