drivers/gpio/gpio-brcmstb.c

   1 /*
   2  * Copyright (C) 2015-2017 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/bitops.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/module.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/irqchip/chained_irq.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/bitops.h>
  23
  24 enum gio_reg_index {
  25         GIO_REG_ODEN = 0,
  26         GIO_REG_DATA,
  27         GIO_REG_IODIR,
  28         GIO_REG_EC,
  29         GIO_REG_EI,
  30         GIO_REG_MASK,
  31         GIO_REG_LEVEL,
  32         GIO_REG_STAT,
  33         NUMBER_OF_GIO_REGISTERS
  34 };
  35
  36 #define GIO_BANK_SIZE           (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
  37 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
  38 #define GIO_ODEN(bank)          GIO_BANK_OFF(bank, GIO_REG_ODEN)
  39 #define GIO_DATA(bank)          GIO_BANK_OFF(bank, GIO_REG_DATA)
  40 #define GIO_IODIR(bank)         GIO_BANK_OFF(bank, GIO_REG_IODIR)
  41 #define GIO_EC(bank)            GIO_BANK_OFF(bank, GIO_REG_EC)
  42 #define GIO_EI(bank)            GIO_BANK_OFF(bank, GIO_REG_EI)
  43 #define GIO_MASK(bank)          GIO_BANK_OFF(bank, GIO_REG_MASK)
  44 #define GIO_LEVEL(bank)         GIO_BANK_OFF(bank, GIO_REG_LEVEL)
  45 #define GIO_STAT(bank)          GIO_BANK_OFF(bank, GIO_REG_STAT)
  46
  47 struct brcmstb_gpio_bank {
  48         struct list_head node;
  49         int id;
  50         struct gpio_chip gc;
  51         struct brcmstb_gpio_priv *parent_priv;
  52         u32 width;
  53         u32 wake_active;
  54         u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
  55 };
  56
  57 struct brcmstb_gpio_priv {
  58         struct list_head bank_list;
  59         void __iomem *reg_base;
  60         struct platform_device *pdev;
  61         struct irq_domain *irq_domain;
  62         struct irq_chip irq_chip;
  63         int parent_irq;
  64         int gpio_base;
  65         int num_gpios;
  66         int parent_wake_irq;
  67 };
  68
  69 #define MAX_GPIO_PER_BANK       32
  70 #define GPIO_BANK(gpio)         ((gpio) >> 5)
  71 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
  72 #define GPIO_BIT(gpio)          ((gpio) & (MAX_GPIO_PER_BANK - 1))
  73
  74 static inline struct brcmstb_gpio_priv *
  75 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
  76 {
  77         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  78         return bank->parent_priv;
  79 }
  80
  81 static unsigned long
  82 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
  83 {
  84         void __iomem *reg_base = bank->parent_priv->reg_base;
  85
  86         return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
  87                bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
  88 }
  89
  90 static unsigned long
  91 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
  92 {
  93         unsigned long status;
  94         unsigned long flags;
  95
  96         spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
  97         status = __brcmstb_gpio_get_active_irqs(bank);
  98         spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
  99
 100         return status;
 101 }
 102
 103 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
 104                                         struct brcmstb_gpio_bank *bank)
 105 {
 106         return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
 107 }
 108
 109 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
 110                 unsigned int hwirq, bool enable)
 111 {
 112         struct gpio_chip *gc = &bank->gc;
 113         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 114         u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
 115         u32 imask;
 116         unsigned long flags;
 117
 118         spin_lock_irqsave(&gc->bgpio_lock, flags);
 119         imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
 120         if (enable)
 121                 imask |= mask;
 122         else
 123                 imask &= ~mask;
 124         gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
 125         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 126 }
 127
 128 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 129 {
 130         struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
 131         /* gc_offset is relative to this gpio_chip; want real offset */
 132         int hwirq = offset + (gc->base - priv->gpio_base);
 133
 134         if (hwirq >= priv->num_gpios)
 135                 return -ENXIO;
 136         return irq_create_mapping(priv->irq_domain, hwirq);
 137 }
 138
 139 /* -------------------- IRQ chip functions -------------------- */
 140
 141 static void brcmstb_gpio_irq_mask(struct irq_data *d)
 142 {
 143         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 144         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 145
 146         brcmstb_gpio_set_imask(bank, d->hwirq, false);
 147 }
 148
 149 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
 150 {
 151         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 152         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 153
 154         brcmstb_gpio_set_imask(bank, d->hwirq, true);
 155 }
 156
 157 static void brcmstb_gpio_irq_ack(struct irq_data *d)
 158 {
 159         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 160         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 161         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 162         u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
 163
 164         gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
 165 }
 166
 167 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 168 {
 169         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 170         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 171         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 172         u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
 173         u32 edge_insensitive, iedge_insensitive;
 174         u32 edge_config, iedge_config;
 175         u32 level, ilevel;
 176         unsigned long flags;
 177
 178         switch (type) {
 179         case IRQ_TYPE_LEVEL_LOW:
 180                 level = mask;
 181                 edge_config = 0;
 182                 edge_insensitive = 0;
 183                 break;
 184         case IRQ_TYPE_LEVEL_HIGH:
 185                 level = mask;
 186                 edge_config = mask;
 187                 edge_insensitive = 0;
 188                 break;
 189         case IRQ_TYPE_EDGE_FALLING:
 190                 level = 0;
 191                 edge_config = 0;
 192                 edge_insensitive = 0;
 193                 break;
 194         case IRQ_TYPE_EDGE_RISING:
 195                 level = 0;
 196                 edge_config = mask;
 197                 edge_insensitive = 0;
 198                 break;
 199         case IRQ_TYPE_EDGE_BOTH:
 200                 level = 0;
 201                 edge_config = 0;  /* don't care, but want known value */
 202                 edge_insensitive = mask;
 203                 break;
 204         default:
 205                 return -EINVAL;
 206         }
 207
 208         spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
 209
 210         iedge_config = bank->gc.read_reg(priv->reg_base +
 211                         GIO_EC(bank->id)) & ~mask;
 212         iedge_insensitive = bank->gc.read_reg(priv->reg_base +
 213                         GIO_EI(bank->id)) & ~mask;
 214         ilevel = bank->gc.read_reg(priv->reg_base +
 215                         GIO_LEVEL(bank->id)) & ~mask;
 216
 217         bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
 218                         iedge_config | edge_config);
 219         bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
 220                         iedge_insensitive | edge_insensitive);
 221         bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
 222                         ilevel | level);
 223
 224         spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
 225         return 0;
 226 }
 227
 228 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
 229                 unsigned int enable)
 230 {
 231         int ret = 0;
 232
 233         if (enable)
 234                 ret = enable_irq_wake(priv->parent_wake_irq);
 235         else
 236                 ret = disable_irq_wake(priv->parent_wake_irq);
 237         if (ret)
 238                 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
 239                                 enable ? "enable" : "disable");
 240         return ret;
 241 }
 242
 243 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 244 {
 245         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 246         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 247         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 248         u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
 249
 250         /*
 251          * Do not do anything specific for now, suspend/resume callbacks will
 252          * configure the interrupt mask appropriately
 253          */
 254         if (enable)
 255                 bank->wake_active |= mask;
 256         else
 257                 bank->wake_active &= ~mask;
 258
 259         return brcmstb_gpio_priv_set_wake(priv, enable);
 260 }
 261
 262 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
 263 {
 264         struct brcmstb_gpio_priv *priv = data;
 265
 266         if (!priv || irq != priv->parent_wake_irq)
 267                 return IRQ_NONE;
 268
 269         /* Nothing to do */
 270         return IRQ_HANDLED;
 271 }
 272
 273 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
 274 {
 275         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 276         struct irq_domain *domain = priv->irq_domain;
 277         int hwbase = bank->gc.base - priv->gpio_base;
 278         unsigned long status;
 279
 280         while ((status = brcmstb_gpio_get_active_irqs(bank))) {
 281                 unsigned int irq, offset;
 282
 283                 for_each_set_bit(offset, &status, 32) {
 284                         if (offset >= bank->width)
 285                                 dev_warn(&priv->pdev->dev,
 286                                          "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
 287                                          bank->id, offset);
 288                         irq = irq_linear_revmap(domain, hwbase + offset);
 289                         generic_handle_irq(irq);
 290                 }
 291         }
 292 }
 293
 294 /* Each UPG GIO block has one IRQ for all banks */
 295 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
 296 {
 297         struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
 298         struct irq_chip *chip = irq_desc_get_chip(desc);
 299         struct brcmstb_gpio_bank *bank;
 300
 301         /* Interrupts weren't properly cleared during probe */
 302         BUG_ON(!priv || !chip);
 303
 304         chained_irq_enter(chip, desc);
 305         list_for_each_entry(bank, &priv->bank_list, node)
 306                 brcmstb_gpio_irq_bank_handler(bank);
 307         chained_irq_exit(chip, desc);
 308 }
 309
 310 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
 311                 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
 312 {
 313         struct brcmstb_gpio_bank *bank;
 314         int i = 0;
 315
 316         /* banks are in descending order */
 317         list_for_each_entry_reverse(bank, &priv->bank_list, node) {
 318                 i += bank->gc.ngpio;
 319                 if (hwirq < i)
 320                         return bank;
 321         }
 322         return NULL;
 323 }
 324
 325 /*
 326  * This lock class tells lockdep that GPIO irqs are in a different
 327  * category than their parents, so it won't report false recursion.
 328  */
 329 static struct lock_class_key brcmstb_gpio_irq_lock_class;
 330
 331
 332 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 333                 irq_hw_number_t hwirq)
 334 {
 335         struct brcmstb_gpio_priv *priv = d->host_data;
 336         struct brcmstb_gpio_bank *bank =
 337                 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
 338         struct platform_device *pdev = priv->pdev;
 339         int ret;
 340
 341         if (!bank)
 342                 return -EINVAL;
 343
 344         dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
 345                 irq, (int)hwirq, bank->id);
 346         ret = irq_set_chip_data(irq, &bank->gc);
 347         if (ret < 0)
 348                 return ret;
 349         irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class);
 350         irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
 351         irq_set_noprobe(irq);
 352         return 0;
 353 }
 354
 355 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
 356 {
 357         irq_set_chip_and_handler(irq, NULL, NULL);
 358         irq_set_chip_data(irq, NULL);
 359 }
 360
 361 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
 362         .map = brcmstb_gpio_irq_map,
 363         .unmap = brcmstb_gpio_irq_unmap,
 364         .xlate = irq_domain_xlate_twocell,
 365 };
 366
 367 /* Make sure that the number of banks matches up between properties */
 368 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
 369                 struct device_node *np, struct resource *res)
 370 {
 371         int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
 372         int num_banks =
 373                 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
 374
 375         if (res_num_banks != num_banks) {
 376                 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
 377                                 res_num_banks, num_banks);
 378                 return -EINVAL;
 379         } else {
 380                 return 0;
 381         }
 382 }
 383
 384 static int brcmstb_gpio_remove(struct platform_device *pdev)
 385 {
 386         struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
 387         struct brcmstb_gpio_bank *bank;
 388         int offset, ret = 0, virq;
 389
 390         if (!priv) {
 391                 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
 392                 return -EFAULT;
 393         }
 394
 395         if (priv->parent_irq > 0)
 396                 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
 397
 398         /* Remove all IRQ mappings and delete the domain */
 399         if (priv->irq_domain) {
 400                 for (offset = 0; offset < priv->num_gpios; offset++) {
 401                         virq = irq_find_mapping(priv->irq_domain, offset);
 402                         irq_dispose_mapping(virq);
 403                 }
 404                 irq_domain_remove(priv->irq_domain);
 405         }
 406
 407         /*
 408          * You can lose return values below, but we report all errors, and it's
 409          * more important to actually perform all of the steps.
 410          */
 411         list_for_each_entry(bank, &priv->bank_list, node)
 412                 gpiochip_remove(&bank->gc);
 413
 414         return ret;
 415 }
 416
 417 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
 418                 const struct of_phandle_args *gpiospec, u32 *flags)
 419 {
 420         struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
 421         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 422         int offset;
 423
 424         if (gc->of_gpio_n_cells != 2) {
 425                 WARN_ON(1);
 426                 return -EINVAL;
 427         }
 428
 429         if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
 430                 return -EINVAL;
 431
 432         offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
 433         if (offset >= gc->ngpio || offset < 0)
 434                 return -EINVAL;
 435
 436         if (unlikely(offset >= bank->width)) {
 437                 dev_warn_ratelimited(&priv->pdev->dev,
 438                         "Received request for invalid GPIO offset %d\n",
 439                         gpiospec->args[0]);
 440         }
 441
 442         if (flags)
 443                 *flags = gpiospec->args[1];
 444
 445         return offset;
 446 }
 447
 448 /* priv->parent_irq and priv->num_gpios must be set before calling */
 449 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
 450                 struct brcmstb_gpio_priv *priv)
 451 {
 452         struct device *dev = &pdev->dev;
 453         struct device_node *np = dev->of_node;
 454         int err;
 455
 456         priv->irq_domain =
 457                 irq_domain_add_linear(np, priv->num_gpios,
 458                                       &brcmstb_gpio_irq_domain_ops,
 459                                       priv);
 460         if (!priv->irq_domain) {
 461                 dev_err(dev, "Couldn't allocate IRQ domain\n");
 462                 return -ENXIO;
 463         }
 464
 465         if (of_property_read_bool(np, "wakeup-source")) {
 466                 priv->parent_wake_irq = platform_get_irq(pdev, 1);
 467                 if (priv->parent_wake_irq < 0) {
 468                         priv->parent_wake_irq = 0;
 469                         dev_warn(dev,
 470                                 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
 471                 } else {
 472                         /*
 473                          * Set wakeup capability so we can process boot-time
 474                          * "wakeups" (e.g., from S5 cold boot)
 475                          */
 476                         device_set_wakeup_capable(dev, true);
 477                         device_wakeup_enable(dev);
 478                         err = devm_request_irq(dev, priv->parent_wake_irq,
 479                                                brcmstb_gpio_wake_irq_handler,
 480                                                IRQF_SHARED,
 481                                                "brcmstb-gpio-wake", priv);
 482
 483                         if (err < 0) {
 484                                 dev_err(dev, "Couldn't request wake IRQ");
 485                                 goto out_free_domain;
 486                         }
 487                 }
 488         }
 489
 490         priv->irq_chip.name = dev_name(dev);
 491         priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
 492         priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
 493         priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
 494         priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
 495         priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
 496
 497         if (priv->parent_wake_irq)
 498                 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
 499
 500         irq_set_chained_handler_and_data(priv->parent_irq,
 501                                          brcmstb_gpio_irq_handler, priv);
 502         irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
 503
 504         return 0;
 505
 506 out_free_domain:
 507         irq_domain_remove(priv->irq_domain);
 508
 509         return err;
 510 }
 511
 512 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
 513                                    struct brcmstb_gpio_bank *bank)
 514 {
 515         struct gpio_chip *gc = &bank->gc;
 516         unsigned int i;
 517
 518         for (i = 0; i < GIO_REG_STAT; i++)
 519                 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
 520                                                    GIO_BANK_OFF(bank->id, i));
 521 }
 522
 523 static void brcmstb_gpio_quiesce(struct device *dev, bool save)
 524 {
 525         struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
 526         struct brcmstb_gpio_bank *bank;
 527         struct gpio_chip *gc;
 528         u32 imask;
 529
 530         /* disable non-wake interrupt */
 531         if (priv->parent_irq >= 0)
 532                 disable_irq(priv->parent_irq);
 533
 534         list_for_each_entry(bank, &priv->bank_list, node) {
 535                 gc = &bank->gc;
 536
 537                 if (save)
 538                         brcmstb_gpio_bank_save(priv, bank);
 539
 540                 /* Unmask GPIOs which have been flagged as wake-up sources */
 541                 if (priv->parent_wake_irq)
 542                         imask = bank->wake_active;
 543                 else
 544                         imask = 0;
 545                 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
 546                                imask);
 547         }
 548 }
 549
 550 static void brcmstb_gpio_shutdown(struct platform_device *pdev)
 551 {
 552         /* Enable GPIO for S5 cold boot */
 553         brcmstb_gpio_quiesce(&pdev->dev, false);
 554 }
 555
 556 #ifdef CONFIG_PM_SLEEP
 557 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
 558                                       struct brcmstb_gpio_bank *bank)
 559 {
 560         struct gpio_chip *gc = &bank->gc;
 561         unsigned int i;
 562
 563         for (i = 0; i < GIO_REG_STAT; i++)
 564                 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
 565                               bank->saved_regs[i]);
 566 }
 567
 568 static int brcmstb_gpio_suspend(struct device *dev)
 569 {
 570         brcmstb_gpio_quiesce(dev, true);
 571         return 0;
 572 }
 573
 574 static int brcmstb_gpio_resume(struct device *dev)
 575 {
 576         struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
 577         struct brcmstb_gpio_bank *bank;
 578         bool need_wakeup_event = false;
 579
 580         list_for_each_entry(bank, &priv->bank_list, node) {
 581                 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
 582                 brcmstb_gpio_bank_restore(priv, bank);
 583         }
 584
 585         if (priv->parent_wake_irq && need_wakeup_event)
 586                 pm_wakeup_event(dev, 0);
 587
 588         /* enable non-wake interrupt */
 589         if (priv->parent_irq >= 0)
 590                 enable_irq(priv->parent_irq);
 591
 592         return 0;
 593 }
 594
 595 #else
 596 #define brcmstb_gpio_suspend    NULL
 597 #define brcmstb_gpio_resume     NULL
 598 #endif /* CONFIG_PM_SLEEP */
 599
 600 static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
 601         .suspend_noirq  = brcmstb_gpio_suspend,
 602         .resume_noirq = brcmstb_gpio_resume,
 603 };
 604
 605 static int brcmstb_gpio_probe(struct platform_device *pdev)
 606 {
 607         struct device *dev = &pdev->dev;
 608         struct device_node *np = dev->of_node;
 609         void __iomem *reg_base;
 610         struct brcmstb_gpio_priv *priv;
 611         struct resource *res;
 612         struct property *prop;
 613         const __be32 *p;
 614         u32 bank_width;
 615         int num_banks = 0;
 616         int err;
 617         static int gpio_base;
 618         unsigned long flags = 0;
 619         bool need_wakeup_event = false;
 620
 621         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 622         if (!priv)
 623                 return -ENOMEM;
 624         platform_set_drvdata(pdev, priv);
 625         INIT_LIST_HEAD(&priv->bank_list);
 626
 627         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 628         reg_base = devm_ioremap_resource(dev, res);
 629         if (IS_ERR(reg_base))
 630                 return PTR_ERR(reg_base);
 631
 632         priv->gpio_base = gpio_base;
 633         priv->reg_base = reg_base;
 634         priv->pdev = pdev;
 635
 636         if (of_property_read_bool(np, "interrupt-controller")) {
 637                 priv->parent_irq = platform_get_irq(pdev, 0);
 638                 if (priv->parent_irq <= 0) {
 639                         dev_err(dev, "Couldn't get IRQ");
 640                         return -ENOENT;
 641                 }
 642         } else {
 643                 priv->parent_irq = -ENOENT;
 644         }
 645
 646         if (brcmstb_gpio_sanity_check_banks(dev, np, res))
 647                 return -EINVAL;
 648
 649         /*
 650          * MIPS endianness is configured by boot strap, which also reverses all
 651          * bus endianness (i.e., big-endian CPU + big endian bus ==> native
 652          * endian I/O).
 653          *
 654          * Other architectures (e.g., ARM) either do not support big endian, or
 655          * else leave I/O in little endian mode.
 656          */
 657 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
 658         flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
 659 #endif
 660
 661         of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
 662                         bank_width) {
 663                 struct brcmstb_gpio_bank *bank;
 664                 struct gpio_chip *gc;
 665
 666                 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
 667                 if (!bank) {
 668                         err = -ENOMEM;
 669                         goto fail;
 670                 }
 671
 672                 bank->parent_priv = priv;
 673                 bank->id = num_banks;
 674                 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
 675                         dev_err(dev, "Invalid bank width %d\n", bank_width);
 676                         err = -EINVAL;
 677                         goto fail;
 678                 } else {
 679                         bank->width = bank_width;
 680                 }
 681
 682                 /*
 683                  * Regs are 4 bytes wide, have data reg, no set/clear regs,
 684                  * and direction bits have 0 = output and 1 = input
 685                  */
 686                 gc = &bank->gc;
 687                 err = bgpio_init(gc, dev, 4,
 688                                 reg_base + GIO_DATA(bank->id),
 689                                 NULL, NULL, NULL,
 690                                 reg_base + GIO_IODIR(bank->id), flags);
 691                 if (err) {
 692                         dev_err(dev, "bgpio_init() failed\n");
 693                         goto fail;
 694                 }
 695
 696                 gc->of_node = np;
 697                 gc->owner = THIS_MODULE;
 698                 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
 699                 if (!gc->label) {
 700                         err = -ENOMEM;
 701                         goto fail;
 702                 }
 703                 gc->base = gpio_base;
 704                 gc->of_gpio_n_cells = 2;
 705                 gc->of_xlate = brcmstb_gpio_of_xlate;
 706                 /* not all ngpio lines are valid, will use bank width later */
 707                 gc->ngpio = MAX_GPIO_PER_BANK;
 708                 if (priv->parent_irq > 0)
 709                         gc->to_irq = brcmstb_gpio_to_irq;
 710
 711                 /*
 712                  * Mask all interrupts by default, since wakeup interrupts may
 713                  * be retained from S5 cold boot
 714                  */
 715                 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
 716                 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
 717
 718                 err = gpiochip_add_data(gc, bank);
 719                 if (err) {
 720                         dev_err(dev, "Could not add gpiochip for bank %d\n",
 721                                         bank->id);
 722                         goto fail;
 723                 }
 724                 gpio_base += gc->ngpio;
 725
 726                 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
 727                         gc->base, gc->ngpio, bank->width);
 728
 729                 /* Everything looks good, so add bank to list */
 730                 list_add(&bank->node, &priv->bank_list);
 731
 732                 num_banks++;
 733         }
 734
 735         priv->num_gpios = gpio_base - priv->gpio_base;
 736         if (priv->parent_irq > 0) {
 737                 err = brcmstb_gpio_irq_setup(pdev, priv);
 738                 if (err)
 739                         goto fail;
 740         }
 741
 742         dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
 743                         num_banks, priv->gpio_base, gpio_base - 1);
 744
 745         if (priv->parent_wake_irq && need_wakeup_event)
 746                 pm_wakeup_event(dev, 0);
 747
 748         return 0;
 749
 750 fail:
 751         (void) brcmstb_gpio_remove(pdev);
 752         return err;
 753 }
 754
 755 static const struct of_device_id brcmstb_gpio_of_match[] = {
 756         { .compatible = "brcm,brcmstb-gpio" },
 757         {},
 758 };
 759
 760 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
 761
 762 static struct platform_driver brcmstb_gpio_driver = {
 763         .driver = {
 764                 .name = "brcmstb-gpio",
 765                 .of_match_table = brcmstb_gpio_of_match,
 766                 .pm = &brcmstb_gpio_pm_ops,
 767         },
 768         .probe = brcmstb_gpio_probe,
 769         .remove = brcmstb_gpio_remove,
 770         .shutdown = brcmstb_gpio_shutdown,
 771 };
 772 module_platform_driver(brcmstb_gpio_driver);
 773
 774 MODULE_AUTHOR("Gregory Fong");
 775 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
 776 MODULE_LICENSE("GPL v2");