drivers/gpio/gpio-davinci.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12 #include <linux/gpio.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/platform_data/gpio-davinci.h>
  25 #include <linux/irqchip/chained_irq.h>
  26
  27 struct davinci_gpio_regs {
  28         u32     dir;
  29         u32     out_data;
  30         u32     set_data;
  31         u32     clr_data;
  32         u32     in_data;
  33         u32     set_rising;
  34         u32     clr_rising;
  35         u32     set_falling;
  36         u32     clr_falling;
  37         u32     intstat;
  38 };
  39
  40 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
  41
  42 #define BINTEN  0x8 /* GPIO Interrupt Per-Bank Enable Register */
  43
  44 #define chip2controller(chip)   \
  45         container_of(chip, struct davinci_gpio_controller, chip)
  46
  47 static void __iomem *gpio_base;
  48
  49 static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
  50 {
  51         void __iomem *ptr;
  52
  53         if (gpio < 32 * 1)
  54                 ptr = gpio_base + 0x10;
  55         else if (gpio < 32 * 2)
  56                 ptr = gpio_base + 0x38;
  57         else if (gpio < 32 * 3)
  58                 ptr = gpio_base + 0x60;
  59         else if (gpio < 32 * 4)
  60                 ptr = gpio_base + 0x88;
  61         else if (gpio < 32 * 5)
  62                 ptr = gpio_base + 0xb0;
  63         else
  64                 ptr = NULL;
  65         return ptr;
  66 }
  67
  68 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
  69 {
  70         struct davinci_gpio_regs __iomem *g;
  71
  72         g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
  73
  74         return g;
  75 }
  76
  77 static int davinci_gpio_irq_setup(struct platform_device *pdev);
  78
  79 /*--------------------------------------------------------------------------*/
  80
  81 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
  82 static inline int __davinci_direction(struct gpio_chip *chip,
  83                         unsigned offset, bool out, int value)
  84 {
  85         struct davinci_gpio_controller *d = chip2controller(chip);
  86         struct davinci_gpio_regs __iomem *g = d->regs;
  87         unsigned long flags;
  88         u32 temp;
  89         u32 mask = 1 << offset;
  90
  91         spin_lock_irqsave(&d->lock, flags);
  92         temp = readl_relaxed(&g->dir);
  93         if (out) {
  94                 temp &= ~mask;
  95                 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
  96         } else {
  97                 temp |= mask;
  98         }
  99         writel_relaxed(temp, &g->dir);
 100         spin_unlock_irqrestore(&d->lock, flags);
 101
 102         return 0;
 103 }
 104
 105 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 106 {
 107         return __davinci_direction(chip, offset, false, 0);
 108 }
 109
 110 static int
 111 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 112 {
 113         return __davinci_direction(chip, offset, true, value);
 114 }
 115
 116 /*
 117  * Read the pin's value (works even if it's set up as output);
 118  * returns zero/nonzero.
 119  *
 120  * Note that changes are synched to the GPIO clock, so reading values back
 121  * right after you've set them may give old values.
 122  */
 123 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 124 {
 125         struct davinci_gpio_controller *d = chip2controller(chip);
 126         struct davinci_gpio_regs __iomem *g = d->regs;
 127
 128         return (1 << offset) & readl_relaxed(&g->in_data);
 129 }
 130
 131 /*
 132  * Assuming the pin is muxed as a gpio output, set its output value.
 133  */
 134 static void
 135 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 136 {
 137         struct davinci_gpio_controller *d = chip2controller(chip);
 138         struct davinci_gpio_regs __iomem *g = d->regs;
 139
 140         writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
 141 }
 142
 143 static struct davinci_gpio_platform_data *
 144 davinci_gpio_get_pdata(struct platform_device *pdev)
 145 {
 146         struct device_node *dn = pdev->dev.of_node;
 147         struct davinci_gpio_platform_data *pdata;
 148         int ret;
 149         u32 val;
 150
 151         if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
 152                 return pdev->dev.platform_data;
 153
 154         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 155         if (!pdata)
 156                 return NULL;
 157
 158         ret = of_property_read_u32(dn, "ti,ngpio", &val);
 159         if (ret)
 160                 goto of_err;
 161
 162         pdata->ngpio = val;
 163
 164         ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
 165         if (ret)
 166                 goto of_err;
 167
 168         pdata->gpio_unbanked = val;
 169
 170         return pdata;
 171
 172 of_err:
 173         dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
 174         return NULL;
 175 }
 176
 177 #ifdef CONFIG_OF_GPIO
 178 static int davinci_gpio_of_xlate(struct gpio_chip *gc,
 179                              const struct of_phandle_args *gpiospec,
 180                              u32 *flags)
 181 {
 182         struct davinci_gpio_controller *chips = dev_get_drvdata(gc->dev);
 183         struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->dev);
 184
 185         if (gpiospec->args[0] > pdata->ngpio)
 186                 return -EINVAL;
 187
 188         if (gc != &chips[gpiospec->args[0] / 32].chip)
 189                 return -EINVAL;
 190
 191         if (flags)
 192                 *flags = gpiospec->args[1];
 193
 194         return gpiospec->args[0] % 32;
 195 }
 196 #endif
 197
 198 static int davinci_gpio_probe(struct platform_device *pdev)
 199 {
 200         int i, base;
 201         unsigned ngpio;
 202         struct davinci_gpio_controller *chips;
 203         struct davinci_gpio_platform_data *pdata;
 204         struct davinci_gpio_regs __iomem *regs;
 205         struct device *dev = &pdev->dev;
 206         struct resource *res;
 207
 208         pdata = davinci_gpio_get_pdata(pdev);
 209         if (!pdata) {
 210                 dev_err(dev, "No platform data found\n");
 211                 return -EINVAL;
 212         }
 213
 214         dev->platform_data = pdata;
 215
 216         /*
 217          * The gpio banks conceptually expose a segmented bitmap,
 218          * and "ngpio" is one more than the largest zero-based
 219          * bit index that's valid.
 220          */
 221         ngpio = pdata->ngpio;
 222         if (ngpio == 0) {
 223                 dev_err(dev, "How many GPIOs?\n");
 224                 return -EINVAL;
 225         }
 226
 227         if (WARN_ON(ARCH_NR_GPIOS < ngpio))
 228                 ngpio = ARCH_NR_GPIOS;
 229
 230         chips = devm_kzalloc(dev,
 231                              ngpio * sizeof(struct davinci_gpio_controller),
 232                              GFP_KERNEL);
 233         if (!chips)
 234                 return -ENOMEM;
 235
 236         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 237         gpio_base = devm_ioremap_resource(dev, res);
 238         if (IS_ERR(gpio_base))
 239                 return PTR_ERR(gpio_base);
 240
 241         for (i = 0, base = 0; base < ngpio; i++, base += 32) {
 242                 chips[i].chip.label = "DaVinci";
 243
 244                 chips[i].chip.direction_input = davinci_direction_in;
 245                 chips[i].chip.get = davinci_gpio_get;
 246                 chips[i].chip.direction_output = davinci_direction_out;
 247                 chips[i].chip.set = davinci_gpio_set;
 248
 249                 chips[i].chip.base = base;
 250                 chips[i].chip.ngpio = ngpio - base;
 251                 if (chips[i].chip.ngpio > 32)
 252                         chips[i].chip.ngpio = 32;
 253
 254 #ifdef CONFIG_OF_GPIO
 255                 chips[i].chip.of_gpio_n_cells = 2;
 256                 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
 257                 chips[i].chip.dev = dev;
 258                 chips[i].chip.of_node = dev->of_node;
 259 #endif
 260                 spin_lock_init(&chips[i].lock);
 261
 262                 regs = gpio2regs(base);
 263                 chips[i].regs = regs;
 264                 chips[i].set_data = &regs->set_data;
 265                 chips[i].clr_data = &regs->clr_data;
 266                 chips[i].in_data = &regs->in_data;
 267
 268                 gpiochip_add(&chips[i].chip);
 269         }
 270
 271         platform_set_drvdata(pdev, chips);
 272         davinci_gpio_irq_setup(pdev);
 273         return 0;
 274 }
 275
 276 /*--------------------------------------------------------------------------*/
 277 /*
 278  * We expect irqs will normally be set up as input pins, but they can also be
 279  * used as output pins ... which is convenient for testing.
 280  *
 281  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 282  * to their GPIOBNK0 irq, with a bit less overhead.
 283  *
 284  * All those INTC hookups (direct, plus several IRQ banks) can also
 285  * serve as EDMA event triggers.
 286  */
 287
 288 static void gpio_irq_disable(struct irq_data *d)
 289 {
 290         struct davinci_gpio_regs __iomem *g = irq2regs(d);
 291         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 292
 293         writel_relaxed(mask, &g->clr_falling);
 294         writel_relaxed(mask, &g->clr_rising);
 295 }
 296
 297 static void gpio_irq_enable(struct irq_data *d)
 298 {
 299         struct davinci_gpio_regs __iomem *g = irq2regs(d);
 300         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 301         unsigned status = irqd_get_trigger_type(d);
 302
 303         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 304         if (!status)
 305                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 306
 307         if (status & IRQ_TYPE_EDGE_FALLING)
 308                 writel_relaxed(mask, &g->set_falling);
 309         if (status & IRQ_TYPE_EDGE_RISING)
 310                 writel_relaxed(mask, &g->set_rising);
 311 }
 312
 313 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
 314 {
 315         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 316                 return -EINVAL;
 317
 318         return 0;
 319 }
 320
 321 static struct irq_chip gpio_irqchip = {
 322         .name           = "GPIO",
 323         .irq_enable     = gpio_irq_enable,
 324         .irq_disable    = gpio_irq_disable,
 325         .irq_set_type   = gpio_irq_type,
 326         .flags          = IRQCHIP_SET_TYPE_MASKED,
 327 };
 328
 329 static void gpio_irq_handler(struct irq_desc *desc)
 330 {
 331         unsigned int irq = irq_desc_get_irq(desc);
 332         struct davinci_gpio_regs __iomem *g;
 333         u32 mask = 0xffff;
 334         struct davinci_gpio_controller *d;
 335
 336         d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
 337         g = (struct davinci_gpio_regs __iomem *)d->regs;
 338
 339         /* we only care about one bank */
 340         if (irq & 1)
 341                 mask <<= 16;
 342
 343         /* temporarily mask (level sensitive) parent IRQ */
 344         chained_irq_enter(irq_desc_get_chip(desc), desc);
 345         while (1) {
 346                 u32             status;
 347                 int             bit;
 348
 349                 /* ack any irqs */
 350                 status = readl_relaxed(&g->intstat) & mask;
 351                 if (!status)
 352                         break;
 353                 writel_relaxed(status, &g->intstat);
 354
 355                 /* now demux them to the right lowlevel handler */
 356
 357                 while (status) {
 358                         bit = __ffs(status);
 359                         status &= ~BIT(bit);
 360                         generic_handle_irq(
 361                                 irq_find_mapping(d->irq_domain,
 362                                                  d->chip.base + bit));
 363                 }
 364         }
 365         chained_irq_exit(irq_desc_get_chip(desc), desc);
 366         /* now it may re-trigger */
 367 }
 368
 369 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 370 {
 371         struct davinci_gpio_controller *d = chip2controller(chip);
 372
 373         if (d->irq_domain)
 374                 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
 375         else
 376                 return -ENXIO;
 377 }
 378
 379 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 380 {
 381         struct davinci_gpio_controller *d = chip2controller(chip);
 382
 383         /*
 384          * NOTE:  we assume for now that only irqs in the first gpio_chip
 385          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 386          */
 387         if (offset < d->gpio_unbanked)
 388                 return d->gpio_irq + offset;
 389         else
 390                 return -ENODEV;
 391 }
 392
 393 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
 394 {
 395         struct davinci_gpio_controller *d;
 396         struct davinci_gpio_regs __iomem *g;
 397         u32 mask;
 398
 399         d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
 400         g = (struct davinci_gpio_regs __iomem *)d->regs;
 401         mask = __gpio_mask(data->irq - d->gpio_irq);
 402
 403         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 404                 return -EINVAL;
 405
 406         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 407                      ? &g->set_falling : &g->clr_falling);
 408         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 409                      ? &g->set_rising : &g->clr_rising);
 410
 411         return 0;
 412 }
 413
 414 static int
 415 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 416                      irq_hw_number_t hw)
 417 {
 418         struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
 419
 420         irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
 421                                 "davinci_gpio");
 422         irq_set_irq_type(irq, IRQ_TYPE_NONE);
 423         irq_set_chip_data(irq, (__force void *)g);
 424         irq_set_handler_data(irq, (void *)__gpio_mask(hw));
 425
 426         return 0;
 427 }
 428
 429 static const struct irq_domain_ops davinci_gpio_irq_ops = {
 430         .map = davinci_gpio_irq_map,
 431         .xlate = irq_domain_xlate_onetwocell,
 432 };
 433
 434 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
 435 {
 436         static struct irq_chip_type gpio_unbanked;
 437
 438         gpio_unbanked = *container_of(irq_get_chip(irq),
 439                                       struct irq_chip_type, chip);
 440
 441         return &gpio_unbanked.chip;
 442 };
 443
 444 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
 445 {
 446         static struct irq_chip gpio_unbanked;
 447
 448         gpio_unbanked = *irq_get_chip(irq);
 449         return &gpio_unbanked;
 450 };
 451
 452 static const struct of_device_id davinci_gpio_ids[];
 453
 454 /*
 455  * NOTE:  for suspend/resume, probably best to make a platform_device with
 456  * suspend_late/resume_resume calls hooking into results of the set_wake()
 457  * calls ... so if no gpios are wakeup events the clock can be disabled,
 458  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 459  * (dm6446) can be set appropriately for GPIOV33 pins.
 460  */
 461
 462 static int davinci_gpio_irq_setup(struct platform_device *pdev)
 463 {
 464         unsigned        gpio, bank;
 465         int             irq;
 466         struct clk      *clk;
 467         u32             binten = 0;
 468         unsigned        ngpio, bank_irq;
 469         struct device *dev = &pdev->dev;
 470         struct resource *res;
 471         struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
 472         struct davinci_gpio_platform_data *pdata = dev->platform_data;
 473         struct davinci_gpio_regs __iomem *g;
 474         struct irq_domain       *irq_domain = NULL;
 475         const struct of_device_id *match;
 476         struct irq_chip *irq_chip;
 477         gpio_get_irq_chip_cb_t gpio_get_irq_chip;
 478
 479         /*
 480          * Use davinci_gpio_get_irq_chip by default to handle non DT cases
 481          */
 482         gpio_get_irq_chip = davinci_gpio_get_irq_chip;
 483         match = of_match_device(of_match_ptr(davinci_gpio_ids),
 484                                 dev);
 485         if (match)
 486                 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
 487
 488         ngpio = pdata->ngpio;
 489         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 490         if (!res) {
 491                 dev_err(dev, "Invalid IRQ resource\n");
 492                 return -EBUSY;
 493         }
 494
 495         bank_irq = res->start;
 496
 497         if (!bank_irq) {
 498                 dev_err(dev, "Invalid IRQ resource\n");
 499                 return -ENODEV;
 500         }
 501
 502         clk = devm_clk_get(dev, "gpio");
 503         if (IS_ERR(clk)) {
 504                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
 505                        PTR_ERR(clk));
 506                 return PTR_ERR(clk);
 507         }
 508         clk_prepare_enable(clk);
 509
 510         if (!pdata->gpio_unbanked) {
 511                 irq = irq_alloc_descs(-1, 0, ngpio, 0);
 512                 if (irq < 0) {
 513                         dev_err(dev, "Couldn't allocate IRQ numbers\n");
 514                         return irq;
 515                 }
 516
 517                 irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
 518                                                         &davinci_gpio_irq_ops,
 519                                                         chips);
 520                 if (!irq_domain) {
 521                         dev_err(dev, "Couldn't register an IRQ domain\n");
 522                         return -ENODEV;
 523                 }
 524         }
 525
 526         /*
 527          * Arrange gpio_to_irq() support, handling either direct IRQs or
 528          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
 529          * IRQs, while the others use banked IRQs, would need some setup
 530          * tweaks to recognize hardware which can do that.
 531          */
 532         for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
 533                 chips[bank].chip.to_irq = gpio_to_irq_banked;
 534                 chips[bank].irq_domain = irq_domain;
 535         }
 536
 537         /*
 538          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
 539          * controller only handling trigger modes.  We currently assume no
 540          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
 541          */
 542         if (pdata->gpio_unbanked) {
 543                 /* pass "bank 0" GPIO IRQs to AINTC */
 544                 chips[0].chip.to_irq = gpio_to_irq_unbanked;
 545                 chips[0].gpio_irq = bank_irq;
 546                 chips[0].gpio_unbanked = pdata->gpio_unbanked;
 547                 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
 548
 549                 /* AINTC handles mask/unmask; GPIO handles triggering */
 550                 irq = bank_irq;
 551                 irq_chip = gpio_get_irq_chip(irq);
 552                 irq_chip->name = "GPIO-AINTC";
 553                 irq_chip->irq_set_type = gpio_irq_type_unbanked;
 554
 555                 /* default trigger: both edges */
 556                 g = gpio2regs(0);
 557                 writel_relaxed(~0, &g->set_falling);
 558                 writel_relaxed(~0, &g->set_rising);
 559
 560                 /* set the direct IRQs up to use that irqchip */
 561                 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
 562                         irq_set_chip(irq, irq_chip);
 563                         irq_set_handler_data(irq, &chips[gpio / 32]);
 564                         irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
 565                 }
 566
 567                 goto done;
 568         }
 569
 570         /*
 571          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
 572          * then chain through our own handler.
 573          */
 574         for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
 575                 /* disabled by default, enabled only as needed */
 576                 g = gpio2regs(gpio);
 577                 writel_relaxed(~0, &g->clr_falling);
 578                 writel_relaxed(~0, &g->clr_rising);
 579
 580                 /*
 581                  * Each chip handles 32 gpios, and each irq bank consists of 16
 582                  * gpio irqs. Pass the irq bank's corresponding controller to
 583                  * the chained irq handler.
 584                  */
 585                 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
 586                                                  &chips[gpio / 32]);
 587
 588                 binten |= BIT(bank);
 589         }
 590
 591 done:
 592         /*
 593          * BINTEN -- per-bank interrupt enable. genirq would also let these
 594          * bits be set/cleared dynamically.
 595          */
 596         writel_relaxed(binten, gpio_base + BINTEN);
 597
 598         return 0;
 599 }
 600
 601 #if IS_ENABLED(CONFIG_OF)
 602 static const struct of_device_id davinci_gpio_ids[] = {
 603         { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
 604         { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
 605         { /* sentinel */ },
 606 };
 607 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
 608 #endif
 609
 610 static struct platform_driver davinci_gpio_driver = {
 611         .probe          = davinci_gpio_probe,
 612         .driver         = {
 613                 .name           = "davinci_gpio",
 614                 .of_match_table = of_match_ptr(davinci_gpio_ids),
 615         },
 616 };
 617
 618 /**
 619  * GPIO driver registration needs to be done before machine_init functions
 620  * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
 621  */
 622 static int __init davinci_gpio_drv_reg(void)
 623 {
 624         return platform_driver_register(&davinci_gpio_driver);
 625 }
 626 postcore_initcall(davinci_gpio_drv_reg);