drivers/gpio/gpio-davinci.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12 #include <linux/gpio.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/platform_data/gpio-davinci.h>
  25 #include <linux/irqchip/chained_irq.h>
  26
  27 struct davinci_gpio_regs {
  28         u32     dir;
  29         u32     out_data;
  30         u32     set_data;
  31         u32     clr_data;
  32         u32     in_data;
  33         u32     set_rising;
  34         u32     clr_rising;
  35         u32     set_falling;
  36         u32     clr_falling;
  37         u32     intstat;
  38 };
  39
  40 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
  41
  42 #define BINTEN  0x8 /* GPIO Interrupt Per-Bank Enable Register */
  43 #define MAX_LABEL_SIZE 20
  44
  45 static void __iomem *gpio_base;
  46 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
  47
  48 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
  49 {
  50         struct davinci_gpio_regs __iomem *g;
  51
  52         g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
  53
  54         return g;
  55 }
  56
  57 static int davinci_gpio_irq_setup(struct platform_device *pdev);
  58
  59 /*--------------------------------------------------------------------------*/
  60
  61 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
  62 static inline int __davinci_direction(struct gpio_chip *chip,
  63                         unsigned offset, bool out, int value)
  64 {
  65         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
  66         struct davinci_gpio_regs __iomem *g;
  67         unsigned long flags;
  68         u32 temp;
  69         int bank = offset / 32;
  70         u32 mask = __gpio_mask(offset);
  71
  72         g = d->regs[bank];
  73         spin_lock_irqsave(&d->lock, flags);
  74         temp = readl_relaxed(&g->dir);
  75         if (out) {
  76                 temp &= ~mask;
  77                 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
  78         } else {
  79                 temp |= mask;
  80         }
  81         writel_relaxed(temp, &g->dir);
  82         spin_unlock_irqrestore(&d->lock, flags);
  83
  84         return 0;
  85 }
  86
  87 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  88 {
  89         return __davinci_direction(chip, offset, false, 0);
  90 }
  91
  92 static int
  93 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  94 {
  95         return __davinci_direction(chip, offset, true, value);
  96 }
  97
  98 /*
  99  * Read the pin's value (works even if it's set up as output);
 100  * returns zero/nonzero.
 101  *
 102  * Note that changes are synched to the GPIO clock, so reading values back
 103  * right after you've set them may give old values.
 104  */
 105 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 106 {
 107         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 108         struct davinci_gpio_regs __iomem *g;
 109         int bank = offset / 32;
 110
 111         g = d->regs[bank];
 112
 113         return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
 114 }
 115
 116 /*
 117  * Assuming the pin is muxed as a gpio output, set its output value.
 118  */
 119 static void
 120 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 121 {
 122         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 123         struct davinci_gpio_regs __iomem *g;
 124         int bank = offset / 32;
 125
 126         g = d->regs[bank];
 127
 128         writel_relaxed(__gpio_mask(offset),
 129                        value ? &g->set_data : &g->clr_data);
 130 }
 131
 132 static struct davinci_gpio_platform_data *
 133 davinci_gpio_get_pdata(struct platform_device *pdev)
 134 {
 135         struct device_node *dn = pdev->dev.of_node;
 136         struct davinci_gpio_platform_data *pdata;
 137         int ret;
 138         u32 val;
 139
 140         if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
 141                 return dev_get_platdata(&pdev->dev);
 142
 143         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 144         if (!pdata)
 145                 return NULL;
 146
 147         ret = of_property_read_u32(dn, "ti,ngpio", &val);
 148         if (ret)
 149                 goto of_err;
 150
 151         pdata->ngpio = val;
 152
 153         ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
 154         if (ret)
 155                 goto of_err;
 156
 157         pdata->gpio_unbanked = val;
 158
 159         return pdata;
 160
 161 of_err:
 162         dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
 163         return NULL;
 164 }
 165
 166 static int davinci_gpio_probe(struct platform_device *pdev)
 167 {
 168         static int ctrl_num, bank_base;
 169         int gpio, bank;
 170         unsigned ngpio, nbank;
 171         struct davinci_gpio_controller *chips;
 172         struct davinci_gpio_platform_data *pdata;
 173         struct device *dev = &pdev->dev;
 174         struct resource *res;
 175         char label[MAX_LABEL_SIZE];
 176
 177         pdata = davinci_gpio_get_pdata(pdev);
 178         if (!pdata) {
 179                 dev_err(dev, "No platform data found\n");
 180                 return -EINVAL;
 181         }
 182
 183         dev->platform_data = pdata;
 184
 185         /*
 186          * The gpio banks conceptually expose a segmented bitmap,
 187          * and "ngpio" is one more than the largest zero-based
 188          * bit index that's valid.
 189          */
 190         ngpio = pdata->ngpio;
 191         if (ngpio == 0) {
 192                 dev_err(dev, "How many GPIOs?\n");
 193                 return -EINVAL;
 194         }
 195
 196         if (WARN_ON(ARCH_NR_GPIOS < ngpio))
 197                 ngpio = ARCH_NR_GPIOS;
 198
 199         nbank = DIV_ROUND_UP(ngpio, 32);
 200         chips = devm_kzalloc(dev,
 201                              nbank * sizeof(struct davinci_gpio_controller),
 202                              GFP_KERNEL);
 203         if (!chips)
 204                 return -ENOMEM;
 205
 206         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 207         gpio_base = devm_ioremap_resource(dev, res);
 208         if (IS_ERR(gpio_base))
 209                 return PTR_ERR(gpio_base);
 210
 211         snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++);
 212         chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL);
 213                 if (!chips->chip.label)
 214                         return -ENOMEM;
 215
 216         chips->chip.direction_input = davinci_direction_in;
 217         chips->chip.get = davinci_gpio_get;
 218         chips->chip.direction_output = davinci_direction_out;
 219         chips->chip.set = davinci_gpio_set;
 220
 221         chips->chip.ngpio = ngpio;
 222         chips->chip.base = bank_base;
 223
 224 #ifdef CONFIG_OF_GPIO
 225         chips->chip.of_gpio_n_cells = 2;
 226         chips->chip.parent = dev;
 227         chips->chip.of_node = dev->of_node;
 228 #endif
 229         spin_lock_init(&chips->lock);
 230         bank_base += ngpio;
 231
 232         for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++)
 233                 chips->regs[bank] = gpio_base + offset_array[bank];
 234
 235         gpiochip_add_data(&chips->chip, chips);
 236         platform_set_drvdata(pdev, chips);
 237         davinci_gpio_irq_setup(pdev);
 238         return 0;
 239 }
 240
 241 /*--------------------------------------------------------------------------*/
 242 /*
 243  * We expect irqs will normally be set up as input pins, but they can also be
 244  * used as output pins ... which is convenient for testing.
 245  *
 246  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 247  * to their GPIOBNK0 irq, with a bit less overhead.
 248  *
 249  * All those INTC hookups (direct, plus several IRQ banks) can also
 250  * serve as EDMA event triggers.
 251  */
 252
 253 static void gpio_irq_disable(struct irq_data *d)
 254 {
 255         struct davinci_gpio_regs __iomem *g = irq2regs(d);
 256         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 257
 258         writel_relaxed(mask, &g->clr_falling);
 259         writel_relaxed(mask, &g->clr_rising);
 260 }
 261
 262 static void gpio_irq_enable(struct irq_data *d)
 263 {
 264         struct davinci_gpio_regs __iomem *g = irq2regs(d);
 265         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 266         unsigned status = irqd_get_trigger_type(d);
 267
 268         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 269         if (!status)
 270                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 271
 272         if (status & IRQ_TYPE_EDGE_FALLING)
 273                 writel_relaxed(mask, &g->set_falling);
 274         if (status & IRQ_TYPE_EDGE_RISING)
 275                 writel_relaxed(mask, &g->set_rising);
 276 }
 277
 278 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
 279 {
 280         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 281                 return -EINVAL;
 282
 283         return 0;
 284 }
 285
 286 static struct irq_chip gpio_irqchip = {
 287         .name           = "GPIO",
 288         .irq_enable     = gpio_irq_enable,
 289         .irq_disable    = gpio_irq_disable,
 290         .irq_set_type   = gpio_irq_type,
 291         .flags          = IRQCHIP_SET_TYPE_MASKED,
 292 };
 293
 294 static void gpio_irq_handler(struct irq_desc *desc)
 295 {
 296         struct davinci_gpio_regs __iomem *g;
 297         u32 mask = 0xffff;
 298         int bank_num;
 299         struct davinci_gpio_controller *d;
 300         struct davinci_gpio_irq_data *irqdata;
 301
 302         irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
 303         bank_num = irqdata->bank_num;
 304         g = irqdata->regs;
 305         d = irqdata->chip;
 306
 307         /* we only care about one bank */
 308         if ((bank_num % 2) == 1)
 309                 mask <<= 16;
 310
 311         /* temporarily mask (level sensitive) parent IRQ */
 312         chained_irq_enter(irq_desc_get_chip(desc), desc);
 313         while (1) {
 314                 u32             status;
 315                 int             bit;
 316                 irq_hw_number_t hw_irq;
 317
 318                 /* ack any irqs */
 319                 status = readl_relaxed(&g->intstat) & mask;
 320                 if (!status)
 321                         break;
 322                 writel_relaxed(status, &g->intstat);
 323
 324                 /* now demux them to the right lowlevel handler */
 325
 326                 while (status) {
 327                         bit = __ffs(status);
 328                         status &= ~BIT(bit);
 329                         /* Max number of gpios per controller is 144 so
 330                          * hw_irq will be in [0..143]
 331                          */
 332                         hw_irq = (bank_num / 2) * 32 + bit;
 333
 334                         generic_handle_irq(
 335                                 irq_find_mapping(d->irq_domain, hw_irq));
 336                 }
 337         }
 338         chained_irq_exit(irq_desc_get_chip(desc), desc);
 339         /* now it may re-trigger */
 340 }
 341
 342 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 343 {
 344         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 345
 346         if (d->irq_domain)
 347                 return irq_create_mapping(d->irq_domain, offset);
 348         else
 349                 return -ENXIO;
 350 }
 351
 352 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 353 {
 354         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 355
 356         /*
 357          * NOTE:  we assume for now that only irqs in the first gpio_chip
 358          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 359          */
 360         if (offset < d->gpio_unbanked)
 361                 return d->base_irq + offset;
 362         else
 363                 return -ENODEV;
 364 }
 365
 366 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
 367 {
 368         struct davinci_gpio_controller *d;
 369         struct davinci_gpio_regs __iomem *g;
 370         u32 mask;
 371
 372         d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
 373         g = (struct davinci_gpio_regs __iomem *)d->regs;
 374         mask = __gpio_mask(data->irq - d->base_irq);
 375
 376         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 377                 return -EINVAL;
 378
 379         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 380                      ? &g->set_falling : &g->clr_falling);
 381         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 382                      ? &g->set_rising : &g->clr_rising);
 383
 384         return 0;
 385 }
 386
 387 static int
 388 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 389                      irq_hw_number_t hw)
 390 {
 391         struct davinci_gpio_controller *chips =
 392                                 (struct davinci_gpio_controller *)d->host_data;
 393         struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
 394
 395         irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
 396                                 "davinci_gpio");
 397         irq_set_irq_type(irq, IRQ_TYPE_NONE);
 398         irq_set_chip_data(irq, (__force void *)g);
 399         irq_set_handler_data(irq, (void *)__gpio_mask(hw));
 400
 401         return 0;
 402 }
 403
 404 static const struct irq_domain_ops davinci_gpio_irq_ops = {
 405         .map = davinci_gpio_irq_map,
 406         .xlate = irq_domain_xlate_onetwocell,
 407 };
 408
 409 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
 410 {
 411         static struct irq_chip_type gpio_unbanked;
 412
 413         gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
 414
 415         return &gpio_unbanked.chip;
 416 };
 417
 418 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
 419 {
 420         static struct irq_chip gpio_unbanked;
 421
 422         gpio_unbanked = *irq_get_chip(irq);
 423         return &gpio_unbanked;
 424 };
 425
 426 static const struct of_device_id davinci_gpio_ids[];
 427
 428 /*
 429  * NOTE:  for suspend/resume, probably best to make a platform_device with
 430  * suspend_late/resume_resume calls hooking into results of the set_wake()
 431  * calls ... so if no gpios are wakeup events the clock can be disabled,
 432  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 433  * (dm6446) can be set appropriately for GPIOV33 pins.
 434  */
 435
 436 static int davinci_gpio_irq_setup(struct platform_device *pdev)
 437 {
 438         unsigned        gpio, bank;
 439         int             irq;
 440         int             ret;
 441         struct clk      *clk;
 442         u32             binten = 0;
 443         unsigned        ngpio, bank_irq;
 444         struct device *dev = &pdev->dev;
 445         struct resource *res;
 446         struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
 447         struct davinci_gpio_platform_data *pdata = dev->platform_data;
 448         struct davinci_gpio_regs __iomem *g;
 449         struct irq_domain       *irq_domain = NULL;
 450         const struct of_device_id *match;
 451         struct irq_chip *irq_chip;
 452         struct davinci_gpio_irq_data *irqdata;
 453         gpio_get_irq_chip_cb_t gpio_get_irq_chip;
 454
 455         /*
 456          * Use davinci_gpio_get_irq_chip by default to handle non DT cases
 457          */
 458         gpio_get_irq_chip = davinci_gpio_get_irq_chip;
 459         match = of_match_device(of_match_ptr(davinci_gpio_ids),
 460                                 dev);
 461         if (match)
 462                 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
 463
 464         ngpio = pdata->ngpio;
 465         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 466         if (!res) {
 467                 dev_err(dev, "Invalid IRQ resource\n");
 468                 return -EBUSY;
 469         }
 470
 471         bank_irq = res->start;
 472
 473         if (!bank_irq) {
 474                 dev_err(dev, "Invalid IRQ resource\n");
 475                 return -ENODEV;
 476         }
 477
 478         clk = devm_clk_get(dev, "gpio");
 479         if (IS_ERR(clk)) {
 480                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
 481                        PTR_ERR(clk));
 482                 return PTR_ERR(clk);
 483         }
 484         ret = clk_prepare_enable(clk);
 485         if (ret)
 486                 return ret;
 487
 488         if (!pdata->gpio_unbanked) {
 489                 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
 490                 if (irq < 0) {
 491                         dev_err(dev, "Couldn't allocate IRQ numbers\n");
 492                         clk_disable_unprepare(clk);
 493                         return irq;
 494                 }
 495
 496                 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
 497                                                         &davinci_gpio_irq_ops,
 498                                                         chips);
 499                 if (!irq_domain) {
 500                         dev_err(dev, "Couldn't register an IRQ domain\n");
 501                         clk_disable_unprepare(clk);
 502                         return -ENODEV;
 503                 }
 504         }
 505
 506         /*
 507          * Arrange gpio_to_irq() support, handling either direct IRQs or
 508          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
 509          * IRQs, while the others use banked IRQs, would need some setup
 510          * tweaks to recognize hardware which can do that.
 511          */
 512         chips->chip.to_irq = gpio_to_irq_banked;
 513         chips->irq_domain = irq_domain;
 514
 515         /*
 516          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
 517          * controller only handling trigger modes.  We currently assume no
 518          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
 519          */
 520         if (pdata->gpio_unbanked) {
 521                 /* pass "bank 0" GPIO IRQs to AINTC */
 522                 chips->chip.to_irq = gpio_to_irq_unbanked;
 523                 chips->base_irq = bank_irq;
 524                 chips->gpio_unbanked = pdata->gpio_unbanked;
 525                 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
 526
 527                 /* AINTC handles mask/unmask; GPIO handles triggering */
 528                 irq = bank_irq;
 529                 irq_chip = gpio_get_irq_chip(irq);
 530                 irq_chip->name = "GPIO-AINTC";
 531                 irq_chip->irq_set_type = gpio_irq_type_unbanked;
 532
 533                 /* default trigger: both edges */
 534                 g = chips->regs[0];
 535                 writel_relaxed(~0, &g->set_falling);
 536                 writel_relaxed(~0, &g->set_rising);
 537
 538                 /* set the direct IRQs up to use that irqchip */
 539                 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
 540                         irq_set_chip(irq, irq_chip);
 541                         irq_set_handler_data(irq, chips);
 542                         irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
 543                 }
 544
 545                 goto done;
 546         }
 547
 548         /*
 549          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
 550          * then chain through our own handler.
 551          */
 552         for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
 553                 /* disabled by default, enabled only as needed
 554                  * There are register sets for 32 GPIOs. 2 banks of 16
 555                  * GPIOs are covered by each set of registers hence divide by 2
 556                  */
 557                 g = chips->regs[bank / 2];
 558                 writel_relaxed(~0, &g->clr_falling);
 559                 writel_relaxed(~0, &g->clr_rising);
 560
 561                 /*
 562                  * Each chip handles 32 gpios, and each irq bank consists of 16
 563                  * gpio irqs. Pass the irq bank's corresponding controller to
 564                  * the chained irq handler.
 565                  */
 566                 irqdata = devm_kzalloc(&pdev->dev,
 567                                        sizeof(struct
 568                                               davinci_gpio_irq_data),
 569                                               GFP_KERNEL);
 570                 if (!irqdata) {
 571                         clk_disable_unprepare(clk);
 572                         return -ENOMEM;
 573                 }
 574
 575                 irqdata->regs = g;
 576                 irqdata->bank_num = bank;
 577                 irqdata->chip = chips;
 578
 579                 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
 580                                                  irqdata);
 581
 582                 binten |= BIT(bank);
 583         }
 584
 585 done:
 586         /*
 587          * BINTEN -- per-bank interrupt enable. genirq would also let these
 588          * bits be set/cleared dynamically.
 589          */
 590         writel_relaxed(binten, gpio_base + BINTEN);
 591
 592         return 0;
 593 }
 594
 595 #if IS_ENABLED(CONFIG_OF)
 596 static const struct of_device_id davinci_gpio_ids[] = {
 597         { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
 598         { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
 599         { /* sentinel */ },
 600 };
 601 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
 602 #endif
 603
 604 static struct platform_driver davinci_gpio_driver = {
 605         .probe          = davinci_gpio_probe,
 606         .driver         = {
 607                 .name           = "davinci_gpio",
 608                 .of_match_table = of_match_ptr(davinci_gpio_ids),
 609         },
 610 };
 611
 612 /**
 613  * GPIO driver registration needs to be done before machine_init functions
 614  * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
 615  */
 616 static int __init davinci_gpio_drv_reg(void)
 617 {
 618         return platform_driver_register(&davinci_gpio_driver);
 619 }
 620 postcore_initcall(davinci_gpio_drv_reg);