drivers/gpio/gpio-davinci.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/gpio/driver.h>
  14 #include <linux/errno.h>
  15 #include <linux/kernel.h>
  16 #include <linux/clk.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/pinctrl/consumer.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/platform_data/gpio-davinci.h>
  27 #include <linux/irqchip/chained_irq.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <asm-generic/gpio.h>
  31
  32 #define MAX_REGS_BANKS 5
  33 #define MAX_INT_PER_BANK 32
  34
  35 struct davinci_gpio_regs {
  36         u32     dir;
  37         u32     out_data;
  38         u32     set_data;
  39         u32     clr_data;
  40         u32     in_data;
  41         u32     set_rising;
  42         u32     clr_rising;
  43         u32     set_falling;
  44         u32     clr_falling;
  45         u32     intstat;
  46 };
  47
  48 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
  49
  50 #define BINTEN  0x8 /* GPIO Interrupt Per-Bank Enable Register */
  51
  52 static void __iomem *gpio_base;
  53 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
  54
  55 struct davinci_gpio_irq_data {
  56         void __iomem                    *regs;
  57         struct davinci_gpio_controller  *chip;
  58         int                             bank_num;
  59 };
  60
  61 struct davinci_gpio_controller {
  62         struct gpio_chip        chip;
  63         struct irq_domain       *irq_domain;
  64         /* Serialize access to GPIO registers */
  65         spinlock_t              lock;
  66         void __iomem            *regs[MAX_REGS_BANKS];
  67         int                     gpio_unbanked;
  68         int                     irqs[MAX_INT_PER_BANK];
  69 };
  70
  71 static inline u32 __gpio_mask(unsigned gpio)
  72 {
  73         return 1 << (gpio % 32);
  74 }
  75
  76 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
  77 {
  78         struct davinci_gpio_regs __iomem *g;
  79
  80         g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
  81
  82         return g;
  83 }
  84
  85 static int davinci_gpio_irq_setup(struct platform_device *pdev);
  86
  87 /*--------------------------------------------------------------------------*/
  88
  89 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
  90 static inline int __davinci_direction(struct gpio_chip *chip,
  91                         unsigned offset, bool out, int value)
  92 {
  93         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
  94         struct davinci_gpio_regs __iomem *g;
  95         unsigned long flags;
  96         u32 temp;
  97         int bank = offset / 32;
  98         u32 mask = __gpio_mask(offset);
  99
 100         g = d->regs[bank];
 101         spin_lock_irqsave(&d->lock, flags);
 102         temp = readl_relaxed(&g->dir);
 103         if (out) {
 104                 temp &= ~mask;
 105                 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
 106         } else {
 107                 temp |= mask;
 108         }
 109         writel_relaxed(temp, &g->dir);
 110         spin_unlock_irqrestore(&d->lock, flags);
 111
 112         return 0;
 113 }
 114
 115 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 116 {
 117         return __davinci_direction(chip, offset, false, 0);
 118 }
 119
 120 static int
 121 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 122 {
 123         return __davinci_direction(chip, offset, true, value);
 124 }
 125
 126 /*
 127  * Read the pin's value (works even if it's set up as output);
 128  * returns zero/nonzero.
 129  *
 130  * Note that changes are synched to the GPIO clock, so reading values back
 131  * right after you've set them may give old values.
 132  */
 133 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 134 {
 135         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 136         struct davinci_gpio_regs __iomem *g;
 137         int bank = offset / 32;
 138
 139         g = d->regs[bank];
 140
 141         return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
 142 }
 143
 144 /*
 145  * Assuming the pin is muxed as a gpio output, set its output value.
 146  */
 147 static void
 148 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 149 {
 150         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 151         struct davinci_gpio_regs __iomem *g;
 152         int bank = offset / 32;
 153
 154         g = d->regs[bank];
 155
 156         writel_relaxed(__gpio_mask(offset),
 157                        value ? &g->set_data : &g->clr_data);
 158 }
 159
 160 static struct davinci_gpio_platform_data *
 161 davinci_gpio_get_pdata(struct platform_device *pdev)
 162 {
 163         struct device_node *dn = pdev->dev.of_node;
 164         struct davinci_gpio_platform_data *pdata;
 165         int ret;
 166         u32 val;
 167
 168         if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
 169                 return dev_get_platdata(&pdev->dev);
 170
 171         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 172         if (!pdata)
 173                 return NULL;
 174
 175         ret = of_property_read_u32(dn, "ti,ngpio", &val);
 176         if (ret)
 177                 goto of_err;
 178
 179         pdata->ngpio = val;
 180
 181         ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
 182         if (ret)
 183                 goto of_err;
 184
 185         pdata->gpio_unbanked = val;
 186
 187         return pdata;
 188
 189 of_err:
 190         dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
 191         return NULL;
 192 }
 193
 194 static int davinci_gpio_probe(struct platform_device *pdev)
 195 {
 196         int bank, i, ret = 0;
 197         unsigned int ngpio, nbank, nirq;
 198         struct davinci_gpio_controller *chips;
 199         struct davinci_gpio_platform_data *pdata;
 200         struct device *dev = &pdev->dev;
 201         struct resource *res;
 202
 203         pdata = davinci_gpio_get_pdata(pdev);
 204         if (!pdata) {
 205                 dev_err(dev, "No platform data found\n");
 206                 return -EINVAL;
 207         }
 208
 209         dev->platform_data = pdata;
 210
 211         /*
 212          * The gpio banks conceptually expose a segmented bitmap,
 213          * and "ngpio" is one more than the largest zero-based
 214          * bit index that's valid.
 215          */
 216         ngpio = pdata->ngpio;
 217         if (ngpio == 0) {
 218                 dev_err(dev, "How many GPIOs?\n");
 219                 return -EINVAL;
 220         }
 221
 222         if (WARN_ON(ARCH_NR_GPIOS < ngpio))
 223                 ngpio = ARCH_NR_GPIOS;
 224
 225         /*
 226          * If there are unbanked interrupts then the number of
 227          * interrupts is equal to number of gpios else all are banked so
 228          * number of interrupts is equal to number of banks(each with 16 gpios)
 229          */
 230         if (pdata->gpio_unbanked)
 231                 nirq = pdata->gpio_unbanked;
 232         else
 233                 nirq = DIV_ROUND_UP(ngpio, 16);
 234
 235         chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
 236         if (!chips)
 237                 return -ENOMEM;
 238
 239         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 240         gpio_base = devm_ioremap_resource(dev, res);
 241         if (IS_ERR(gpio_base))
 242                 return PTR_ERR(gpio_base);
 243
 244         for (i = 0; i < nirq; i++) {
 245                 chips->irqs[i] = platform_get_irq(pdev, i);
 246                 if (chips->irqs[i] < 0) {
 247                         dev_info(dev, "IRQ not populated, err = %d\n",
 248                                  chips->irqs[i]);
 249                         return chips->irqs[i];
 250                 }
 251         }
 252
 253         chips->chip.label = dev_name(dev);
 254
 255         chips->chip.direction_input = davinci_direction_in;
 256         chips->chip.get = davinci_gpio_get;
 257         chips->chip.direction_output = davinci_direction_out;
 258         chips->chip.set = davinci_gpio_set;
 259
 260         chips->chip.ngpio = ngpio;
 261         chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
 262
 263 #ifdef CONFIG_OF_GPIO
 264         chips->chip.of_gpio_n_cells = 2;
 265         chips->chip.parent = dev;
 266         chips->chip.of_node = dev->of_node;
 267
 268         if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
 269                 chips->chip.request = gpiochip_generic_request;
 270                 chips->chip.free = gpiochip_generic_free;
 271         }
 272 #endif
 273         spin_lock_init(&chips->lock);
 274
 275         nbank = DIV_ROUND_UP(ngpio, 32);
 276         for (bank = 0; bank < nbank; bank++)
 277                 chips->regs[bank] = gpio_base + offset_array[bank];
 278
 279         ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
 280         if (ret)
 281                 return ret;
 282
 283         platform_set_drvdata(pdev, chips);
 284         ret = davinci_gpio_irq_setup(pdev);
 285         if (ret)
 286                 return ret;
 287
 288         return 0;
 289 }
 290
 291 /*--------------------------------------------------------------------------*/
 292 /*
 293  * We expect irqs will normally be set up as input pins, but they can also be
 294  * used as output pins ... which is convenient for testing.
 295  *
 296  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 297  * to their GPIOBNK0 irq, with a bit less overhead.
 298  *
 299  * All those INTC hookups (direct, plus several IRQ banks) can also
 300  * serve as EDMA event triggers.
 301  */
 302
 303 static void gpio_irq_disable(struct irq_data *d)
 304 {
 305         struct davinci_gpio_regs __iomem *g = irq2regs(d);
 306         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 307
 308         writel_relaxed(mask, &g->clr_falling);
 309         writel_relaxed(mask, &g->clr_rising);
 310 }
 311
 312 static void gpio_irq_enable(struct irq_data *d)
 313 {
 314         struct davinci_gpio_regs __iomem *g = irq2regs(d);
 315         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 316         unsigned status = irqd_get_trigger_type(d);
 317
 318         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 319         if (!status)
 320                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 321
 322         if (status & IRQ_TYPE_EDGE_FALLING)
 323                 writel_relaxed(mask, &g->set_falling);
 324         if (status & IRQ_TYPE_EDGE_RISING)
 325                 writel_relaxed(mask, &g->set_rising);
 326 }
 327
 328 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
 329 {
 330         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 331                 return -EINVAL;
 332
 333         return 0;
 334 }
 335
 336 static struct irq_chip gpio_irqchip = {
 337         .name           = "GPIO",
 338         .irq_enable     = gpio_irq_enable,
 339         .irq_disable    = gpio_irq_disable,
 340         .irq_set_type   = gpio_irq_type,
 341         .flags          = IRQCHIP_SET_TYPE_MASKED,
 342 };
 343
 344 static void gpio_irq_handler(struct irq_desc *desc)
 345 {
 346         struct davinci_gpio_regs __iomem *g;
 347         u32 mask = 0xffff;
 348         int bank_num;
 349         struct davinci_gpio_controller *d;
 350         struct davinci_gpio_irq_data *irqdata;
 351
 352         irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
 353         bank_num = irqdata->bank_num;
 354         g = irqdata->regs;
 355         d = irqdata->chip;
 356
 357         /* we only care about one bank */
 358         if ((bank_num % 2) == 1)
 359                 mask <<= 16;
 360
 361         /* temporarily mask (level sensitive) parent IRQ */
 362         chained_irq_enter(irq_desc_get_chip(desc), desc);
 363         while (1) {
 364                 u32             status;
 365                 int             bit;
 366                 irq_hw_number_t hw_irq;
 367
 368                 /* ack any irqs */
 369                 status = readl_relaxed(&g->intstat) & mask;
 370                 if (!status)
 371                         break;
 372                 writel_relaxed(status, &g->intstat);
 373
 374                 /* now demux them to the right lowlevel handler */
 375
 376                 while (status) {
 377                         bit = __ffs(status);
 378                         status &= ~BIT(bit);
 379                         /* Max number of gpios per controller is 144 so
 380                          * hw_irq will be in [0..143]
 381                          */
 382                         hw_irq = (bank_num / 2) * 32 + bit;
 383
 384                         generic_handle_irq(
 385                                 irq_find_mapping(d->irq_domain, hw_irq));
 386                 }
 387         }
 388         chained_irq_exit(irq_desc_get_chip(desc), desc);
 389         /* now it may re-trigger */
 390 }
 391
 392 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 393 {
 394         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 395
 396         if (d->irq_domain)
 397                 return irq_create_mapping(d->irq_domain, offset);
 398         else
 399                 return -ENXIO;
 400 }
 401
 402 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 403 {
 404         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 405
 406         /*
 407          * NOTE:  we assume for now that only irqs in the first gpio_chip
 408          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 409          */
 410         if (offset < d->gpio_unbanked)
 411                 return d->irqs[offset];
 412         else
 413                 return -ENODEV;
 414 }
 415
 416 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
 417 {
 418         struct davinci_gpio_controller *d;
 419         struct davinci_gpio_regs __iomem *g;
 420         u32 mask, i;
 421
 422         d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
 423         g = (struct davinci_gpio_regs __iomem *)d->regs[0];
 424         for (i = 0; i < MAX_INT_PER_BANK; i++)
 425                 if (data->irq == d->irqs[i])
 426                         break;
 427
 428         if (i == MAX_INT_PER_BANK)
 429                 return -EINVAL;
 430
 431         mask = __gpio_mask(i);
 432
 433         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 434                 return -EINVAL;
 435
 436         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 437                      ? &g->set_falling : &g->clr_falling);
 438         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 439                      ? &g->set_rising : &g->clr_rising);
 440
 441         return 0;
 442 }
 443
 444 static int
 445 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 446                      irq_hw_number_t hw)
 447 {
 448         struct davinci_gpio_controller *chips =
 449                                 (struct davinci_gpio_controller *)d->host_data;
 450         struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
 451
 452         irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
 453                                 "davinci_gpio");
 454         irq_set_irq_type(irq, IRQ_TYPE_NONE);
 455         irq_set_chip_data(irq, (__force void *)g);
 456         irq_set_handler_data(irq, (void *)__gpio_mask(hw));
 457
 458         return 0;
 459 }
 460
 461 static const struct irq_domain_ops davinci_gpio_irq_ops = {
 462         .map = davinci_gpio_irq_map,
 463         .xlate = irq_domain_xlate_onetwocell,
 464 };
 465
 466 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
 467 {
 468         static struct irq_chip_type gpio_unbanked;
 469
 470         gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
 471
 472         return &gpio_unbanked.chip;
 473 };
 474
 475 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
 476 {
 477         static struct irq_chip gpio_unbanked;
 478
 479         gpio_unbanked = *irq_get_chip(irq);
 480         return &gpio_unbanked;
 481 };
 482
 483 static const struct of_device_id davinci_gpio_ids[];
 484
 485 /*
 486  * NOTE:  for suspend/resume, probably best to make a platform_device with
 487  * suspend_late/resume_resume calls hooking into results of the set_wake()
 488  * calls ... so if no gpios are wakeup events the clock can be disabled,
 489  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 490  * (dm6446) can be set appropriately for GPIOV33 pins.
 491  */
 492
 493 static int davinci_gpio_irq_setup(struct platform_device *pdev)
 494 {
 495         unsigned        gpio, bank;
 496         int             irq;
 497         int             ret;
 498         struct clk      *clk;
 499         u32             binten = 0;
 500         unsigned        ngpio;
 501         struct device *dev = &pdev->dev;
 502         struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
 503         struct davinci_gpio_platform_data *pdata = dev->platform_data;
 504         struct davinci_gpio_regs __iomem *g;
 505         struct irq_domain       *irq_domain = NULL;
 506         const struct of_device_id *match;
 507         struct irq_chip *irq_chip;
 508         struct davinci_gpio_irq_data *irqdata;
 509         gpio_get_irq_chip_cb_t gpio_get_irq_chip;
 510
 511         /*
 512          * Use davinci_gpio_get_irq_chip by default to handle non DT cases
 513          */
 514         gpio_get_irq_chip = davinci_gpio_get_irq_chip;
 515         match = of_match_device(of_match_ptr(davinci_gpio_ids),
 516                                 dev);
 517         if (match)
 518                 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
 519
 520         ngpio = pdata->ngpio;
 521
 522         clk = devm_clk_get(dev, "gpio");
 523         if (IS_ERR(clk)) {
 524                 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
 525                 return PTR_ERR(clk);
 526         }
 527
 528         ret = clk_prepare_enable(clk);
 529         if (ret)
 530                 return ret;
 531
 532         if (!pdata->gpio_unbanked) {
 533                 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
 534                 if (irq < 0) {
 535                         dev_err(dev, "Couldn't allocate IRQ numbers\n");
 536                         clk_disable_unprepare(clk);
 537                         return irq;
 538                 }
 539
 540                 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
 541                                                         &davinci_gpio_irq_ops,
 542                                                         chips);
 543                 if (!irq_domain) {
 544                         dev_err(dev, "Couldn't register an IRQ domain\n");
 545                         clk_disable_unprepare(clk);
 546                         return -ENODEV;
 547                 }
 548         }
 549
 550         /*
 551          * Arrange gpio_to_irq() support, handling either direct IRQs or
 552          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
 553          * IRQs, while the others use banked IRQs, would need some setup
 554          * tweaks to recognize hardware which can do that.
 555          */
 556         chips->chip.to_irq = gpio_to_irq_banked;
 557         chips->irq_domain = irq_domain;
 558
 559         /*
 560          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
 561          * controller only handling trigger modes.  We currently assume no
 562          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
 563          */
 564         if (pdata->gpio_unbanked) {
 565                 /* pass "bank 0" GPIO IRQs to AINTC */
 566                 chips->chip.to_irq = gpio_to_irq_unbanked;
 567                 chips->gpio_unbanked = pdata->gpio_unbanked;
 568                 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
 569
 570                 /* AINTC handles mask/unmask; GPIO handles triggering */
 571                 irq = chips->irqs[0];
 572                 irq_chip = gpio_get_irq_chip(irq);
 573                 irq_chip->name = "GPIO-AINTC";
 574                 irq_chip->irq_set_type = gpio_irq_type_unbanked;
 575
 576                 /* default trigger: both edges */
 577                 g = chips->regs[0];
 578                 writel_relaxed(~0, &g->set_falling);
 579                 writel_relaxed(~0, &g->set_rising);
 580
 581                 /* set the direct IRQs up to use that irqchip */
 582                 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
 583                         irq_set_chip(chips->irqs[gpio], irq_chip);
 584                         irq_set_handler_data(chips->irqs[gpio], chips);
 585                         irq_set_status_flags(chips->irqs[gpio],
 586                                              IRQ_TYPE_EDGE_BOTH);
 587                 }
 588
 589                 goto done;
 590         }
 591
 592         /*
 593          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
 594          * then chain through our own handler.
 595          */
 596         for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
 597                 /* disabled by default, enabled only as needed
 598                  * There are register sets for 32 GPIOs. 2 banks of 16
 599                  * GPIOs are covered by each set of registers hence divide by 2
 600                  */
 601                 g = chips->regs[bank / 2];
 602                 writel_relaxed(~0, &g->clr_falling);
 603                 writel_relaxed(~0, &g->clr_rising);
 604
 605                 /*
 606                  * Each chip handles 32 gpios, and each irq bank consists of 16
 607                  * gpio irqs. Pass the irq bank's corresponding controller to
 608                  * the chained irq handler.
 609                  */
 610                 irqdata = devm_kzalloc(&pdev->dev,
 611                                        sizeof(struct
 612                                               davinci_gpio_irq_data),
 613                                               GFP_KERNEL);
 614                 if (!irqdata) {
 615                         clk_disable_unprepare(clk);
 616                         return -ENOMEM;
 617                 }
 618
 619                 irqdata->regs = g;
 620                 irqdata->bank_num = bank;
 621                 irqdata->chip = chips;
 622
 623                 irq_set_chained_handler_and_data(chips->irqs[bank],
 624                                                  gpio_irq_handler, irqdata);
 625
 626                 binten |= BIT(bank);
 627         }
 628
 629 done:
 630         /*
 631          * BINTEN -- per-bank interrupt enable. genirq would also let these
 632          * bits be set/cleared dynamically.
 633          */
 634         writel_relaxed(binten, gpio_base + BINTEN);
 635
 636         return 0;
 637 }
 638
 639 static const struct of_device_id davinci_gpio_ids[] = {
 640         { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
 641         { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
 642         { /* sentinel */ },
 643 };
 644 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
 645
 646 static struct platform_driver davinci_gpio_driver = {
 647         .probe          = davinci_gpio_probe,
 648         .driver         = {
 649                 .name           = "davinci_gpio",
 650                 .of_match_table = of_match_ptr(davinci_gpio_ids),
 651         },
 652 };
 653
 654 /**
 655  * GPIO driver registration needs to be done before machine_init functions
 656  * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
 657  */
 658 static int __init davinci_gpio_drv_reg(void)
 659 {
 660         return platform_driver_register(&davinci_gpio_driver);
 661 }
 662 postcore_initcall(davinci_gpio_drv_reg);