drivers/gpio/gpio-davinci.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12 #include <linux/gpio.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/platform_data/gpio-davinci.h>
  25 #include <linux/irqchip/chained_irq.h>
  26
  27 struct davinci_gpio_regs {
  28         u32     dir;
  29         u32     out_data;
  30         u32     set_data;
  31         u32     clr_data;
  32         u32     in_data;
  33         u32     set_rising;
  34         u32     clr_rising;
  35         u32     set_falling;
  36         u32     clr_falling;
  37         u32     intstat;
  38 };
  39
  40 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
  41
  42 #define BINTEN  0x8 /* GPIO Interrupt Per-Bank Enable Register */
  43 #define MAX_LABEL_SIZE 20
  44
  45 static void __iomem *gpio_base;
  46 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
  47
  48 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
  49 {
  50         struct davinci_gpio_regs __iomem *g;
  51
  52         g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
  53
  54         return g;
  55 }
  56
  57 static int davinci_gpio_irq_setup(struct platform_device *pdev);
  58
  59 /*--------------------------------------------------------------------------*/
  60
  61 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
  62 static inline int __davinci_direction(struct gpio_chip *chip,
  63                         unsigned offset, bool out, int value)
  64 {
  65         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
  66         struct davinci_gpio_regs __iomem *g;
  67         unsigned long flags;
  68         u32 temp;
  69         int bank = offset / 32;
  70         u32 mask = __gpio_mask(offset);
  71
  72         g = d->regs[bank];
  73         spin_lock_irqsave(&d->lock, flags);
  74         temp = readl_relaxed(&g->dir);
  75         if (out) {
  76                 temp &= ~mask;
  77                 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
  78         } else {
  79                 temp |= mask;
  80         }
  81         writel_relaxed(temp, &g->dir);
  82         spin_unlock_irqrestore(&d->lock, flags);
  83
  84         return 0;
  85 }
  86
  87 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  88 {
  89         return __davinci_direction(chip, offset, false, 0);
  90 }
  91
  92 static int
  93 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  94 {
  95         return __davinci_direction(chip, offset, true, value);
  96 }
  97
  98 /*
  99  * Read the pin's value (works even if it's set up as output);
 100  * returns zero/nonzero.
 101  *
 102  * Note that changes are synched to the GPIO clock, so reading values back
 103  * right after you've set them may give old values.
 104  */
 105 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 106 {
 107         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 108         struct davinci_gpio_regs __iomem *g;
 109         int bank = offset / 32;
 110
 111         g = d->regs[bank];
 112
 113         return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
 114 }
 115
 116 /*
 117  * Assuming the pin is muxed as a gpio output, set its output value.
 118  */
 119 static void
 120 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 121 {
 122         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 123         struct davinci_gpio_regs __iomem *g;
 124         int bank = offset / 32;
 125
 126         g = d->regs[bank];
 127
 128         writel_relaxed(__gpio_mask(offset),
 129                        value ? &g->set_data : &g->clr_data);
 130 }
 131
 132 static struct davinci_gpio_platform_data *
 133 davinci_gpio_get_pdata(struct platform_device *pdev)
 134 {
 135         struct device_node *dn = pdev->dev.of_node;
 136         struct davinci_gpio_platform_data *pdata;
 137         int ret;
 138         u32 val;
 139
 140         if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
 141                 return dev_get_platdata(&pdev->dev);
 142
 143         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 144         if (!pdata)
 145                 return NULL;
 146
 147         ret = of_property_read_u32(dn, "ti,ngpio", &val);
 148         if (ret)
 149                 goto of_err;
 150
 151         pdata->ngpio = val;
 152
 153         ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
 154         if (ret)
 155                 goto of_err;
 156
 157         pdata->gpio_unbanked = val;
 158
 159         return pdata;
 160
 161 of_err:
 162         dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
 163         return NULL;
 164 }
 165
 166 static int davinci_gpio_probe(struct platform_device *pdev)
 167 {
 168         static int ctrl_num, bank_base;
 169         int gpio, bank, ret = 0;
 170         unsigned ngpio, nbank;
 171         struct davinci_gpio_controller *chips;
 172         struct davinci_gpio_platform_data *pdata;
 173         struct device *dev = &pdev->dev;
 174         struct resource *res;
 175         char label[MAX_LABEL_SIZE];
 176
 177         pdata = davinci_gpio_get_pdata(pdev);
 178         if (!pdata) {
 179                 dev_err(dev, "No platform data found\n");
 180                 return -EINVAL;
 181         }
 182
 183         dev->platform_data = pdata;
 184
 185         /*
 186          * The gpio banks conceptually expose a segmented bitmap,
 187          * and "ngpio" is one more than the largest zero-based
 188          * bit index that's valid.
 189          */
 190         ngpio = pdata->ngpio;
 191         if (ngpio == 0) {
 192                 dev_err(dev, "How many GPIOs?\n");
 193                 return -EINVAL;
 194         }
 195
 196         if (WARN_ON(ARCH_NR_GPIOS < ngpio))
 197                 ngpio = ARCH_NR_GPIOS;
 198
 199         nbank = DIV_ROUND_UP(ngpio, 32);
 200         chips = devm_kzalloc(dev,
 201                              nbank * sizeof(struct davinci_gpio_controller),
 202                              GFP_KERNEL);
 203         if (!chips)
 204                 return -ENOMEM;
 205
 206         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 207         gpio_base = devm_ioremap_resource(dev, res);
 208         if (IS_ERR(gpio_base))
 209                 return PTR_ERR(gpio_base);
 210
 211         snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++);
 212         chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL);
 213                 if (!chips->chip.label)
 214                         return -ENOMEM;
 215
 216         chips->chip.direction_input = davinci_direction_in;
 217         chips->chip.get = davinci_gpio_get;
 218         chips->chip.direction_output = davinci_direction_out;
 219         chips->chip.set = davinci_gpio_set;
 220
 221         chips->chip.ngpio = ngpio;
 222         chips->chip.base = bank_base;
 223
 224 #ifdef CONFIG_OF_GPIO
 225         chips->chip.of_gpio_n_cells = 2;
 226         chips->chip.parent = dev;
 227         chips->chip.of_node = dev->of_node;
 228 #endif
 229         spin_lock_init(&chips->lock);
 230         bank_base += ngpio;
 231
 232         for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++)
 233                 chips->regs[bank] = gpio_base + offset_array[bank];
 234
 235         ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
 236         if (ret)
 237                 goto err;
 238
 239         platform_set_drvdata(pdev, chips);
 240         ret = davinci_gpio_irq_setup(pdev);
 241         if (ret)
 242                 goto err;
 243
 244         return 0;
 245
 246 err:
 247         /* Revert the static variable increments */
 248         ctrl_num--;
 249         bank_base -= ngpio;
 250
 251         return ret;
 252 }
 253
 254 /*--------------------------------------------------------------------------*/
 255 /*
 256  * We expect irqs will normally be set up as input pins, but they can also be
 257  * used as output pins ... which is convenient for testing.
 258  *
 259  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 260  * to their GPIOBNK0 irq, with a bit less overhead.
 261  *
 262  * All those INTC hookups (direct, plus several IRQ banks) can also
 263  * serve as EDMA event triggers.
 264  */
 265
 266 static void gpio_irq_disable(struct irq_data *d)
 267 {
 268         struct davinci_gpio_regs __iomem *g = irq2regs(d);
 269         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 270
 271         writel_relaxed(mask, &g->clr_falling);
 272         writel_relaxed(mask, &g->clr_rising);
 273 }
 274
 275 static void gpio_irq_enable(struct irq_data *d)
 276 {
 277         struct davinci_gpio_regs __iomem *g = irq2regs(d);
 278         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 279         unsigned status = irqd_get_trigger_type(d);
 280
 281         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 282         if (!status)
 283                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 284
 285         if (status & IRQ_TYPE_EDGE_FALLING)
 286                 writel_relaxed(mask, &g->set_falling);
 287         if (status & IRQ_TYPE_EDGE_RISING)
 288                 writel_relaxed(mask, &g->set_rising);
 289 }
 290
 291 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
 292 {
 293         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 294                 return -EINVAL;
 295
 296         return 0;
 297 }
 298
 299 static struct irq_chip gpio_irqchip = {
 300         .name           = "GPIO",
 301         .irq_enable     = gpio_irq_enable,
 302         .irq_disable    = gpio_irq_disable,
 303         .irq_set_type   = gpio_irq_type,
 304         .flags          = IRQCHIP_SET_TYPE_MASKED,
 305 };
 306
 307 static void gpio_irq_handler(struct irq_desc *desc)
 308 {
 309         struct davinci_gpio_regs __iomem *g;
 310         u32 mask = 0xffff;
 311         int bank_num;
 312         struct davinci_gpio_controller *d;
 313         struct davinci_gpio_irq_data *irqdata;
 314
 315         irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
 316         bank_num = irqdata->bank_num;
 317         g = irqdata->regs;
 318         d = irqdata->chip;
 319
 320         /* we only care about one bank */
 321         if ((bank_num % 2) == 1)
 322                 mask <<= 16;
 323
 324         /* temporarily mask (level sensitive) parent IRQ */
 325         chained_irq_enter(irq_desc_get_chip(desc), desc);
 326         while (1) {
 327                 u32             status;
 328                 int             bit;
 329                 irq_hw_number_t hw_irq;
 330
 331                 /* ack any irqs */
 332                 status = readl_relaxed(&g->intstat) & mask;
 333                 if (!status)
 334                         break;
 335                 writel_relaxed(status, &g->intstat);
 336
 337                 /* now demux them to the right lowlevel handler */
 338
 339                 while (status) {
 340                         bit = __ffs(status);
 341                         status &= ~BIT(bit);
 342                         /* Max number of gpios per controller is 144 so
 343                          * hw_irq will be in [0..143]
 344                          */
 345                         hw_irq = (bank_num / 2) * 32 + bit;
 346
 347                         generic_handle_irq(
 348                                 irq_find_mapping(d->irq_domain, hw_irq));
 349                 }
 350         }
 351         chained_irq_exit(irq_desc_get_chip(desc), desc);
 352         /* now it may re-trigger */
 353 }
 354
 355 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 356 {
 357         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 358
 359         if (d->irq_domain)
 360                 return irq_create_mapping(d->irq_domain, offset);
 361         else
 362                 return -ENXIO;
 363 }
 364
 365 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 366 {
 367         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 368
 369         /*
 370          * NOTE:  we assume for now that only irqs in the first gpio_chip
 371          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 372          */
 373         if (offset < d->gpio_unbanked)
 374                 return d->base_irq + offset;
 375         else
 376                 return -ENODEV;
 377 }
 378
 379 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
 380 {
 381         struct davinci_gpio_controller *d;
 382         struct davinci_gpio_regs __iomem *g;
 383         u32 mask;
 384
 385         d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
 386         g = (struct davinci_gpio_regs __iomem *)d->regs;
 387         mask = __gpio_mask(data->irq - d->base_irq);
 388
 389         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 390                 return -EINVAL;
 391
 392         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 393                      ? &g->set_falling : &g->clr_falling);
 394         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 395                      ? &g->set_rising : &g->clr_rising);
 396
 397         return 0;
 398 }
 399
 400 static int
 401 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 402                      irq_hw_number_t hw)
 403 {
 404         struct davinci_gpio_controller *chips =
 405                                 (struct davinci_gpio_controller *)d->host_data;
 406         struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
 407
 408         irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
 409                                 "davinci_gpio");
 410         irq_set_irq_type(irq, IRQ_TYPE_NONE);
 411         irq_set_chip_data(irq, (__force void *)g);
 412         irq_set_handler_data(irq, (void *)__gpio_mask(hw));
 413
 414         return 0;
 415 }
 416
 417 static const struct irq_domain_ops davinci_gpio_irq_ops = {
 418         .map = davinci_gpio_irq_map,
 419         .xlate = irq_domain_xlate_onetwocell,
 420 };
 421
 422 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
 423 {
 424         static struct irq_chip_type gpio_unbanked;
 425
 426         gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
 427
 428         return &gpio_unbanked.chip;
 429 };
 430
 431 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
 432 {
 433         static struct irq_chip gpio_unbanked;
 434
 435         gpio_unbanked = *irq_get_chip(irq);
 436         return &gpio_unbanked;
 437 };
 438
 439 static const struct of_device_id davinci_gpio_ids[];
 440
 441 /*
 442  * NOTE:  for suspend/resume, probably best to make a platform_device with
 443  * suspend_late/resume_resume calls hooking into results of the set_wake()
 444  * calls ... so if no gpios are wakeup events the clock can be disabled,
 445  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 446  * (dm6446) can be set appropriately for GPIOV33 pins.
 447  */
 448
 449 static int davinci_gpio_irq_setup(struct platform_device *pdev)
 450 {
 451         unsigned        gpio, bank;
 452         int             irq;
 453         int             ret;
 454         struct clk      *clk;
 455         u32             binten = 0;
 456         unsigned        ngpio, bank_irq;
 457         struct device *dev = &pdev->dev;
 458         struct resource *res;
 459         struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
 460         struct davinci_gpio_platform_data *pdata = dev->platform_data;
 461         struct davinci_gpio_regs __iomem *g;
 462         struct irq_domain       *irq_domain = NULL;
 463         const struct of_device_id *match;
 464         struct irq_chip *irq_chip;
 465         struct davinci_gpio_irq_data *irqdata;
 466         gpio_get_irq_chip_cb_t gpio_get_irq_chip;
 467
 468         /*
 469          * Use davinci_gpio_get_irq_chip by default to handle non DT cases
 470          */
 471         gpio_get_irq_chip = davinci_gpio_get_irq_chip;
 472         match = of_match_device(of_match_ptr(davinci_gpio_ids),
 473                                 dev);
 474         if (match)
 475                 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
 476
 477         ngpio = pdata->ngpio;
 478         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 479         if (!res) {
 480                 dev_err(dev, "Invalid IRQ resource\n");
 481                 return -EBUSY;
 482         }
 483
 484         bank_irq = res->start;
 485
 486         if (!bank_irq) {
 487                 dev_err(dev, "Invalid IRQ resource\n");
 488                 return -ENODEV;
 489         }
 490
 491         clk = devm_clk_get(dev, "gpio");
 492         if (IS_ERR(clk)) {
 493                 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
 494                 return PTR_ERR(clk);
 495         }
 496         ret = clk_prepare_enable(clk);
 497         if (ret)
 498                 return ret;
 499
 500         if (!pdata->gpio_unbanked) {
 501                 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
 502                 if (irq < 0) {
 503                         dev_err(dev, "Couldn't allocate IRQ numbers\n");
 504                         clk_disable_unprepare(clk);
 505                         return irq;
 506                 }
 507
 508                 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
 509                                                         &davinci_gpio_irq_ops,
 510                                                         chips);
 511                 if (!irq_domain) {
 512                         dev_err(dev, "Couldn't register an IRQ domain\n");
 513                         clk_disable_unprepare(clk);
 514                         return -ENODEV;
 515                 }
 516         }
 517
 518         /*
 519          * Arrange gpio_to_irq() support, handling either direct IRQs or
 520          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
 521          * IRQs, while the others use banked IRQs, would need some setup
 522          * tweaks to recognize hardware which can do that.
 523          */
 524         chips->chip.to_irq = gpio_to_irq_banked;
 525         chips->irq_domain = irq_domain;
 526
 527         /*
 528          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
 529          * controller only handling trigger modes.  We currently assume no
 530          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
 531          */
 532         if (pdata->gpio_unbanked) {
 533                 /* pass "bank 0" GPIO IRQs to AINTC */
 534                 chips->chip.to_irq = gpio_to_irq_unbanked;
 535                 chips->base_irq = bank_irq;
 536                 chips->gpio_unbanked = pdata->gpio_unbanked;
 537                 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
 538
 539                 /* AINTC handles mask/unmask; GPIO handles triggering */
 540                 irq = bank_irq;
 541                 irq_chip = gpio_get_irq_chip(irq);
 542                 irq_chip->name = "GPIO-AINTC";
 543                 irq_chip->irq_set_type = gpio_irq_type_unbanked;
 544
 545                 /* default trigger: both edges */
 546                 g = chips->regs[0];
 547                 writel_relaxed(~0, &g->set_falling);
 548                 writel_relaxed(~0, &g->set_rising);
 549
 550                 /* set the direct IRQs up to use that irqchip */
 551                 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
 552                         irq_set_chip(irq, irq_chip);
 553                         irq_set_handler_data(irq, chips);
 554                         irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
 555                 }
 556
 557                 goto done;
 558         }
 559
 560         /*
 561          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
 562          * then chain through our own handler.
 563          */
 564         for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
 565                 /* disabled by default, enabled only as needed
 566                  * There are register sets for 32 GPIOs. 2 banks of 16
 567                  * GPIOs are covered by each set of registers hence divide by 2
 568                  */
 569                 g = chips->regs[bank / 2];
 570                 writel_relaxed(~0, &g->clr_falling);
 571                 writel_relaxed(~0, &g->clr_rising);
 572
 573                 /*
 574                  * Each chip handles 32 gpios, and each irq bank consists of 16
 575                  * gpio irqs. Pass the irq bank's corresponding controller to
 576                  * the chained irq handler.
 577                  */
 578                 irqdata = devm_kzalloc(&pdev->dev,
 579                                        sizeof(struct
 580                                               davinci_gpio_irq_data),
 581                                               GFP_KERNEL);
 582                 if (!irqdata) {
 583                         clk_disable_unprepare(clk);
 584                         return -ENOMEM;
 585                 }
 586
 587                 irqdata->regs = g;
 588                 irqdata->bank_num = bank;
 589                 irqdata->chip = chips;
 590
 591                 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
 592                                                  irqdata);
 593
 594                 binten |= BIT(bank);
 595         }
 596
 597 done:
 598         /*
 599          * BINTEN -- per-bank interrupt enable. genirq would also let these
 600          * bits be set/cleared dynamically.
 601          */
 602         writel_relaxed(binten, gpio_base + BINTEN);
 603
 604         return 0;
 605 }
 606
 607 #if IS_ENABLED(CONFIG_OF)
 608 static const struct of_device_id davinci_gpio_ids[] = {
 609         { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
 610         { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
 611         { /* sentinel */ },
 612 };
 613 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
 614 #endif
 615
 616 static struct platform_driver davinci_gpio_driver = {
 617         .probe          = davinci_gpio_probe,
 618         .driver         = {
 619                 .name           = "davinci_gpio",
 620                 .of_match_table = of_match_ptr(davinci_gpio_ids),
 621         },
 622 };
 623
 624 /**
 625  * GPIO driver registration needs to be done before machine_init functions
 626  * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
 627  */
 628 static int __init davinci_gpio_drv_reg(void)
 629 {
 630         return platform_driver_register(&davinci_gpio_driver);
 631 }
 632 postcore_initcall(davinci_gpio_drv_reg);