1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
5 * 2013 (c) Aeroflex Gaisler AB
7 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
10 * Full documentation of the GRGPIO core can be found here:
11 * http://www.gaisler.com/products/grlib/grip.pdf
13 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
14 * information on open firmware properties.
16 * Contributors: Andreas Larsson <andreas@gaisler.com>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
25 #include <linux/of_platform.h>
26 #include <linux/gpio/driver.h>
27 #include <linux/slab.h>
28 #include <linux/err.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/irqdomain.h>
32 #include <linux/bitops.h>
34 #define GRGPIO_MAX_NGPIO 32
36 #define GRGPIO_DATA 0x00
37 #define GRGPIO_OUTPUT 0x04
38 #define GRGPIO_DIR 0x08
39 #define GRGPIO_IMASK 0x0c
40 #define GRGPIO_IPOL 0x10
41 #define GRGPIO_IEDGE 0x14
42 #define GRGPIO_BYPASS 0x18
43 #define GRGPIO_IMAP_BASE 0x20
45 /* Structure for an irq of the core - called an underlying irq */
47 u8 refcnt
; /* Reference counter to manage requesting/freeing of uirq */
48 u8 uirq
; /* Underlying irq of the gpio driver */
52 * Structure for an irq of a gpio line handed out by this driver. The index is
53 * used to map to the corresponding underlying irq.
56 s8 index
; /* Index into struct grgpio_priv's uirqs, or -1 */
57 u8 irq
; /* irq for the gpio line */
65 u32 imask
; /* irq mask shadow register */
68 * The grgpio core can have multiple "underlying" irqs. The gpio lines
69 * can be mapped to any one or none of these underlying irqs
70 * independently of each other. This driver sets up an irq domain and
71 * hands out separate irqs to each gpio line
73 struct irq_domain
*domain
;
76 * This array contains information on each underlying irq, each
77 * irq of the grgpio core itself.
79 struct grgpio_uirq uirqs
[GRGPIO_MAX_NGPIO
];
82 * This array contains information for each gpio line on the irqs
83 * obtains from this driver. An index value of -1 for a certain gpio
84 * line indicates that the line has no irq. Otherwise the index connects
85 * the irq to the underlying irq by pointing into the uirqs array.
87 struct grgpio_lirq lirqs
[GRGPIO_MAX_NGPIO
];
90 static void grgpio_set_imask(struct grgpio_priv
*priv
, unsigned int offset
,
93 struct gpio_chip
*gc
= &priv
->gc
;
96 priv
->imask
|= BIT(offset
);
98 priv
->imask
&= ~BIT(offset
);
99 gc
->write_reg(priv
->regs
+ GRGPIO_IMASK
, priv
->imask
);
102 static int grgpio_to_irq(struct gpio_chip
*gc
, unsigned offset
)
104 struct grgpio_priv
*priv
= gpiochip_get_data(gc
);
106 if (offset
>= gc
->ngpio
)
109 if (priv
->lirqs
[offset
].index
< 0)
112 return irq_create_mapping(priv
->domain
, offset
);
115 /* -------------------- IRQ chip functions -------------------- */
117 static int grgpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
119 struct grgpio_priv
*priv
= irq_data_get_irq_chip_data(d
);
121 u32 mask
= BIT(d
->hwirq
);
128 case IRQ_TYPE_LEVEL_LOW
:
132 case IRQ_TYPE_LEVEL_HIGH
:
136 case IRQ_TYPE_EDGE_FALLING
:
140 case IRQ_TYPE_EDGE_RISING
:
148 spin_lock_irqsave(&priv
->gc
.bgpio_lock
, flags
);
150 ipol
= priv
->gc
.read_reg(priv
->regs
+ GRGPIO_IPOL
) & ~mask
;
151 iedge
= priv
->gc
.read_reg(priv
->regs
+ GRGPIO_IEDGE
) & ~mask
;
153 priv
->gc
.write_reg(priv
->regs
+ GRGPIO_IPOL
, ipol
| pol
);
154 priv
->gc
.write_reg(priv
->regs
+ GRGPIO_IEDGE
, iedge
| edge
);
156 spin_unlock_irqrestore(&priv
->gc
.bgpio_lock
, flags
);
161 static void grgpio_irq_mask(struct irq_data
*d
)
163 struct grgpio_priv
*priv
= irq_data_get_irq_chip_data(d
);
164 int offset
= d
->hwirq
;
167 spin_lock_irqsave(&priv
->gc
.bgpio_lock
, flags
);
169 grgpio_set_imask(priv
, offset
, 0);
171 spin_unlock_irqrestore(&priv
->gc
.bgpio_lock
, flags
);
174 static void grgpio_irq_unmask(struct irq_data
*d
)
176 struct grgpio_priv
*priv
= irq_data_get_irq_chip_data(d
);
177 int offset
= d
->hwirq
;
180 spin_lock_irqsave(&priv
->gc
.bgpio_lock
, flags
);
182 grgpio_set_imask(priv
, offset
, 1);
184 spin_unlock_irqrestore(&priv
->gc
.bgpio_lock
, flags
);
187 static struct irq_chip grgpio_irq_chip
= {
189 .irq_mask
= grgpio_irq_mask
,
190 .irq_unmask
= grgpio_irq_unmask
,
191 .irq_set_type
= grgpio_irq_set_type
,
194 static irqreturn_t
grgpio_irq_handler(int irq
, void *dev
)
196 struct grgpio_priv
*priv
= dev
;
197 int ngpio
= priv
->gc
.ngpio
;
202 spin_lock_irqsave(&priv
->gc
.bgpio_lock
, flags
);
205 * For each gpio line, call its interrupt handler if it its underlying
206 * irq matches the current irq that is handled.
208 for (i
= 0; i
< ngpio
; i
++) {
209 struct grgpio_lirq
*lirq
= &priv
->lirqs
[i
];
211 if (priv
->imask
& BIT(i
) && lirq
->index
>= 0 &&
212 priv
->uirqs
[lirq
->index
].uirq
== irq
) {
213 generic_handle_irq(lirq
->irq
);
218 spin_unlock_irqrestore(&priv
->gc
.bgpio_lock
, flags
);
221 dev_warn(priv
->dev
, "No gpio line matched irq %d\n", irq
);
227 * This function will be called as a consequence of the call to
228 * irq_create_mapping in grgpio_to_irq
230 static int grgpio_irq_map(struct irq_domain
*d
, unsigned int irq
,
231 irq_hw_number_t hwirq
)
233 struct grgpio_priv
*priv
= d
->host_data
;
234 struct grgpio_lirq
*lirq
;
235 struct grgpio_uirq
*uirq
;
243 lirq
= &priv
->lirqs
[offset
];
247 dev_dbg(priv
->dev
, "Mapping irq %d for gpio line %d\n",
250 spin_lock_irqsave(&priv
->gc
.bgpio_lock
, flags
);
252 /* Request underlying irq if not already requested */
254 uirq
= &priv
->uirqs
[lirq
->index
];
255 if (uirq
->refcnt
== 0) {
256 ret
= request_irq(uirq
->uirq
, grgpio_irq_handler
, 0,
257 dev_name(priv
->dev
), priv
);
260 "Could not request underlying irq %d\n",
263 spin_unlock_irqrestore(&priv
->gc
.bgpio_lock
, flags
);
270 spin_unlock_irqrestore(&priv
->gc
.bgpio_lock
, flags
);
273 irq_set_chip_data(irq
, priv
);
274 irq_set_chip_and_handler(irq
, &grgpio_irq_chip
,
276 irq_set_noprobe(irq
);
281 static void grgpio_irq_unmap(struct irq_domain
*d
, unsigned int irq
)
283 struct grgpio_priv
*priv
= d
->host_data
;
285 struct grgpio_lirq
*lirq
;
286 struct grgpio_uirq
*uirq
;
288 int ngpio
= priv
->gc
.ngpio
;
291 irq_set_chip_and_handler(irq
, NULL
, NULL
);
292 irq_set_chip_data(irq
, NULL
);
294 spin_lock_irqsave(&priv
->gc
.bgpio_lock
, flags
);
296 /* Free underlying irq if last user unmapped */
298 for (i
= 0; i
< ngpio
; i
++) {
299 lirq
= &priv
->lirqs
[i
];
300 if (lirq
->irq
== irq
) {
301 grgpio_set_imask(priv
, i
, 0);
310 uirq
= &priv
->uirqs
[lirq
->index
];
312 if (uirq
->refcnt
== 0)
313 free_irq(uirq
->uirq
, priv
);
316 spin_unlock_irqrestore(&priv
->gc
.bgpio_lock
, flags
);
319 static const struct irq_domain_ops grgpio_irq_domain_ops
= {
320 .map
= grgpio_irq_map
,
321 .unmap
= grgpio_irq_unmap
,
324 /* ------------------------------------------------------------ */
326 static int grgpio_probe(struct platform_device
*ofdev
)
328 struct device_node
*np
= ofdev
->dev
.of_node
;
330 struct gpio_chip
*gc
;
331 struct grgpio_priv
*priv
;
332 struct resource
*res
;
339 priv
= devm_kzalloc(&ofdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
343 res
= platform_get_resource(ofdev
, IORESOURCE_MEM
, 0);
344 regs
= devm_ioremap_resource(&ofdev
->dev
, res
);
346 return PTR_ERR(regs
);
349 err
= bgpio_init(gc
, &ofdev
->dev
, 4, regs
+ GRGPIO_DATA
,
350 regs
+ GRGPIO_OUTPUT
, NULL
, regs
+ GRGPIO_DIR
, NULL
,
351 BGPIOF_BIG_ENDIAN_BYTE_ORDER
);
353 dev_err(&ofdev
->dev
, "bgpio_init() failed\n");
358 priv
->imask
= gc
->read_reg(regs
+ GRGPIO_IMASK
);
359 priv
->dev
= &ofdev
->dev
;
362 gc
->owner
= THIS_MODULE
;
363 gc
->to_irq
= grgpio_to_irq
;
364 gc
->label
= devm_kasprintf(&ofdev
->dev
, GFP_KERNEL
, "%pOF", np
);
367 err
= of_property_read_u32(np
, "nbits", &prop
);
368 if (err
|| prop
<= 0 || prop
> GRGPIO_MAX_NGPIO
) {
369 gc
->ngpio
= GRGPIO_MAX_NGPIO
;
371 "No or invalid nbits property: assume %d\n", gc
->ngpio
);
377 * The irqmap contains the index values indicating which underlying irq,
378 * if anyone, is connected to that line
380 irqmap
= (s32
*)of_get_property(np
, "irqmap", &size
);
382 if (size
< gc
->ngpio
) {
384 "irqmap shorter than ngpio (%d < %d)\n",
389 priv
->domain
= irq_domain_add_linear(np
, gc
->ngpio
,
390 &grgpio_irq_domain_ops
,
393 dev_err(&ofdev
->dev
, "Could not add irq domain\n");
397 for (i
= 0; i
< gc
->ngpio
; i
++) {
398 struct grgpio_lirq
*lirq
;
401 lirq
= &priv
->lirqs
[i
];
402 lirq
->index
= irqmap
[i
];
407 ret
= platform_get_irq(ofdev
, lirq
->index
);
410 * Continue without irq functionality for that
414 "Failed to get irq for offset %d\n", i
);
417 priv
->uirqs
[lirq
->index
].uirq
= ret
;
421 platform_set_drvdata(ofdev
, priv
);
423 err
= gpiochip_add_data(gc
, priv
);
425 dev_err(&ofdev
->dev
, "Could not add gpiochip\n");
427 irq_domain_remove(priv
->domain
);
431 dev_info(&ofdev
->dev
, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
432 priv
->regs
, gc
->base
, gc
->ngpio
, priv
->domain
? "on" : "off");
437 static int grgpio_remove(struct platform_device
*ofdev
)
439 struct grgpio_priv
*priv
= platform_get_drvdata(ofdev
);
444 spin_lock_irqsave(&priv
->gc
.bgpio_lock
, flags
);
447 for (i
= 0; i
< GRGPIO_MAX_NGPIO
; i
++) {
448 if (priv
->uirqs
[i
].refcnt
!= 0) {
455 gpiochip_remove(&priv
->gc
);
458 irq_domain_remove(priv
->domain
);
461 spin_unlock_irqrestore(&priv
->gc
.bgpio_lock
, flags
);
466 static const struct of_device_id grgpio_match
[] = {
467 {.name
= "GAISLER_GPIO"},
472 MODULE_DEVICE_TABLE(of
, grgpio_match
);
474 static struct platform_driver grgpio_driver
= {
477 .of_match_table
= grgpio_match
,
479 .probe
= grgpio_probe
,
480 .remove
= grgpio_remove
,
482 module_platform_driver(grgpio_driver
);
484 MODULE_AUTHOR("Aeroflex Gaisler AB.");
485 MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
486 MODULE_LICENSE("GPL");