2 * Intel ICH6-10, Series 5 and 6 GPIO driver
4 * Copyright (C) 2010 Extreme Engineering Solutions.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/gpio.h>
26 #include <linux/platform_device.h>
27 #include <linux/mfd/lpc_ich.h>
29 #define DRV_NAME "gpio_ich"
32 * GPIO register offsets in GPIO I/O space.
33 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
34 * LVLx registers. Logic in the read/write functions takes a register and
35 * an absolute bit number and determines the proper register offset and bit
36 * number in that register. For example, to read the value of GPIO bit 50
37 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
46 static const u8 ichx_regs
[3][3] = {
47 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
48 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
49 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
52 static const u8 ichx_reglen
[3] = {
56 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
57 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
60 /* Max GPIO pins the chipset can have */
63 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
66 /* USE_SEL is bogus on some chipsets, eg 3100 */
67 u32 use_sel_ignore
[3];
69 /* Some chipsets have quirks, let these use their own request/get */
70 int (*request
)(struct gpio_chip
*chip
, unsigned offset
);
71 int (*get
)(struct gpio_chip
*chip
, unsigned offset
);
76 struct platform_device
*dev
;
77 struct gpio_chip chip
;
78 struct resource
*gpio_base
; /* GPIO IO base */
79 struct resource
*pm_base
; /* Power Mangagment IO base */
80 struct ichx_desc
*desc
; /* Pointer to chipset-specific description */
81 u32 orig_gpio_ctrl
; /* Orig CTRL value, used to restore on exit */
82 u8 use_gpio
; /* Which GPIO groups are usable */
85 static int modparam_gpiobase
= -1; /* dynamic */
86 module_param_named(gpiobase
, modparam_gpiobase
, int, 0444);
87 MODULE_PARM_DESC(gpiobase
, "The GPIO number base. -1 means dynamic, "
88 "which is the default.");
90 static int ichx_write_bit(int reg
, unsigned nr
, int val
, int verify
)
98 spin_lock_irqsave(&ichx_priv
.lock
, flags
);
100 data
= ICHX_READ(ichx_regs
[reg
][reg_nr
], ichx_priv
.gpio_base
);
105 ICHX_WRITE(data
, ichx_regs
[reg
][reg_nr
], ichx_priv
.gpio_base
);
106 tmp
= ICHX_READ(ichx_regs
[reg
][reg_nr
], ichx_priv
.gpio_base
);
107 if (verify
&& data
!= tmp
)
110 spin_unlock_irqrestore(&ichx_priv
.lock
, flags
);
115 static int ichx_read_bit(int reg
, unsigned nr
)
119 int reg_nr
= nr
/ 32;
122 spin_lock_irqsave(&ichx_priv
.lock
, flags
);
124 data
= ICHX_READ(ichx_regs
[reg
][reg_nr
], ichx_priv
.gpio_base
);
126 spin_unlock_irqrestore(&ichx_priv
.lock
, flags
);
128 return data
& (1 << bit
) ? 1 : 0;
131 static int ichx_gpio_check_available(struct gpio_chip
*gpio
, unsigned nr
)
133 return (ichx_priv
.use_gpio
& (1 << (nr
/ 32))) ? 0 : -ENXIO
;
136 static int ichx_gpio_direction_input(struct gpio_chip
*gpio
, unsigned nr
)
138 if (!ichx_gpio_check_available(gpio
, nr
))
142 * Try setting pin as an input and verify it worked since many pins
145 if (ichx_write_bit(GPIO_IO_SEL
, nr
, 1, 1))
151 static int ichx_gpio_direction_output(struct gpio_chip
*gpio
, unsigned nr
,
154 if (!ichx_gpio_check_available(gpio
, nr
))
157 /* Set GPIO output value. */
158 ichx_write_bit(GPIO_LVL
, nr
, val
, 0);
161 * Try setting pin as an output and verify it worked since many pins
164 if (ichx_write_bit(GPIO_IO_SEL
, nr
, 0, 1))
170 static int ichx_gpio_get(struct gpio_chip
*chip
, unsigned nr
)
172 if (!ichx_gpio_check_available(chip
, nr
))
175 return ichx_read_bit(GPIO_LVL
, nr
);
178 static int ich6_gpio_get(struct gpio_chip
*chip
, unsigned nr
)
183 if (!ichx_gpio_check_available(chip
, nr
))
187 * GPI 0 - 15 need to be read from the power management registers on
188 * a ICH6/3100 bridge.
191 if (!ichx_priv
.pm_base
)
194 spin_lock_irqsave(&ichx_priv
.lock
, flags
);
196 /* GPI 0 - 15 are latched, write 1 to clear*/
197 ICHX_WRITE(1 << (16 + nr
), 0, ichx_priv
.pm_base
);
198 data
= ICHX_READ(0, ichx_priv
.pm_base
);
200 spin_unlock_irqrestore(&ichx_priv
.lock
, flags
);
202 return (data
>> 16) & (1 << nr
) ? 1 : 0;
204 return ichx_gpio_get(chip
, nr
);
208 static int ichx_gpio_request(struct gpio_chip
*chip
, unsigned nr
)
211 * Note we assume the BIOS properly set a bridge's USE value. Some
212 * chips (eg Intel 3100) have bogus USE values though, so first see if
213 * the chipset's USE value can be trusted for this specific bit.
214 * If it can't be trusted, assume that the pin can be used as a GPIO.
216 if (ichx_priv
.desc
->use_sel_ignore
[nr
/ 32] & (1 << (nr
& 0x1f)))
219 return ichx_read_bit(GPIO_USE_SEL
, nr
) ? 0 : -ENODEV
;
222 static int ich6_gpio_request(struct gpio_chip
*chip
, unsigned nr
)
225 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
226 * bridge as they are controlled by USE register bits 0 and 1. See
227 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
230 if (nr
== 16 || nr
== 17)
233 return ichx_gpio_request(chip
, nr
);
236 static void ichx_gpio_set(struct gpio_chip
*chip
, unsigned nr
, int val
)
238 ichx_write_bit(GPIO_LVL
, nr
, val
, 0);
241 static void ichx_gpiolib_setup(struct gpio_chip
*chip
)
243 chip
->owner
= THIS_MODULE
;
244 chip
->label
= DRV_NAME
;
245 chip
->dev
= &ichx_priv
.dev
->dev
;
247 /* Allow chip-specific overrides of request()/get() */
248 chip
->request
= ichx_priv
.desc
->request
?
249 ichx_priv
.desc
->request
: ichx_gpio_request
;
250 chip
->get
= ichx_priv
.desc
->get
?
251 ichx_priv
.desc
->get
: ichx_gpio_get
;
253 chip
->set
= ichx_gpio_set
;
254 chip
->direction_input
= ichx_gpio_direction_input
;
255 chip
->direction_output
= ichx_gpio_direction_output
;
256 chip
->base
= modparam_gpiobase
;
257 chip
->ngpio
= ichx_priv
.desc
->ngpio
;
259 chip
->dbg_show
= NULL
;
262 /* ICH6-based, 631xesb-based */
263 static struct ichx_desc ich6_desc
= {
264 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
265 .request
= ich6_gpio_request
,
266 .get
= ich6_gpio_get
,
268 /* GPIO 0-15 are read in the GPE0_STS PM register */
275 static struct ichx_desc i3100_desc
= {
277 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
278 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
279 * Datasheet for more info.
281 .use_sel_ignore
= {0x00130000, 0x00010000, 0x0},
283 /* The 3100 needs fixups for GPIO 0 - 17 */
284 .request
= ich6_gpio_request
,
285 .get
= ich6_gpio_get
,
287 /* GPIO 0-15 are read in the GPE0_STS PM register */
293 /* ICH7 and ICH8-based */
294 static struct ichx_desc ich7_desc
= {
299 static struct ichx_desc ich9_desc
= {
303 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
304 static struct ichx_desc ich10_cons_desc
= {
307 static struct ichx_desc ich10_corp_desc
= {
311 /* Intel 5 series, 6 series, 3400 series, and C200 series */
312 static struct ichx_desc intel5_desc
= {
316 static int ichx_gpio_request_regions(struct resource
*res_base
,
317 const char *name
, u8 use_gpio
)
321 if (!res_base
|| !res_base
->start
|| !res_base
->end
)
324 for (i
= 0; i
< ARRAY_SIZE(ichx_regs
[0]); i
++) {
325 if (!(use_gpio
& (1 << i
)))
327 if (!request_region(res_base
->start
+ ichx_regs
[0][i
],
328 ichx_reglen
[i
], name
))
334 /* Clean up: release already requested regions, if any */
335 for (i
--; i
>= 0; i
--) {
336 if (!(use_gpio
& (1 << i
)))
338 release_region(res_base
->start
+ ichx_regs
[0][i
],
344 static void ichx_gpio_release_regions(struct resource
*res_base
, u8 use_gpio
)
348 for (i
= 0; i
< ARRAY_SIZE(ichx_regs
[0]); i
++) {
349 if (!(use_gpio
& (1 << i
)))
351 release_region(res_base
->start
+ ichx_regs
[0][i
],
356 static int ichx_gpio_probe(struct platform_device
*pdev
)
358 struct resource
*res_base
, *res_pm
;
360 struct lpc_ich_info
*ich_info
= pdev
->dev
.platform_data
;
365 ichx_priv
.dev
= pdev
;
367 switch (ich_info
->gpio_version
) {
369 ichx_priv
.desc
= &i3100_desc
;
372 ichx_priv
.desc
= &intel5_desc
;
375 ichx_priv
.desc
= &ich6_desc
;
378 ichx_priv
.desc
= &ich7_desc
;
381 ichx_priv
.desc
= &ich9_desc
;
383 case ICH_V10CORP_GPIO
:
384 ichx_priv
.desc
= &ich10_corp_desc
;
386 case ICH_V10CONS_GPIO
:
387 ichx_priv
.desc
= &ich10_cons_desc
;
393 res_base
= platform_get_resource(pdev
, IORESOURCE_IO
, ICH_RES_GPIO
);
394 ichx_priv
.use_gpio
= ich_info
->use_gpio
;
395 err
= ichx_gpio_request_regions(res_base
, pdev
->name
,
400 ichx_priv
.gpio_base
= res_base
;
403 * If necessary, determine the I/O address of ACPI/power management
404 * registers which are needed to read the the GPE0 register for GPI pins
405 * 0 - 15 on some chipsets.
407 if (!ichx_priv
.desc
->uses_gpe0
)
410 res_pm
= platform_get_resource(pdev
, IORESOURCE_IO
, ICH_RES_GPE0
);
412 pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
416 if (!request_region(res_pm
->start
, resource_size(res_pm
),
418 pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
422 ichx_priv
.pm_base
= res_pm
;
425 ichx_gpiolib_setup(&ichx_priv
.chip
);
426 err
= gpiochip_add(&ichx_priv
.chip
);
428 pr_err("Failed to register GPIOs\n");
432 pr_info("GPIO from %d to %d on %s\n", ichx_priv
.chip
.base
,
433 ichx_priv
.chip
.base
+ ichx_priv
.chip
.ngpio
- 1, DRV_NAME
);
438 ichx_gpio_release_regions(ichx_priv
.gpio_base
, ichx_priv
.use_gpio
);
439 if (ichx_priv
.pm_base
)
440 release_region(ichx_priv
.pm_base
->start
,
441 resource_size(ichx_priv
.pm_base
));
445 static int ichx_gpio_remove(struct platform_device
*pdev
)
449 err
= gpiochip_remove(&ichx_priv
.chip
);
451 dev_err(&pdev
->dev
, "%s failed, %d\n",
452 "gpiochip_remove()", err
);
456 ichx_gpio_release_regions(ichx_priv
.gpio_base
, ichx_priv
.use_gpio
);
457 if (ichx_priv
.pm_base
)
458 release_region(ichx_priv
.pm_base
->start
,
459 resource_size(ichx_priv
.pm_base
));
464 static struct platform_driver ichx_gpio_driver
= {
466 .owner
= THIS_MODULE
,
469 .probe
= ichx_gpio_probe
,
470 .remove
= ichx_gpio_remove
,
473 module_platform_driver(ichx_gpio_driver
);
475 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
476 MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
477 MODULE_LICENSE("GPL");
478 MODULE_ALIAS("platform:"DRV_NAME
);