drivers/gpio/gpio-intel-mid.c

   1 /*
   2  * Moorestown platform Langwell chip GPIO driver
   3  *
   4  * Copyright (c) 2008, 2009, 2013, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /* Supports:
  21  * Moorestown platform Langwell chip.
  22  * Medfield platform Penwell chip.
  23  * Clovertrail platform Cloverview chip.
  24  * Merrifield platform Tangier chip.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/kernel.h>
  31 #include <linux/delay.h>
  32 #include <linux/stddef.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/init.h>
  35 #include <linux/irq.h>
  36 #include <linux/io.h>
  37 #include <linux/gpio.h>
  38 #include <linux/slab.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/irqdomain.h>
  41
  42 #define INTEL_MID_IRQ_TYPE_EDGE         (1 << 0)
  43 #define INTEL_MID_IRQ_TYPE_LEVEL        (1 << 1)
  44
  45 /*
  46  * Langwell chip has 64 pins and thus there are 2 32bit registers to control
  47  * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
  48  * registers to control them, so we only define the order here instead of a
  49  * structure, to get a bit offset for a pin (use GPDR as an example):
  50  *
  51  * nreg = ngpio / 32;
  52  * reg = offset / 32;
  53  * bit = offset % 32;
  54  * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
  55  *
  56  * so the bit of reg_addr is to control pin offset's GPDR feature
  57 */
  58
  59 enum GPIO_REG {
  60         GPLR = 0,       /* pin level read-only */
  61         GPDR,           /* pin direction */
  62         GPSR,           /* pin set */
  63         GPCR,           /* pin clear */
  64         GRER,           /* rising edge detect */
  65         GFER,           /* falling edge detect */
  66         GEDR,           /* edge detect result */
  67         GAFR,           /* alt function */
  68 };
  69
  70 /* intel_mid gpio driver data */
  71 struct intel_mid_gpio_ddata {
  72         u16 ngpio;              /* number of gpio pins */
  73         u32 gplr_offset;        /* offset of first GPLR register from base */
  74         u32 flis_base;          /* base address of FLIS registers */
  75         u32 flis_len;           /* length of FLIS registers */
  76         u32 (*get_flis_offset)(int gpio);
  77         u32 chip_irq_type;      /* chip interrupt type */
  78 };
  79
  80 struct intel_mid_gpio {
  81         struct gpio_chip                chip;
  82         void __iomem                    *reg_base;
  83         spinlock_t                      lock;
  84         struct pci_dev                  *pdev;
  85         struct irq_domain               *domain;
  86 };
  87
  88 #define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
  89
  90 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
  91                               enum GPIO_REG reg_type)
  92 {
  93         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
  94         unsigned nreg = chip->ngpio / 32;
  95         u8 reg = offset / 32;
  96
  97         return priv->reg_base + reg_type * nreg * 4 + reg * 4;
  98 }
  99
 100 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
 101                                    enum GPIO_REG reg_type)
 102 {
 103         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
 104         unsigned nreg = chip->ngpio / 32;
 105         u8 reg = offset / 16;
 106
 107         return priv->reg_base + reg_type * nreg * 4 + reg * 4;
 108 }
 109
 110 static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
 111 {
 112         void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
 113         u32 value = readl(gafr);
 114         int shift = (offset % 16) << 1, af = (value >> shift) & 3;
 115
 116         if (af) {
 117                 value &= ~(3 << shift);
 118                 writel(value, gafr);
 119         }
 120         return 0;
 121 }
 122
 123 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 124 {
 125         void __iomem *gplr = gpio_reg(chip, offset, GPLR);
 126
 127         return readl(gplr) & BIT(offset % 32);
 128 }
 129
 130 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 131 {
 132         void __iomem *gpsr, *gpcr;
 133
 134         if (value) {
 135                 gpsr = gpio_reg(chip, offset, GPSR);
 136                 writel(BIT(offset % 32), gpsr);
 137         } else {
 138                 gpcr = gpio_reg(chip, offset, GPCR);
 139                 writel(BIT(offset % 32), gpcr);
 140         }
 141 }
 142
 143 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 144 {
 145         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
 146         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 147         u32 value;
 148         unsigned long flags;
 149
 150         if (priv->pdev)
 151                 pm_runtime_get(&priv->pdev->dev);
 152
 153         spin_lock_irqsave(&priv->lock, flags);
 154         value = readl(gpdr);
 155         value &= ~BIT(offset % 32);
 156         writel(value, gpdr);
 157         spin_unlock_irqrestore(&priv->lock, flags);
 158
 159         if (priv->pdev)
 160                 pm_runtime_put(&priv->pdev->dev);
 161
 162         return 0;
 163 }
 164
 165 static int intel_gpio_direction_output(struct gpio_chip *chip,
 166                         unsigned offset, int value)
 167 {
 168         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
 169         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 170         unsigned long flags;
 171
 172         intel_gpio_set(chip, offset, value);
 173
 174         if (priv->pdev)
 175                 pm_runtime_get(&priv->pdev->dev);
 176
 177         spin_lock_irqsave(&priv->lock, flags);
 178         value = readl(gpdr);
 179         value |= BIT(offset % 32);
 180         writel(value, gpdr);
 181         spin_unlock_irqrestore(&priv->lock, flags);
 182
 183         if (priv->pdev)
 184                 pm_runtime_put(&priv->pdev->dev);
 185
 186         return 0;
 187 }
 188
 189 static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 190 {
 191         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
 192         return irq_create_mapping(priv->domain, offset);
 193 }
 194
 195 static int intel_mid_irq_type(struct irq_data *d, unsigned type)
 196 {
 197         struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
 198         u32 gpio = irqd_to_hwirq(d);
 199         unsigned long flags;
 200         u32 value;
 201         void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
 202         void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
 203
 204         if (gpio >= priv->chip.ngpio)
 205                 return -EINVAL;
 206
 207         if (priv->pdev)
 208                 pm_runtime_get(&priv->pdev->dev);
 209
 210         spin_lock_irqsave(&priv->lock, flags);
 211         if (type & IRQ_TYPE_EDGE_RISING)
 212                 value = readl(grer) | BIT(gpio % 32);
 213         else
 214                 value = readl(grer) & (~BIT(gpio % 32));
 215         writel(value, grer);
 216
 217         if (type & IRQ_TYPE_EDGE_FALLING)
 218                 value = readl(gfer) | BIT(gpio % 32);
 219         else
 220                 value = readl(gfer) & (~BIT(gpio % 32));
 221         writel(value, gfer);
 222         spin_unlock_irqrestore(&priv->lock, flags);
 223
 224         if (priv->pdev)
 225                 pm_runtime_put(&priv->pdev->dev);
 226
 227         return 0;
 228 }
 229
 230 static void intel_mid_irq_unmask(struct irq_data *d)
 231 {
 232 }
 233
 234 static void intel_mid_irq_mask(struct irq_data *d)
 235 {
 236 }
 237
 238 static struct irq_chip intel_mid_irqchip = {
 239         .name           = "INTEL_MID-GPIO",
 240         .irq_mask       = intel_mid_irq_mask,
 241         .irq_unmask     = intel_mid_irq_unmask,
 242         .irq_set_type   = intel_mid_irq_type,
 243 };
 244
 245 static const struct intel_mid_gpio_ddata gpio_lincroft = {
 246         .ngpio = 64,
 247 };
 248
 249 static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
 250         .ngpio = 96,
 251         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
 252 };
 253
 254 static const struct intel_mid_gpio_ddata gpio_penwell_core = {
 255         .ngpio = 96,
 256         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
 257 };
 258
 259 static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
 260         .ngpio = 96,
 261         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
 262 };
 263
 264 static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
 265         .ngpio = 96,
 266         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
 267 };
 268
 269 static const struct intel_mid_gpio_ddata gpio_tangier = {
 270         .ngpio = 192,
 271         .gplr_offset = 4,
 272         .flis_base = 0xff0c0000,
 273         .flis_len = 0x8000,
 274         .get_flis_offset = NULL,
 275         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
 276 };
 277
 278 static DEFINE_PCI_DEVICE_TABLE(intel_gpio_ids) = {
 279         {
 280                 /* Lincroft */
 281                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
 282                 .driver_data = (kernel_ulong_t)&gpio_lincroft,
 283         },
 284         {
 285                 /* Penwell AON */
 286                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
 287                 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
 288         },
 289         {
 290                 /* Penwell Core */
 291                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
 292                 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
 293         },
 294         {
 295                 /* Cloverview Aon */
 296                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
 297                 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
 298         },
 299         {
 300                 /* Cloverview Core */
 301                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
 302                 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
 303         },
 304         {
 305                 /* Tangier */
 306                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
 307                 .driver_data = (kernel_ulong_t)&gpio_tangier,
 308         },
 309         { 0 }
 310 };
 311 MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
 312
 313 static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
 314 {
 315         struct irq_data *data = irq_desc_get_irq_data(desc);
 316         struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
 317         struct irq_chip *chip = irq_data_get_irq_chip(data);
 318         u32 base, gpio, mask;
 319         unsigned long pending;
 320         void __iomem *gedr;
 321
 322         /* check GPIO controller to check which pin triggered the interrupt */
 323         for (base = 0; base < priv->chip.ngpio; base += 32) {
 324                 gedr = gpio_reg(&priv->chip, base, GEDR);
 325                 while ((pending = readl(gedr))) {
 326                         gpio = __ffs(pending);
 327                         mask = BIT(gpio);
 328                         /* Clear before handling so we can't lose an edge */
 329                         writel(mask, gedr);
 330                         generic_handle_irq(irq_find_mapping(priv->domain,
 331                                                             base + gpio));
 332                 }
 333         }
 334
 335         chip->irq_eoi(data);
 336 }
 337
 338 static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
 339 {
 340         void __iomem *reg;
 341         unsigned base;
 342
 343         for (base = 0; base < priv->chip.ngpio; base += 32) {
 344                 /* Clear the rising-edge detect register */
 345                 reg = gpio_reg(&priv->chip, base, GRER);
 346                 writel(0, reg);
 347                 /* Clear the falling-edge detect register */
 348                 reg = gpio_reg(&priv->chip, base, GFER);
 349                 writel(0, reg);
 350                 /* Clear the edge detect status register */
 351                 reg = gpio_reg(&priv->chip, base, GEDR);
 352                 writel(~0, reg);
 353         }
 354 }
 355
 356 static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 357                             irq_hw_number_t hwirq)
 358 {
 359         struct intel_mid_gpio *priv = d->host_data;
 360
 361         irq_set_chip_and_handler_name(irq, &intel_mid_irqchip,
 362                                       handle_simple_irq, "demux");
 363         irq_set_chip_data(irq, priv);
 364         irq_set_irq_type(irq, IRQ_TYPE_NONE);
 365
 366         return 0;
 367 }
 368
 369 static const struct irq_domain_ops intel_gpio_irq_ops = {
 370         .map = intel_gpio_irq_map,
 371         .xlate = irq_domain_xlate_twocell,
 372 };
 373
 374 static int intel_gpio_runtime_idle(struct device *dev)
 375 {
 376         pm_schedule_suspend(dev, 500);
 377         return -EBUSY;
 378 }
 379
 380 static const struct dev_pm_ops intel_gpio_pm_ops = {
 381         SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
 382 };
 383
 384 static int intel_gpio_probe(struct pci_dev *pdev,
 385                           const struct pci_device_id *id)
 386 {
 387         void __iomem *base;
 388         struct intel_mid_gpio *priv;
 389         u32 gpio_base;
 390         u32 irq_base;
 391         int retval;
 392         struct intel_mid_gpio_ddata *ddata =
 393                                 (struct intel_mid_gpio_ddata *)id->driver_data;
 394
 395         retval = pcim_enable_device(pdev);
 396         if (retval)
 397                 return retval;
 398
 399         retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
 400         if (retval) {
 401                 dev_err(&pdev->dev, "I/O memory mapping error\n");
 402                 return retval;
 403         }
 404
 405         base = pcim_iomap_table(pdev)[1];
 406
 407         irq_base = readl(base);
 408         gpio_base = readl(sizeof(u32) + base);
 409
 410         /* release the IO mapping, since we already get the info from bar1 */
 411         pcim_iounmap_regions(pdev, 1 << 1);
 412
 413         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 414         if (!priv) {
 415                 dev_err(&pdev->dev, "can't allocate chip data\n");
 416                 return -ENOMEM;
 417         }
 418
 419         priv->reg_base = pcim_iomap_table(pdev)[0];
 420         priv->chip.label = dev_name(&pdev->dev);
 421         priv->chip.request = intel_gpio_request;
 422         priv->chip.direction_input = intel_gpio_direction_input;
 423         priv->chip.direction_output = intel_gpio_direction_output;
 424         priv->chip.get = intel_gpio_get;
 425         priv->chip.set = intel_gpio_set;
 426         priv->chip.to_irq = intel_gpio_to_irq;
 427         priv->chip.base = gpio_base;
 428         priv->chip.ngpio = ddata->ngpio;
 429         priv->chip.can_sleep = 0;
 430         priv->pdev = pdev;
 431
 432         spin_lock_init(&priv->lock);
 433
 434         priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
 435                                         irq_base, &intel_gpio_irq_ops, priv);
 436         if (!priv->domain)
 437                 return -ENOMEM;
 438
 439         pci_set_drvdata(pdev, priv);
 440         retval = gpiochip_add(&priv->chip);
 441         if (retval) {
 442                 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
 443                 return retval;
 444         }
 445
 446         intel_mid_irq_init_hw(priv);
 447
 448         irq_set_handler_data(pdev->irq, priv);
 449         irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
 450
 451         pm_runtime_put_noidle(&pdev->dev);
 452         pm_runtime_allow(&pdev->dev);
 453
 454         return 0;
 455 }
 456
 457 static struct pci_driver intel_gpio_driver = {
 458         .name           = "intel_mid_gpio",
 459         .id_table       = intel_gpio_ids,
 460         .probe          = intel_gpio_probe,
 461         .driver         = {
 462                 .pm     = &intel_gpio_pm_ops,
 463         },
 464 };
 465
 466 static int __init intel_gpio_init(void)
 467 {
 468         return pci_register_driver(&intel_gpio_driver);
 469 }
 470
 471 device_initcall(intel_gpio_init);