2 * Moorestown platform Langwell chip GPIO driver
4 * Copyright (c) 2008, 2009, 2013, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * Moorestown platform Langwell chip.
22 * Medfield platform Penwell chip.
23 * Clovertrail platform Cloverview chip.
24 * Merrifield platform Tangier chip.
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/platform_device.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/stddef.h>
33 #include <linux/interrupt.h>
34 #include <linux/init.h>
35 #include <linux/irq.h>
37 #include <linux/gpio.h>
38 #include <linux/slab.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/irqdomain.h>
42 #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
43 #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
46 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
47 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
48 * registers to control them, so we only define the order here instead of a
49 * structure, to get a bit offset for a pin (use GPDR as an example):
54 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
56 * so the bit of reg_addr is to control pin offset's GPDR feature
60 GPLR
= 0, /* pin level read-only */
61 GPDR
, /* pin direction */
64 GRER
, /* rising edge detect */
65 GFER
, /* falling edge detect */
66 GEDR
, /* edge detect result */
67 GAFR
, /* alt function */
70 /* intel_mid gpio driver data */
71 struct intel_mid_gpio_ddata
{
72 u16 ngpio
; /* number of gpio pins */
73 u32 gplr_offset
; /* offset of first GPLR register from base */
74 u32 flis_base
; /* base address of FLIS registers */
75 u32 flis_len
; /* length of FLIS registers */
76 u32 (*get_flis_offset
)(int gpio
);
77 u32 chip_irq_type
; /* chip interrupt type */
80 struct intel_mid_gpio
{
81 struct gpio_chip chip
;
82 void __iomem
*reg_base
;
85 struct irq_domain
*domain
;
88 #define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
90 static void __iomem
*gpio_reg(struct gpio_chip
*chip
, unsigned offset
,
91 enum GPIO_REG reg_type
)
93 struct intel_mid_gpio
*priv
= to_intel_gpio_priv(chip
);
94 unsigned nreg
= chip
->ngpio
/ 32;
97 return priv
->reg_base
+ reg_type
* nreg
* 4 + reg
* 4;
100 static void __iomem
*gpio_reg_2bit(struct gpio_chip
*chip
, unsigned offset
,
101 enum GPIO_REG reg_type
)
103 struct intel_mid_gpio
*priv
= to_intel_gpio_priv(chip
);
104 unsigned nreg
= chip
->ngpio
/ 32;
105 u8 reg
= offset
/ 16;
107 return priv
->reg_base
+ reg_type
* nreg
* 4 + reg
* 4;
110 static int intel_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
112 void __iomem
*gafr
= gpio_reg_2bit(chip
, offset
, GAFR
);
113 u32 value
= readl(gafr
);
114 int shift
= (offset
% 16) << 1, af
= (value
>> shift
) & 3;
117 value
&= ~(3 << shift
);
123 static int intel_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
125 void __iomem
*gplr
= gpio_reg(chip
, offset
, GPLR
);
127 return readl(gplr
) & BIT(offset
% 32);
130 static void intel_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
132 void __iomem
*gpsr
, *gpcr
;
135 gpsr
= gpio_reg(chip
, offset
, GPSR
);
136 writel(BIT(offset
% 32), gpsr
);
138 gpcr
= gpio_reg(chip
, offset
, GPCR
);
139 writel(BIT(offset
% 32), gpcr
);
143 static int intel_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
145 struct intel_mid_gpio
*priv
= to_intel_gpio_priv(chip
);
146 void __iomem
*gpdr
= gpio_reg(chip
, offset
, GPDR
);
151 pm_runtime_get(&priv
->pdev
->dev
);
153 spin_lock_irqsave(&priv
->lock
, flags
);
155 value
&= ~BIT(offset
% 32);
157 spin_unlock_irqrestore(&priv
->lock
, flags
);
160 pm_runtime_put(&priv
->pdev
->dev
);
165 static int intel_gpio_direction_output(struct gpio_chip
*chip
,
166 unsigned offset
, int value
)
168 struct intel_mid_gpio
*priv
= to_intel_gpio_priv(chip
);
169 void __iomem
*gpdr
= gpio_reg(chip
, offset
, GPDR
);
172 intel_gpio_set(chip
, offset
, value
);
175 pm_runtime_get(&priv
->pdev
->dev
);
177 spin_lock_irqsave(&priv
->lock
, flags
);
179 value
|= BIT(offset
% 32);
181 spin_unlock_irqrestore(&priv
->lock
, flags
);
184 pm_runtime_put(&priv
->pdev
->dev
);
189 static int intel_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
191 struct intel_mid_gpio
*priv
= to_intel_gpio_priv(chip
);
192 return irq_create_mapping(priv
->domain
, offset
);
195 static int intel_mid_irq_type(struct irq_data
*d
, unsigned type
)
197 struct intel_mid_gpio
*priv
= irq_data_get_irq_chip_data(d
);
198 u32 gpio
= irqd_to_hwirq(d
);
201 void __iomem
*grer
= gpio_reg(&priv
->chip
, gpio
, GRER
);
202 void __iomem
*gfer
= gpio_reg(&priv
->chip
, gpio
, GFER
);
204 if (gpio
>= priv
->chip
.ngpio
)
208 pm_runtime_get(&priv
->pdev
->dev
);
210 spin_lock_irqsave(&priv
->lock
, flags
);
211 if (type
& IRQ_TYPE_EDGE_RISING
)
212 value
= readl(grer
) | BIT(gpio
% 32);
214 value
= readl(grer
) & (~BIT(gpio
% 32));
217 if (type
& IRQ_TYPE_EDGE_FALLING
)
218 value
= readl(gfer
) | BIT(gpio
% 32);
220 value
= readl(gfer
) & (~BIT(gpio
% 32));
222 spin_unlock_irqrestore(&priv
->lock
, flags
);
225 pm_runtime_put(&priv
->pdev
->dev
);
230 static void intel_mid_irq_unmask(struct irq_data
*d
)
234 static void intel_mid_irq_mask(struct irq_data
*d
)
238 static struct irq_chip intel_mid_irqchip
= {
239 .name
= "INTEL_MID-GPIO",
240 .irq_mask
= intel_mid_irq_mask
,
241 .irq_unmask
= intel_mid_irq_unmask
,
242 .irq_set_type
= intel_mid_irq_type
,
245 static const struct intel_mid_gpio_ddata gpio_lincroft
= {
249 static const struct intel_mid_gpio_ddata gpio_penwell_aon
= {
251 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
,
254 static const struct intel_mid_gpio_ddata gpio_penwell_core
= {
256 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
,
259 static const struct intel_mid_gpio_ddata gpio_cloverview_aon
= {
261 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
| INTEL_MID_IRQ_TYPE_LEVEL
,
264 static const struct intel_mid_gpio_ddata gpio_cloverview_core
= {
266 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
,
269 static const struct intel_mid_gpio_ddata gpio_tangier
= {
272 .flis_base
= 0xff0c0000,
274 .get_flis_offset
= NULL
,
275 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
,
278 static const struct pci_device_id intel_gpio_ids
[] = {
281 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x080f),
282 .driver_data
= (kernel_ulong_t
)&gpio_lincroft
,
286 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081f),
287 .driver_data
= (kernel_ulong_t
)&gpio_penwell_aon
,
291 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081a),
292 .driver_data
= (kernel_ulong_t
)&gpio_penwell_core
,
296 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x08eb),
297 .driver_data
= (kernel_ulong_t
)&gpio_cloverview_aon
,
300 /* Cloverview Core */
301 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x08f7),
302 .driver_data
= (kernel_ulong_t
)&gpio_cloverview_core
,
306 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x1199),
307 .driver_data
= (kernel_ulong_t
)&gpio_tangier
,
311 MODULE_DEVICE_TABLE(pci
, intel_gpio_ids
);
313 static void intel_mid_irq_handler(unsigned irq
, struct irq_desc
*desc
)
315 struct irq_data
*data
= irq_desc_get_irq_data(desc
);
316 struct intel_mid_gpio
*priv
= irq_data_get_irq_handler_data(data
);
317 struct irq_chip
*chip
= irq_data_get_irq_chip(data
);
318 u32 base
, gpio
, mask
;
319 unsigned long pending
;
322 /* check GPIO controller to check which pin triggered the interrupt */
323 for (base
= 0; base
< priv
->chip
.ngpio
; base
+= 32) {
324 gedr
= gpio_reg(&priv
->chip
, base
, GEDR
);
325 while ((pending
= readl(gedr
))) {
326 gpio
= __ffs(pending
);
328 /* Clear before handling so we can't lose an edge */
330 generic_handle_irq(irq_find_mapping(priv
->domain
,
338 static void intel_mid_irq_init_hw(struct intel_mid_gpio
*priv
)
343 for (base
= 0; base
< priv
->chip
.ngpio
; base
+= 32) {
344 /* Clear the rising-edge detect register */
345 reg
= gpio_reg(&priv
->chip
, base
, GRER
);
347 /* Clear the falling-edge detect register */
348 reg
= gpio_reg(&priv
->chip
, base
, GFER
);
350 /* Clear the edge detect status register */
351 reg
= gpio_reg(&priv
->chip
, base
, GEDR
);
356 static int intel_gpio_irq_map(struct irq_domain
*d
, unsigned int irq
,
357 irq_hw_number_t hwirq
)
359 struct intel_mid_gpio
*priv
= d
->host_data
;
361 irq_set_chip_and_handler(irq
, &intel_mid_irqchip
, handle_simple_irq
);
362 irq_set_chip_data(irq
, priv
);
363 irq_set_irq_type(irq
, IRQ_TYPE_NONE
);
368 static const struct irq_domain_ops intel_gpio_irq_ops
= {
369 .map
= intel_gpio_irq_map
,
370 .xlate
= irq_domain_xlate_twocell
,
373 static int intel_gpio_runtime_idle(struct device
*dev
)
375 pm_schedule_suspend(dev
, 500);
379 static const struct dev_pm_ops intel_gpio_pm_ops
= {
380 SET_RUNTIME_PM_OPS(NULL
, NULL
, intel_gpio_runtime_idle
)
383 static int intel_gpio_probe(struct pci_dev
*pdev
,
384 const struct pci_device_id
*id
)
387 struct intel_mid_gpio
*priv
;
391 struct intel_mid_gpio_ddata
*ddata
=
392 (struct intel_mid_gpio_ddata
*)id
->driver_data
;
394 retval
= pcim_enable_device(pdev
);
398 retval
= pcim_iomap_regions(pdev
, 1 << 0 | 1 << 1, pci_name(pdev
));
400 dev_err(&pdev
->dev
, "I/O memory mapping error\n");
404 base
= pcim_iomap_table(pdev
)[1];
406 irq_base
= readl(base
);
407 gpio_base
= readl(sizeof(u32
) + base
);
409 /* release the IO mapping, since we already get the info from bar1 */
410 pcim_iounmap_regions(pdev
, 1 << 1);
412 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
414 dev_err(&pdev
->dev
, "can't allocate chip data\n");
418 priv
->reg_base
= pcim_iomap_table(pdev
)[0];
419 priv
->chip
.label
= dev_name(&pdev
->dev
);
420 priv
->chip
.request
= intel_gpio_request
;
421 priv
->chip
.direction_input
= intel_gpio_direction_input
;
422 priv
->chip
.direction_output
= intel_gpio_direction_output
;
423 priv
->chip
.get
= intel_gpio_get
;
424 priv
->chip
.set
= intel_gpio_set
;
425 priv
->chip
.to_irq
= intel_gpio_to_irq
;
426 priv
->chip
.base
= gpio_base
;
427 priv
->chip
.ngpio
= ddata
->ngpio
;
428 priv
->chip
.can_sleep
= false;
431 spin_lock_init(&priv
->lock
);
433 priv
->domain
= irq_domain_add_simple(pdev
->dev
.of_node
, ddata
->ngpio
,
434 irq_base
, &intel_gpio_irq_ops
, priv
);
438 pci_set_drvdata(pdev
, priv
);
439 retval
= gpiochip_add(&priv
->chip
);
441 dev_err(&pdev
->dev
, "gpiochip_add error %d\n", retval
);
445 intel_mid_irq_init_hw(priv
);
447 irq_set_handler_data(pdev
->irq
, priv
);
448 irq_set_chained_handler(pdev
->irq
, intel_mid_irq_handler
);
450 pm_runtime_put_noidle(&pdev
->dev
);
451 pm_runtime_allow(&pdev
->dev
);
456 static struct pci_driver intel_gpio_driver
= {
457 .name
= "intel_mid_gpio",
458 .id_table
= intel_gpio_ids
,
459 .probe
= intel_gpio_probe
,
461 .pm
= &intel_gpio_pm_ops
,
465 static int __init
intel_gpio_init(void)
467 return pci_register_driver(&intel_gpio_driver
);
470 device_initcall(intel_gpio_init
);