drivers/gpio/gpio-mpc8xxx.c

   1 /*
   2  * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
   3  *
   4  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
   5  * Copyright (C) 2016 Freescale Semiconductor Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <linux/acpi.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/property.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/slab.h>
  25 #include <linux/irq.h>
  26 #include <linux/gpio/driver.h>
  27 #include <linux/bitops.h>
  28 #include <linux/interrupt.h>
  29
  30 #define MPC8XXX_GPIO_PINS       32
  31
  32 #define GPIO_DIR                0x00
  33 #define GPIO_ODR                0x04
  34 #define GPIO_DAT                0x08
  35 #define GPIO_IER                0x0c
  36 #define GPIO_IMR                0x10
  37 #define GPIO_ICR                0x14
  38 #define GPIO_ICR2               0x18
  39 #define GPIO_IBE                0x18
  40
  41 struct mpc8xxx_gpio_chip {
  42         struct gpio_chip        gc;
  43         void __iomem *regs;
  44         raw_spinlock_t lock;
  45
  46         int (*direction_output)(struct gpio_chip *chip,
  47                                 unsigned offset, int value);
  48
  49         struct irq_domain *irq;
  50         unsigned int irqn;
  51 };
  52
  53 /*
  54  * This hardware has a big endian bit assignment such that GPIO line 0 is
  55  * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
  56  * This inline helper give the right bitmask for a certain line.
  57  */
  58 static inline u32 mpc_pin2mask(unsigned int offset)
  59 {
  60         return BIT(31 - offset);
  61 }
  62
  63 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
  64  * defined as output cannot be determined by reading GPDAT register,
  65  * so we use shadow data register instead. The status of input pins
  66  * is determined by reading GPDAT register.
  67  */
  68 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  69 {
  70         u32 val;
  71         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  72         u32 out_mask, out_shadow;
  73
  74         out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
  75         val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
  76         out_shadow = gc->bgpio_data & out_mask;
  77
  78         return !!((val | out_shadow) & mpc_pin2mask(gpio));
  79 }
  80
  81 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
  82                                 unsigned int gpio, int val)
  83 {
  84         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  85         /* GPIO 28..31 are input only on MPC5121 */
  86         if (gpio >= 28)
  87                 return -EINVAL;
  88
  89         return mpc8xxx_gc->direction_output(gc, gpio, val);
  90 }
  91
  92 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
  93                                 unsigned int gpio, int val)
  94 {
  95         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  96         /* GPIO 0..3 are input only on MPC5125 */
  97         if (gpio <= 3)
  98                 return -EINVAL;
  99
 100         return mpc8xxx_gc->direction_output(gc, gpio, val);
 101 }
 102
 103 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 104 {
 105         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 106
 107         if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
 108                 return irq_create_mapping(mpc8xxx_gc->irq, offset);
 109         else
 110                 return -ENXIO;
 111 }
 112
 113 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
 114 {
 115         struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
 116         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 117         unsigned long mask;
 118         int i;
 119
 120         mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
 121                 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
 122         for_each_set_bit(i, &mask, 32)
 123                 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
 124
 125         return IRQ_HANDLED;
 126 }
 127
 128 static void mpc8xxx_irq_unmask(struct irq_data *d)
 129 {
 130         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 131         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 132         unsigned long flags;
 133
 134         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 135
 136         gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
 137                 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
 138                 | mpc_pin2mask(irqd_to_hwirq(d)));
 139
 140         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 141 }
 142
 143 static void mpc8xxx_irq_mask(struct irq_data *d)
 144 {
 145         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 146         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 147         unsigned long flags;
 148
 149         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 150
 151         gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
 152                 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
 153                 & ~mpc_pin2mask(irqd_to_hwirq(d)));
 154
 155         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 156 }
 157
 158 static void mpc8xxx_irq_ack(struct irq_data *d)
 159 {
 160         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 161         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 162
 163         gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
 164                       mpc_pin2mask(irqd_to_hwirq(d)));
 165 }
 166
 167 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
 168 {
 169         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 170         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 171         unsigned long flags;
 172
 173         switch (flow_type) {
 174         case IRQ_TYPE_EDGE_FALLING:
 175                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 176                 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
 177                         gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
 178                         | mpc_pin2mask(irqd_to_hwirq(d)));
 179                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 180                 break;
 181
 182         case IRQ_TYPE_EDGE_BOTH:
 183                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 184                 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
 185                         gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
 186                         & ~mpc_pin2mask(irqd_to_hwirq(d)));
 187                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 188                 break;
 189
 190         default:
 191                 return -EINVAL;
 192         }
 193
 194         return 0;
 195 }
 196
 197 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
 198 {
 199         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 200         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 201         unsigned long gpio = irqd_to_hwirq(d);
 202         void __iomem *reg;
 203         unsigned int shift;
 204         unsigned long flags;
 205
 206         if (gpio < 16) {
 207                 reg = mpc8xxx_gc->regs + GPIO_ICR;
 208                 shift = (15 - gpio) * 2;
 209         } else {
 210                 reg = mpc8xxx_gc->regs + GPIO_ICR2;
 211                 shift = (15 - (gpio % 16)) * 2;
 212         }
 213
 214         switch (flow_type) {
 215         case IRQ_TYPE_EDGE_FALLING:
 216         case IRQ_TYPE_LEVEL_LOW:
 217                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 218                 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
 219                         | (2 << shift));
 220                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 221                 break;
 222
 223         case IRQ_TYPE_EDGE_RISING:
 224         case IRQ_TYPE_LEVEL_HIGH:
 225                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 226                 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
 227                         | (1 << shift));
 228                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 229                 break;
 230
 231         case IRQ_TYPE_EDGE_BOTH:
 232                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 233                 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
 234                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 235                 break;
 236
 237         default:
 238                 return -EINVAL;
 239         }
 240
 241         return 0;
 242 }
 243
 244 static struct irq_chip mpc8xxx_irq_chip = {
 245         .name           = "mpc8xxx-gpio",
 246         .irq_unmask     = mpc8xxx_irq_unmask,
 247         .irq_mask       = mpc8xxx_irq_mask,
 248         .irq_ack        = mpc8xxx_irq_ack,
 249         /* this might get overwritten in mpc8xxx_probe() */
 250         .irq_set_type   = mpc8xxx_irq_set_type,
 251 };
 252
 253 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
 254                                 irq_hw_number_t hwirq)
 255 {
 256         irq_set_chip_data(irq, h->host_data);
 257         irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
 258
 259         return 0;
 260 }
 261
 262 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
 263         .map    = mpc8xxx_gpio_irq_map,
 264         .xlate  = irq_domain_xlate_twocell,
 265 };
 266
 267 struct mpc8xxx_gpio_devtype {
 268         int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
 269         int (*gpio_get)(struct gpio_chip *, unsigned int);
 270         int (*irq_set_type)(struct irq_data *, unsigned int);
 271 };
 272
 273 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
 274         .gpio_dir_out = mpc5121_gpio_dir_out,
 275         .irq_set_type = mpc512x_irq_set_type,
 276 };
 277
 278 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
 279         .gpio_dir_out = mpc5125_gpio_dir_out,
 280         .irq_set_type = mpc512x_irq_set_type,
 281 };
 282
 283 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
 284         .gpio_get = mpc8572_gpio_get,
 285 };
 286
 287 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
 288         .irq_set_type = mpc8xxx_irq_set_type,
 289 };
 290
 291 static const struct of_device_id mpc8xxx_gpio_ids[] = {
 292         { .compatible = "fsl,mpc8349-gpio", },
 293         { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
 294         { .compatible = "fsl,mpc8610-gpio", },
 295         { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
 296         { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
 297         { .compatible = "fsl,pq3-gpio",     },
 298         { .compatible = "fsl,ls1028a-gpio", },
 299         { .compatible = "fsl,ls1088a-gpio", },
 300         { .compatible = "fsl,qoriq-gpio",   },
 301         {}
 302 };
 303
 304 static int mpc8xxx_probe(struct platform_device *pdev)
 305 {
 306         struct device_node *np = pdev->dev.of_node;
 307         struct mpc8xxx_gpio_chip *mpc8xxx_gc;
 308         struct gpio_chip        *gc;
 309         const struct mpc8xxx_gpio_devtype *devtype = NULL;
 310         struct fwnode_handle *fwnode;
 311         int ret;
 312
 313         mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
 314         if (!mpc8xxx_gc)
 315                 return -ENOMEM;
 316
 317         platform_set_drvdata(pdev, mpc8xxx_gc);
 318
 319         raw_spin_lock_init(&mpc8xxx_gc->lock);
 320
 321         mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
 322         if (IS_ERR(mpc8xxx_gc->regs))
 323                 return PTR_ERR(mpc8xxx_gc->regs);
 324
 325         gc = &mpc8xxx_gc->gc;
 326         gc->parent = &pdev->dev;
 327
 328         if (device_property_read_bool(&pdev->dev, "little-endian")) {
 329                 ret = bgpio_init(gc, &pdev->dev, 4,
 330                                  mpc8xxx_gc->regs + GPIO_DAT,
 331                                  NULL, NULL,
 332                                  mpc8xxx_gc->regs + GPIO_DIR, NULL,
 333                                  BGPIOF_BIG_ENDIAN);
 334                 if (ret)
 335                         goto err;
 336                 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
 337         } else {
 338                 ret = bgpio_init(gc, &pdev->dev, 4,
 339                                  mpc8xxx_gc->regs + GPIO_DAT,
 340                                  NULL, NULL,
 341                                  mpc8xxx_gc->regs + GPIO_DIR, NULL,
 342                                  BGPIOF_BIG_ENDIAN
 343                                  | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
 344                 if (ret)
 345                         goto err;
 346                 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
 347         }
 348
 349         mpc8xxx_gc->direction_output = gc->direction_output;
 350
 351         devtype = device_get_match_data(&pdev->dev);
 352         if (!devtype)
 353                 devtype = &mpc8xxx_gpio_devtype_default;
 354
 355         /*
 356          * It's assumed that only a single type of gpio controller is available
 357          * on the current machine, so overwriting global data is fine.
 358          */
 359         if (devtype->irq_set_type)
 360                 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
 361
 362         if (devtype->gpio_dir_out)
 363                 gc->direction_output = devtype->gpio_dir_out;
 364         if (devtype->gpio_get)
 365                 gc->get = devtype->gpio_get;
 366
 367         gc->to_irq = mpc8xxx_gpio_to_irq;
 368
 369         /*
 370          * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
 371          * the input enable of each individual GPIO port.  When an individual
 372          * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
 373          * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
 374          * the port value to the GPIO Data Register.
 375          */
 376         fwnode = dev_fwnode(&pdev->dev);
 377         if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
 378             of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
 379             of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
 380             is_acpi_node(fwnode))
 381                 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
 382
 383         ret = gpiochip_add_data(gc, mpc8xxx_gc);
 384         if (ret) {
 385                 dev_err(&pdev->dev,
 386                         "GPIO chip registration failed with status %d\n", ret);
 387                 goto err;
 388         }
 389
 390         mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
 391         if (!mpc8xxx_gc->irqn)
 392                 return 0;
 393
 394         mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
 395                                                    MPC8XXX_GPIO_PINS,
 396                                                    &mpc8xxx_gpio_irq_ops,
 397                                                    mpc8xxx_gc);
 398
 399         if (!mpc8xxx_gc->irq)
 400                 return 0;
 401
 402         /* ack and mask all irqs */
 403         gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
 404         gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
 405
 406         ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
 407                                mpc8xxx_gpio_irq_cascade,
 408                                IRQF_SHARED, "gpio-cascade",
 409                                mpc8xxx_gc);
 410         if (ret) {
 411                 dev_err(&pdev->dev,
 412                         "failed to devm_request_irq(%d), ret = %d\n",
 413                         mpc8xxx_gc->irqn, ret);
 414                 goto err;
 415         }
 416
 417         return 0;
 418 err:
 419         iounmap(mpc8xxx_gc->regs);
 420         return ret;
 421 }
 422
 423 static int mpc8xxx_remove(struct platform_device *pdev)
 424 {
 425         struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
 426
 427         if (mpc8xxx_gc->irq) {
 428                 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
 429                 irq_domain_remove(mpc8xxx_gc->irq);
 430         }
 431
 432         gpiochip_remove(&mpc8xxx_gc->gc);
 433         iounmap(mpc8xxx_gc->regs);
 434
 435         return 0;
 436 }
 437
 438 #ifdef CONFIG_ACPI
 439 static const struct acpi_device_id gpio_acpi_ids[] = {
 440         {"NXP0031",},
 441         { }
 442 };
 443 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
 444 #endif
 445
 446 static struct platform_driver mpc8xxx_plat_driver = {
 447         .probe          = mpc8xxx_probe,
 448         .remove         = mpc8xxx_remove,
 449         .driver         = {
 450                 .name = "gpio-mpc8xxx",
 451                 .of_match_table = mpc8xxx_gpio_ids,
 452                 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
 453         },
 454 };
 455
 456 static int __init mpc8xxx_init(void)
 457 {
 458         return platform_driver_register(&mpc8xxx_plat_driver);
 459 }
 460
 461 arch_initcall(mpc8xxx_init);