drivers/gpio/gpio-mpc8xxx.c

   1 /*
   2  * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
   3  *
   4  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
   5  * Copyright (C) 2016 Freescale Semiconductor Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/slab.h>
  22 #include <linux/irq.h>
  23 #include <linux/gpio/driver.h>
  24
  25 #define MPC8XXX_GPIO_PINS       32
  26
  27 #define GPIO_DIR                0x00
  28 #define GPIO_ODR                0x04
  29 #define GPIO_DAT                0x08
  30 #define GPIO_IER                0x0c
  31 #define GPIO_IMR                0x10
  32 #define GPIO_ICR                0x14
  33 #define GPIO_ICR2               0x18
  34
  35 struct mpc8xxx_gpio_chip {
  36         struct gpio_chip        gc;
  37         void __iomem *regs;
  38         raw_spinlock_t lock;
  39
  40         unsigned long (*read_reg)(void __iomem *reg);
  41         void (*write_reg)(void __iomem *reg, unsigned long data);
  42
  43         int (*direction_output)(struct gpio_chip *chip,
  44                                 unsigned offset, int value);
  45
  46         struct irq_domain *irq;
  47         unsigned int irqn;
  48 };
  49
  50 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
  51  * defined as output cannot be determined by reading GPDAT register,
  52  * so we use shadow data register instead. The status of input pins
  53  * is determined by reading GPDAT register.
  54  */
  55 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  56 {
  57         u32 val;
  58         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  59         u32 out_mask, out_shadow;
  60
  61         out_mask = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
  62         val = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
  63         out_shadow = gc->bgpio_data & out_mask;
  64
  65         return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
  66 }
  67
  68 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
  69                                 unsigned int gpio, int val)
  70 {
  71         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  72         /* GPIO 28..31 are input only on MPC5121 */
  73         if (gpio >= 28)
  74                 return -EINVAL;
  75
  76         return mpc8xxx_gc->direction_output(gc, gpio, val);
  77 }
  78
  79 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
  80                                 unsigned int gpio, int val)
  81 {
  82         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  83         /* GPIO 0..3 are input only on MPC5125 */
  84         if (gpio <= 3)
  85                 return -EINVAL;
  86
  87         return mpc8xxx_gc->direction_output(gc, gpio, val);
  88 }
  89
  90 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  91 {
  92         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  93
  94         if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
  95                 return irq_create_mapping(mpc8xxx_gc->irq, offset);
  96         else
  97                 return -ENXIO;
  98 }
  99
 100 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
 101 {
 102         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
 103         struct irq_chip *chip = irq_desc_get_chip(desc);
 104         unsigned int mask;
 105
 106         mask = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
 107                 & mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
 108         if (mask)
 109                 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
 110                                                      32 - ffs(mask)));
 111         if (chip->irq_eoi)
 112                 chip->irq_eoi(&desc->irq_data);
 113 }
 114
 115 static void mpc8xxx_irq_unmask(struct irq_data *d)
 116 {
 117         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 118         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 119         unsigned long flags;
 120
 121         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 122
 123         mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
 124                 mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
 125                 | gc->pin2mask(gc, irqd_to_hwirq(d)));
 126
 127         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 128 }
 129
 130 static void mpc8xxx_irq_mask(struct irq_data *d)
 131 {
 132         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 133         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 134         unsigned long flags;
 135
 136         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 137
 138         mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
 139                 mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
 140                 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
 141
 142         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 143 }
 144
 145 static void mpc8xxx_irq_ack(struct irq_data *d)
 146 {
 147         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 148         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 149
 150         mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
 151                 gc->pin2mask(gc, irqd_to_hwirq(d)));
 152 }
 153
 154 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
 155 {
 156         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 157         struct gpio_chip *gc = &mpc8xxx_gc->gc;
 158         unsigned long flags;
 159
 160         switch (flow_type) {
 161         case IRQ_TYPE_EDGE_FALLING:
 162                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 163                 mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
 164                         mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
 165                         | gc->pin2mask(gc, irqd_to_hwirq(d)));
 166                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 167                 break;
 168
 169         case IRQ_TYPE_EDGE_BOTH:
 170                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 171                 mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
 172                         mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
 173                         & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
 174                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 175                 break;
 176
 177         default:
 178                 return -EINVAL;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
 185 {
 186         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 187         unsigned long gpio = irqd_to_hwirq(d);
 188         void __iomem *reg;
 189         unsigned int shift;
 190         unsigned long flags;
 191
 192         if (gpio < 16) {
 193                 reg = mpc8xxx_gc->regs + GPIO_ICR;
 194                 shift = (15 - gpio) * 2;
 195         } else {
 196                 reg = mpc8xxx_gc->regs + GPIO_ICR2;
 197                 shift = (15 - (gpio % 16)) * 2;
 198         }
 199
 200         switch (flow_type) {
 201         case IRQ_TYPE_EDGE_FALLING:
 202         case IRQ_TYPE_LEVEL_LOW:
 203                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 204                 mpc8xxx_gc->write_reg(reg,
 205                         (mpc8xxx_gc->read_reg(reg) & ~(3 << shift))
 206                         | (2 << shift));
 207                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 208                 break;
 209
 210         case IRQ_TYPE_EDGE_RISING:
 211         case IRQ_TYPE_LEVEL_HIGH:
 212                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 213                 mpc8xxx_gc->write_reg(reg,
 214                         (mpc8xxx_gc->read_reg(reg) & ~(3 << shift))
 215                         | (1 << shift));
 216                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 217                 break;
 218
 219         case IRQ_TYPE_EDGE_BOTH:
 220                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 221                 mpc8xxx_gc->write_reg(reg,
 222                         (mpc8xxx_gc->read_reg(reg) & ~(3 << shift)));
 223                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 224                 break;
 225
 226         default:
 227                 return -EINVAL;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static struct irq_chip mpc8xxx_irq_chip = {
 234         .name           = "mpc8xxx-gpio",
 235         .irq_unmask     = mpc8xxx_irq_unmask,
 236         .irq_mask       = mpc8xxx_irq_mask,
 237         .irq_ack        = mpc8xxx_irq_ack,
 238         /* this might get overwritten in mpc8xxx_probe() */
 239         .irq_set_type   = mpc8xxx_irq_set_type,
 240 };
 241
 242 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
 243                                 irq_hw_number_t hwirq)
 244 {
 245         irq_set_chip_data(irq, h->host_data);
 246         irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
 247
 248         return 0;
 249 }
 250
 251 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
 252         .map    = mpc8xxx_gpio_irq_map,
 253         .xlate  = irq_domain_xlate_twocell,
 254 };
 255
 256 struct mpc8xxx_gpio_devtype {
 257         int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
 258         int (*gpio_get)(struct gpio_chip *, unsigned int);
 259         int (*irq_set_type)(struct irq_data *, unsigned int);
 260 };
 261
 262 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
 263         .gpio_dir_out = mpc5121_gpio_dir_out,
 264         .irq_set_type = mpc512x_irq_set_type,
 265 };
 266
 267 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
 268         .gpio_dir_out = mpc5125_gpio_dir_out,
 269         .irq_set_type = mpc512x_irq_set_type,
 270 };
 271
 272 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
 273         .gpio_get = mpc8572_gpio_get,
 274 };
 275
 276 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
 277         .irq_set_type = mpc8xxx_irq_set_type,
 278 };
 279
 280 static const struct of_device_id mpc8xxx_gpio_ids[] = {
 281         { .compatible = "fsl,mpc8349-gpio", },
 282         { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
 283         { .compatible = "fsl,mpc8610-gpio", },
 284         { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
 285         { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
 286         { .compatible = "fsl,pq3-gpio",     },
 287         { .compatible = "fsl,qoriq-gpio",   },
 288         {}
 289 };
 290
 291 static int mpc8xxx_probe(struct platform_device *pdev)
 292 {
 293         struct device_node *np = pdev->dev.of_node;
 294         struct mpc8xxx_gpio_chip *mpc8xxx_gc;
 295         struct gpio_chip        *gc;
 296         const struct mpc8xxx_gpio_devtype *devtype =
 297                 of_device_get_match_data(&pdev->dev);
 298         int ret;
 299
 300         mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
 301         if (!mpc8xxx_gc)
 302                 return -ENOMEM;
 303
 304         platform_set_drvdata(pdev, mpc8xxx_gc);
 305
 306         raw_spin_lock_init(&mpc8xxx_gc->lock);
 307
 308         mpc8xxx_gc->regs = of_iomap(np, 0);
 309         if (!mpc8xxx_gc->regs)
 310                 return -ENOMEM;
 311
 312         gc = &mpc8xxx_gc->gc;
 313
 314         if (of_property_read_bool(np, "little-endian")) {
 315                 ret = bgpio_init(gc, &pdev->dev, 4,
 316                                  mpc8xxx_gc->regs + GPIO_DAT,
 317                                  NULL, NULL,
 318                                  mpc8xxx_gc->regs + GPIO_DIR, NULL,
 319                                  BGPIOF_BIG_ENDIAN);
 320                 if (ret)
 321                         goto err;
 322                 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
 323         } else {
 324                 ret = bgpio_init(gc, &pdev->dev, 4,
 325                                  mpc8xxx_gc->regs + GPIO_DAT,
 326                                  NULL, NULL,
 327                                  mpc8xxx_gc->regs + GPIO_DIR, NULL,
 328                                  BGPIOF_BIG_ENDIAN
 329                                  | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
 330                 if (ret)
 331                         goto err;
 332                 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
 333         }
 334
 335         mpc8xxx_gc->read_reg = gc->read_reg;
 336         mpc8xxx_gc->write_reg = gc->write_reg;
 337
 338         if (!devtype)
 339                 devtype = &mpc8xxx_gpio_devtype_default;
 340
 341         /*
 342          * It's assumed that only a single type of gpio controller is available
 343          * on the current machine, so overwriting global data is fine.
 344          */
 345         mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
 346
 347         gc->direction_output = devtype->gpio_dir_out ?: gc->direction_output;
 348         gc->get = devtype->gpio_get ?: gc->get;
 349         gc->to_irq = mpc8xxx_gpio_to_irq;
 350
 351         mpc8xxx_gc->direction_output = gc->direction_output;
 352
 353         ret = gpiochip_add_data(gc, mpc8xxx_gc);
 354         if (ret) {
 355                 pr_err("%s: GPIO chip registration failed with status %d\n",
 356                        np->full_name, ret);
 357                 goto err;
 358         }
 359
 360         mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
 361         if (!mpc8xxx_gc->irqn)
 362                 return 0;
 363
 364         mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
 365                                         &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
 366         if (!mpc8xxx_gc->irq)
 367                 return 0;
 368
 369         /* ack and mask all irqs */
 370         mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
 371         mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
 372
 373         irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
 374                                          mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
 375         return 0;
 376 err:
 377         iounmap(mpc8xxx_gc->regs);
 378         return ret;
 379 }
 380
 381 static int mpc8xxx_remove(struct platform_device *pdev)
 382 {
 383         struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
 384
 385         if (mpc8xxx_gc->irq) {
 386                 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
 387                 irq_domain_remove(mpc8xxx_gc->irq);
 388         }
 389
 390         gpiochip_remove(&mpc8xxx_gc->gc);
 391         iounmap(mpc8xxx_gc->regs);
 392
 393         return 0;
 394 }
 395
 396 static struct platform_driver mpc8xxx_plat_driver = {
 397         .probe          = mpc8xxx_probe,
 398         .remove         = mpc8xxx_remove,
 399         .driver         = {
 400                 .name = "gpio-mpc8xxx",
 401                 .of_match_table = mpc8xxx_gpio_ids,
 402         },
 403 };
 404
 405 static int __init mpc8xxx_init(void)
 406 {
 407         return platform_driver_register(&mpc8xxx_plat_driver);
 408 }
 409
 410 arch_initcall(mpc8xxx_init);