2 * GPIO driver for Marvell SoCs
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
36 #include <linux/bitops.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/gpio/driver.h>
40 #include <linux/gpio/consumer.h>
41 #include <linux/init.h>
43 #include <linux/irq.h>
44 #include <linux/irqchip/chained_irq.h>
45 #include <linux/irqdomain.h>
46 #include <linux/mfd/syscon.h>
47 #include <linux/of_device.h>
48 #include <linux/of_irq.h>
49 #include <linux/pinctrl/consumer.h>
50 #include <linux/platform_device.h>
51 #include <linux/pwm.h>
52 #include <linux/regmap.h>
53 #include <linux/slab.h>
56 * GPIO unit register offsets.
58 #define GPIO_OUT_OFF 0x0000
59 #define GPIO_IO_CONF_OFF 0x0004
60 #define GPIO_BLINK_EN_OFF 0x0008
61 #define GPIO_IN_POL_OFF 0x000c
62 #define GPIO_DATA_IN_OFF 0x0010
63 #define GPIO_EDGE_CAUSE_OFF 0x0014
64 #define GPIO_EDGE_MASK_OFF 0x0018
65 #define GPIO_LEVEL_MASK_OFF 0x001c
66 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
69 * PWM register offsets.
71 #define PWM_BLINK_ON_DURATION_OFF 0x0
72 #define PWM_BLINK_OFF_DURATION_OFF 0x4
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
77 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
80 * The Armada XP has per-CPU registers for interrupt cause, interrupt
81 * mask and interrupt level mask. Those are relative to the
84 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
85 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
86 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
88 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
89 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
90 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
91 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
93 #define MVEBU_MAX_GPIO_PER_BANK 32
96 void __iomem
*membase
;
97 unsigned long clk_rate
;
98 struct gpio_desc
*gpiod
;
101 struct mvebu_gpio_chip
*mvchip
;
103 /* Used to preserve GPIO/PWM registers across suspend/resume */
105 u32 blink_on_duration
;
106 u32 blink_off_duration
;
109 struct mvebu_gpio_chip
{
110 struct gpio_chip chip
;
113 struct regmap
*percpu_regs
;
115 struct irq_domain
*domain
;
118 /* Used for PWM support */
120 struct mvebu_pwm
*mvpwm
;
122 /* Used to preserve GPIO registers across suspend/resume */
127 u32 edge_mask_regs
[4];
128 u32 level_mask_regs
[4];
132 * Functions returning addresses of individual registers for a given
136 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip
*mvchip
,
137 struct regmap
**map
, unsigned int *offset
)
141 switch (mvchip
->soc_variant
) {
142 case MVEBU_GPIO_SOC_VARIANT_ORION
:
143 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
144 case MVEBU_GPIO_SOC_VARIANT_A8K
:
146 *offset
= GPIO_EDGE_CAUSE_OFF
+ mvchip
->offset
;
148 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
149 cpu
= smp_processor_id();
150 *map
= mvchip
->percpu_regs
;
151 *offset
= GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu
);
159 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip
*mvchip
)
165 mvebu_gpioreg_edge_cause(mvchip
, &map
, &offset
);
166 regmap_read(map
, offset
, &val
);
172 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip
*mvchip
, u32 val
)
177 mvebu_gpioreg_edge_cause(mvchip
, &map
, &offset
);
178 regmap_write(map
, offset
, val
);
182 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip
*mvchip
,
183 struct regmap
**map
, unsigned int *offset
)
187 switch (mvchip
->soc_variant
) {
188 case MVEBU_GPIO_SOC_VARIANT_ORION
:
189 case MVEBU_GPIO_SOC_VARIANT_A8K
:
191 *offset
= GPIO_EDGE_MASK_OFF
+ mvchip
->offset
;
193 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
194 cpu
= smp_processor_id();
196 *offset
= GPIO_EDGE_MASK_MV78200_OFF(cpu
);
198 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
199 cpu
= smp_processor_id();
200 *map
= mvchip
->percpu_regs
;
201 *offset
= GPIO_EDGE_MASK_ARMADAXP_OFF(cpu
);
209 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip
*mvchip
)
215 mvebu_gpioreg_edge_mask(mvchip
, &map
, &offset
);
216 regmap_read(map
, offset
, &val
);
222 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip
*mvchip
, u32 val
)
227 mvebu_gpioreg_edge_mask(mvchip
, &map
, &offset
);
228 regmap_write(map
, offset
, val
);
232 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip
*mvchip
,
233 struct regmap
**map
, unsigned int *offset
)
237 switch (mvchip
->soc_variant
) {
238 case MVEBU_GPIO_SOC_VARIANT_ORION
:
239 case MVEBU_GPIO_SOC_VARIANT_A8K
:
241 *offset
= GPIO_LEVEL_MASK_OFF
+ mvchip
->offset
;
243 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
244 cpu
= smp_processor_id();
246 *offset
= GPIO_LEVEL_MASK_MV78200_OFF(cpu
);
248 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
249 cpu
= smp_processor_id();
250 *map
= mvchip
->percpu_regs
;
251 *offset
= GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu
);
259 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip
*mvchip
)
265 mvebu_gpioreg_level_mask(mvchip
, &map
, &offset
);
266 regmap_read(map
, offset
, &val
);
272 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip
*mvchip
, u32 val
)
277 mvebu_gpioreg_level_mask(mvchip
, &map
, &offset
);
278 regmap_write(map
, offset
, val
);
282 * Functions returning addresses of individual registers for a given
285 static void __iomem
*mvebu_pwmreg_blink_on_duration(struct mvebu_pwm
*mvpwm
)
287 return mvpwm
->membase
+ PWM_BLINK_ON_DURATION_OFF
;
290 static void __iomem
*mvebu_pwmreg_blink_off_duration(struct mvebu_pwm
*mvpwm
)
292 return mvpwm
->membase
+ PWM_BLINK_OFF_DURATION_OFF
;
296 * Functions implementing the gpio_chip methods
298 static void mvebu_gpio_set(struct gpio_chip
*chip
, unsigned int pin
, int value
)
300 struct mvebu_gpio_chip
*mvchip
= gpiochip_get_data(chip
);
302 regmap_update_bits(mvchip
->regs
, GPIO_OUT_OFF
+ mvchip
->offset
,
303 BIT(pin
), value
? BIT(pin
) : 0);
306 static int mvebu_gpio_get(struct gpio_chip
*chip
, unsigned int pin
)
308 struct mvebu_gpio_chip
*mvchip
= gpiochip_get_data(chip
);
311 regmap_read(mvchip
->regs
, GPIO_IO_CONF_OFF
+ mvchip
->offset
, &u
);
316 regmap_read(mvchip
->regs
, GPIO_DATA_IN_OFF
+ mvchip
->offset
,
318 regmap_read(mvchip
->regs
, GPIO_IN_POL_OFF
+ mvchip
->offset
,
320 u
= data_in
^ in_pol
;
322 regmap_read(mvchip
->regs
, GPIO_OUT_OFF
+ mvchip
->offset
, &u
);
325 return (u
>> pin
) & 1;
328 static void mvebu_gpio_blink(struct gpio_chip
*chip
, unsigned int pin
,
331 struct mvebu_gpio_chip
*mvchip
= gpiochip_get_data(chip
);
333 regmap_update_bits(mvchip
->regs
, GPIO_BLINK_EN_OFF
+ mvchip
->offset
,
334 BIT(pin
), value
? BIT(pin
) : 0);
337 static int mvebu_gpio_direction_input(struct gpio_chip
*chip
, unsigned int pin
)
339 struct mvebu_gpio_chip
*mvchip
= gpiochip_get_data(chip
);
343 * Check with the pinctrl driver whether this pin is usable as
346 ret
= pinctrl_gpio_direction_input(chip
->base
+ pin
);
350 regmap_update_bits(mvchip
->regs
, GPIO_IO_CONF_OFF
+ mvchip
->offset
,
356 static int mvebu_gpio_direction_output(struct gpio_chip
*chip
, unsigned int pin
,
359 struct mvebu_gpio_chip
*mvchip
= gpiochip_get_data(chip
);
363 * Check with the pinctrl driver whether this pin is usable as
366 ret
= pinctrl_gpio_direction_output(chip
->base
+ pin
);
370 mvebu_gpio_blink(chip
, pin
, 0);
371 mvebu_gpio_set(chip
, pin
, value
);
373 regmap_update_bits(mvchip
->regs
, GPIO_IO_CONF_OFF
+ mvchip
->offset
,
379 static int mvebu_gpio_get_direction(struct gpio_chip
*chip
, unsigned int pin
)
381 struct mvebu_gpio_chip
*mvchip
= gpiochip_get_data(chip
);
384 regmap_read(mvchip
->regs
, GPIO_IO_CONF_OFF
+ mvchip
->offset
, &u
);
386 return !!(u
& BIT(pin
));
389 static int mvebu_gpio_to_irq(struct gpio_chip
*chip
, unsigned int pin
)
391 struct mvebu_gpio_chip
*mvchip
= gpiochip_get_data(chip
);
393 return irq_create_mapping(mvchip
->domain
, pin
);
397 * Functions implementing the irq_chip methods
399 static void mvebu_gpio_irq_ack(struct irq_data
*d
)
401 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
402 struct mvebu_gpio_chip
*mvchip
= gc
->private;
406 mvebu_gpio_write_edge_cause(mvchip
, ~mask
);
410 static void mvebu_gpio_edge_irq_mask(struct irq_data
*d
)
412 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
413 struct mvebu_gpio_chip
*mvchip
= gc
->private;
414 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
418 ct
->mask_cache_priv
&= ~mask
;
419 mvebu_gpio_write_edge_mask(mvchip
, ct
->mask_cache_priv
);
423 static void mvebu_gpio_edge_irq_unmask(struct irq_data
*d
)
425 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
426 struct mvebu_gpio_chip
*mvchip
= gc
->private;
427 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
431 ct
->mask_cache_priv
|= mask
;
432 mvebu_gpio_write_edge_mask(mvchip
, ct
->mask_cache_priv
);
436 static void mvebu_gpio_level_irq_mask(struct irq_data
*d
)
438 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
439 struct mvebu_gpio_chip
*mvchip
= gc
->private;
440 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
444 ct
->mask_cache_priv
&= ~mask
;
445 mvebu_gpio_write_level_mask(mvchip
, ct
->mask_cache_priv
);
449 static void mvebu_gpio_level_irq_unmask(struct irq_data
*d
)
451 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
452 struct mvebu_gpio_chip
*mvchip
= gc
->private;
453 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
457 ct
->mask_cache_priv
|= mask
;
458 mvebu_gpio_write_level_mask(mvchip
, ct
->mask_cache_priv
);
462 /*****************************************************************************
465 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
466 * value of the line or the opposite value.
468 * Level IRQ handlers: DATA_IN is used directly as cause register.
469 * Interrupt are masked by LEVEL_MASK registers.
470 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
471 * Interrupt are masked by EDGE_MASK registers.
472 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
473 * the polarity to catch the next line transaction.
474 * This is a race condition that might not perfectly
475 * work on some use cases.
477 * Every eight GPIO lines are grouped (OR'ed) before going up to main
481 * data-in /--------| |-----| |----\
482 * -----| |----- ---- to main cause reg
483 * X \----------------| |----/
484 * polarity LEVEL mask
486 ****************************************************************************/
488 static int mvebu_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
490 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
491 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
492 struct mvebu_gpio_chip
*mvchip
= gc
->private;
498 regmap_read(mvchip
->regs
, GPIO_IO_CONF_OFF
+ mvchip
->offset
, &u
);
499 if ((u
& BIT(pin
)) == 0)
502 type
&= IRQ_TYPE_SENSE_MASK
;
503 if (type
== IRQ_TYPE_NONE
)
506 /* Check if we need to change chip and handler */
507 if (!(ct
->type
& type
))
508 if (irq_setup_alt_chip(d
, type
))
512 * Configure interrupt polarity.
515 case IRQ_TYPE_EDGE_RISING
:
516 case IRQ_TYPE_LEVEL_HIGH
:
517 regmap_update_bits(mvchip
->regs
,
518 GPIO_IN_POL_OFF
+ mvchip
->offset
,
521 case IRQ_TYPE_EDGE_FALLING
:
522 case IRQ_TYPE_LEVEL_LOW
:
523 regmap_update_bits(mvchip
->regs
,
524 GPIO_IN_POL_OFF
+ mvchip
->offset
,
527 case IRQ_TYPE_EDGE_BOTH
: {
528 u32 data_in
, in_pol
, val
;
530 regmap_read(mvchip
->regs
,
531 GPIO_IN_POL_OFF
+ mvchip
->offset
, &in_pol
);
532 regmap_read(mvchip
->regs
,
533 GPIO_DATA_IN_OFF
+ mvchip
->offset
, &data_in
);
536 * set initial polarity based on current input level
538 if ((data_in
^ in_pol
) & BIT(pin
))
539 val
= BIT(pin
); /* falling */
541 val
= 0; /* raising */
543 regmap_update_bits(mvchip
->regs
,
544 GPIO_IN_POL_OFF
+ mvchip
->offset
,
552 static void mvebu_gpio_irq_handler(struct irq_desc
*desc
)
554 struct mvebu_gpio_chip
*mvchip
= irq_desc_get_handler_data(desc
);
555 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
556 u32 cause
, type
, data_in
, level_mask
, edge_cause
, edge_mask
;
562 chained_irq_enter(chip
, desc
);
564 regmap_read(mvchip
->regs
, GPIO_DATA_IN_OFF
+ mvchip
->offset
, &data_in
);
565 level_mask
= mvebu_gpio_read_level_mask(mvchip
);
566 edge_cause
= mvebu_gpio_read_edge_cause(mvchip
);
567 edge_mask
= mvebu_gpio_read_edge_mask(mvchip
);
569 cause
= (data_in
& level_mask
) | (edge_cause
& edge_mask
);
571 for (i
= 0; i
< mvchip
->chip
.ngpio
; i
++) {
574 irq
= irq_find_mapping(mvchip
->domain
, i
);
576 if (!(cause
& BIT(i
)))
579 type
= irq_get_trigger_type(irq
);
580 if ((type
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
) {
581 /* Swap polarity (race with GPIO line) */
584 regmap_read(mvchip
->regs
,
585 GPIO_IN_POL_OFF
+ mvchip
->offset
,
588 regmap_write(mvchip
->regs
,
589 GPIO_IN_POL_OFF
+ mvchip
->offset
,
593 generic_handle_irq(irq
);
596 chained_irq_exit(chip
, desc
);
600 * Functions implementing the pwm_chip methods
602 static struct mvebu_pwm
*to_mvebu_pwm(struct pwm_chip
*chip
)
604 return container_of(chip
, struct mvebu_pwm
, chip
);
607 static int mvebu_pwm_request(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
609 struct mvebu_pwm
*mvpwm
= to_mvebu_pwm(chip
);
610 struct mvebu_gpio_chip
*mvchip
= mvpwm
->mvchip
;
611 struct gpio_desc
*desc
;
615 spin_lock_irqsave(&mvpwm
->lock
, flags
);
620 desc
= gpiochip_request_own_desc(&mvchip
->chip
,
621 pwm
->hwpwm
, "mvebu-pwm", 0);
627 ret
= gpiod_direction_output(desc
, 0);
629 gpiochip_free_own_desc(desc
);
636 spin_unlock_irqrestore(&mvpwm
->lock
, flags
);
640 static void mvebu_pwm_free(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
642 struct mvebu_pwm
*mvpwm
= to_mvebu_pwm(chip
);
645 spin_lock_irqsave(&mvpwm
->lock
, flags
);
646 gpiochip_free_own_desc(mvpwm
->gpiod
);
648 spin_unlock_irqrestore(&mvpwm
->lock
, flags
);
651 static void mvebu_pwm_get_state(struct pwm_chip
*chip
,
652 struct pwm_device
*pwm
,
653 struct pwm_state
*state
) {
655 struct mvebu_pwm
*mvpwm
= to_mvebu_pwm(chip
);
656 struct mvebu_gpio_chip
*mvchip
= mvpwm
->mvchip
;
657 unsigned long long val
;
661 spin_lock_irqsave(&mvpwm
->lock
, flags
);
663 val
= (unsigned long long)
664 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm
));
666 do_div(val
, mvpwm
->clk_rate
);
668 state
->duty_cycle
= UINT_MAX
;
670 state
->duty_cycle
= val
;
672 state
->duty_cycle
= 1;
674 val
= (unsigned long long)
675 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm
));
677 do_div(val
, mvpwm
->clk_rate
);
678 if (val
< state
->duty_cycle
) {
681 val
-= state
->duty_cycle
;
683 state
->period
= UINT_MAX
;
690 regmap_read(mvchip
->regs
, GPIO_BLINK_EN_OFF
+ mvchip
->offset
, &u
);
692 state
->enabled
= true;
694 state
->enabled
= false;
696 spin_unlock_irqrestore(&mvpwm
->lock
, flags
);
699 static int mvebu_pwm_apply(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
700 struct pwm_state
*state
)
702 struct mvebu_pwm
*mvpwm
= to_mvebu_pwm(chip
);
703 struct mvebu_gpio_chip
*mvchip
= mvpwm
->mvchip
;
704 unsigned long long val
;
706 unsigned int on
, off
;
708 val
= (unsigned long long) mvpwm
->clk_rate
* state
->duty_cycle
;
709 do_div(val
, NSEC_PER_SEC
);
717 val
= (unsigned long long) mvpwm
->clk_rate
*
718 (state
->period
- state
->duty_cycle
);
719 do_div(val
, NSEC_PER_SEC
);
727 spin_lock_irqsave(&mvpwm
->lock
, flags
);
729 writel_relaxed(on
, mvebu_pwmreg_blink_on_duration(mvpwm
));
730 writel_relaxed(off
, mvebu_pwmreg_blink_off_duration(mvpwm
));
732 mvebu_gpio_blink(&mvchip
->chip
, pwm
->hwpwm
, 1);
734 mvebu_gpio_blink(&mvchip
->chip
, pwm
->hwpwm
, 0);
736 spin_unlock_irqrestore(&mvpwm
->lock
, flags
);
741 static const struct pwm_ops mvebu_pwm_ops
= {
742 .request
= mvebu_pwm_request
,
743 .free
= mvebu_pwm_free
,
744 .get_state
= mvebu_pwm_get_state
,
745 .apply
= mvebu_pwm_apply
,
746 .owner
= THIS_MODULE
,
749 static void __maybe_unused
mvebu_pwm_suspend(struct mvebu_gpio_chip
*mvchip
)
751 struct mvebu_pwm
*mvpwm
= mvchip
->mvpwm
;
753 regmap_read(mvchip
->regs
, GPIO_BLINK_CNT_SELECT_OFF
+ mvchip
->offset
,
754 &mvpwm
->blink_select
);
755 mvpwm
->blink_on_duration
=
756 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm
));
757 mvpwm
->blink_off_duration
=
758 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm
));
761 static void __maybe_unused
mvebu_pwm_resume(struct mvebu_gpio_chip
*mvchip
)
763 struct mvebu_pwm
*mvpwm
= mvchip
->mvpwm
;
765 regmap_write(mvchip
->regs
, GPIO_BLINK_CNT_SELECT_OFF
+ mvchip
->offset
,
766 mvpwm
->blink_select
);
767 writel_relaxed(mvpwm
->blink_on_duration
,
768 mvebu_pwmreg_blink_on_duration(mvpwm
));
769 writel_relaxed(mvpwm
->blink_off_duration
,
770 mvebu_pwmreg_blink_off_duration(mvpwm
));
773 static int mvebu_pwm_probe(struct platform_device
*pdev
,
774 struct mvebu_gpio_chip
*mvchip
,
777 struct device
*dev
= &pdev
->dev
;
778 struct mvebu_pwm
*mvpwm
;
779 struct resource
*res
;
782 if (!of_device_is_compatible(mvchip
->chip
.of_node
,
783 "marvell,armada-370-gpio"))
787 * There are only two sets of PWM configuration registers for
788 * all the GPIO lines on those SoCs which this driver reserves
789 * for the first two GPIO chips. So if the resource is missing
790 * we can't treat it as an error.
792 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "pwm");
796 if (IS_ERR(mvchip
->clk
))
797 return PTR_ERR(mvchip
->clk
);
800 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
801 * with id 1. Don't allow further GPIO chips to be used for PWM.
809 regmap_write(mvchip
->regs
,
810 GPIO_BLINK_CNT_SELECT_OFF
+ mvchip
->offset
, set
);
812 mvpwm
= devm_kzalloc(dev
, sizeof(struct mvebu_pwm
), GFP_KERNEL
);
815 mvchip
->mvpwm
= mvpwm
;
816 mvpwm
->mvchip
= mvchip
;
818 mvpwm
->membase
= devm_ioremap_resource(dev
, res
);
819 if (IS_ERR(mvpwm
->membase
))
820 return PTR_ERR(mvpwm
->membase
);
822 mvpwm
->clk_rate
= clk_get_rate(mvchip
->clk
);
823 if (!mvpwm
->clk_rate
) {
824 dev_err(dev
, "failed to get clock rate\n");
828 mvpwm
->chip
.dev
= dev
;
829 mvpwm
->chip
.ops
= &mvebu_pwm_ops
;
830 mvpwm
->chip
.npwm
= mvchip
->chip
.ngpio
;
832 * There may already be some PWM allocated, so we can't force
833 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
834 * So, we let pwmchip_add() do the numbering and take the next free
837 mvpwm
->chip
.base
= -1;
839 spin_lock_init(&mvpwm
->lock
);
841 return pwmchip_add(&mvpwm
->chip
);
844 #ifdef CONFIG_DEBUG_FS
845 #include <linux/seq_file.h>
847 static void mvebu_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
849 struct mvebu_gpio_chip
*mvchip
= gpiochip_get_data(chip
);
850 u32 out
, io_conf
, blink
, in_pol
, data_in
, cause
, edg_msk
, lvl_msk
;
853 regmap_read(mvchip
->regs
, GPIO_OUT_OFF
+ mvchip
->offset
, &out
);
854 regmap_read(mvchip
->regs
, GPIO_IO_CONF_OFF
+ mvchip
->offset
, &io_conf
);
855 regmap_read(mvchip
->regs
, GPIO_BLINK_EN_OFF
+ mvchip
->offset
, &blink
);
856 regmap_read(mvchip
->regs
, GPIO_IN_POL_OFF
+ mvchip
->offset
, &in_pol
);
857 regmap_read(mvchip
->regs
, GPIO_DATA_IN_OFF
+ mvchip
->offset
, &data_in
);
858 cause
= mvebu_gpio_read_edge_cause(mvchip
);
859 edg_msk
= mvebu_gpio_read_edge_mask(mvchip
);
860 lvl_msk
= mvebu_gpio_read_level_mask(mvchip
);
862 for (i
= 0; i
< chip
->ngpio
; i
++) {
867 label
= gpiochip_is_requested(chip
, i
);
872 is_out
= !(io_conf
& msk
);
874 seq_printf(s
, " gpio-%-3d (%-20.20s)", chip
->base
+ i
, label
);
877 seq_printf(s
, " out %s %s\n",
878 out
& msk
? "hi" : "lo",
879 blink
& msk
? "(blink )" : "");
883 seq_printf(s
, " in %s (act %s) - IRQ",
884 (data_in
^ in_pol
) & msk
? "hi" : "lo",
885 in_pol
& msk
? "lo" : "hi");
886 if (!((edg_msk
| lvl_msk
) & msk
)) {
887 seq_puts(s
, " disabled\n");
891 seq_puts(s
, " edge ");
893 seq_puts(s
, " level");
894 seq_printf(s
, " (%s)\n", cause
& msk
? "pending" : "clear ");
898 #define mvebu_gpio_dbg_show NULL
901 static const struct of_device_id mvebu_gpio_of_match
[] = {
903 .compatible
= "marvell,orion-gpio",
904 .data
= (void *) MVEBU_GPIO_SOC_VARIANT_ORION
,
907 .compatible
= "marvell,mv78200-gpio",
908 .data
= (void *) MVEBU_GPIO_SOC_VARIANT_MV78200
,
911 .compatible
= "marvell,armadaxp-gpio",
912 .data
= (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP
,
915 .compatible
= "marvell,armada-370-gpio",
916 .data
= (void *) MVEBU_GPIO_SOC_VARIANT_ORION
,
919 .compatible
= "marvell,armada-8k-gpio",
920 .data
= (void *) MVEBU_GPIO_SOC_VARIANT_A8K
,
927 static int mvebu_gpio_suspend(struct platform_device
*pdev
, pm_message_t state
)
929 struct mvebu_gpio_chip
*mvchip
= platform_get_drvdata(pdev
);
932 regmap_read(mvchip
->regs
, GPIO_OUT_OFF
+ mvchip
->offset
,
934 regmap_read(mvchip
->regs
, GPIO_IO_CONF_OFF
+ mvchip
->offset
,
935 &mvchip
->io_conf_reg
);
936 regmap_read(mvchip
->regs
, GPIO_BLINK_EN_OFF
+ mvchip
->offset
,
937 &mvchip
->blink_en_reg
);
938 regmap_read(mvchip
->regs
, GPIO_IN_POL_OFF
+ mvchip
->offset
,
939 &mvchip
->in_pol_reg
);
941 switch (mvchip
->soc_variant
) {
942 case MVEBU_GPIO_SOC_VARIANT_ORION
:
943 case MVEBU_GPIO_SOC_VARIANT_A8K
:
944 regmap_read(mvchip
->regs
, GPIO_EDGE_MASK_OFF
+ mvchip
->offset
,
945 &mvchip
->edge_mask_regs
[0]);
946 regmap_read(mvchip
->regs
, GPIO_LEVEL_MASK_OFF
+ mvchip
->offset
,
947 &mvchip
->level_mask_regs
[0]);
949 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
950 for (i
= 0; i
< 2; i
++) {
951 regmap_read(mvchip
->regs
,
952 GPIO_EDGE_MASK_MV78200_OFF(i
),
953 &mvchip
->edge_mask_regs
[i
]);
954 regmap_read(mvchip
->regs
,
955 GPIO_LEVEL_MASK_MV78200_OFF(i
),
956 &mvchip
->level_mask_regs
[i
]);
959 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
960 for (i
= 0; i
< 4; i
++) {
961 regmap_read(mvchip
->regs
,
962 GPIO_EDGE_MASK_ARMADAXP_OFF(i
),
963 &mvchip
->edge_mask_regs
[i
]);
964 regmap_read(mvchip
->regs
,
965 GPIO_LEVEL_MASK_ARMADAXP_OFF(i
),
966 &mvchip
->level_mask_regs
[i
]);
973 if (IS_ENABLED(CONFIG_PWM
))
974 mvebu_pwm_suspend(mvchip
);
979 static int mvebu_gpio_resume(struct platform_device
*pdev
)
981 struct mvebu_gpio_chip
*mvchip
= platform_get_drvdata(pdev
);
984 regmap_write(mvchip
->regs
, GPIO_OUT_OFF
+ mvchip
->offset
,
986 regmap_write(mvchip
->regs
, GPIO_IO_CONF_OFF
+ mvchip
->offset
,
987 mvchip
->io_conf_reg
);
988 regmap_write(mvchip
->regs
, GPIO_BLINK_EN_OFF
+ mvchip
->offset
,
989 mvchip
->blink_en_reg
);
990 regmap_write(mvchip
->regs
, GPIO_IN_POL_OFF
+ mvchip
->offset
,
993 switch (mvchip
->soc_variant
) {
994 case MVEBU_GPIO_SOC_VARIANT_ORION
:
995 case MVEBU_GPIO_SOC_VARIANT_A8K
:
996 regmap_write(mvchip
->regs
, GPIO_EDGE_MASK_OFF
+ mvchip
->offset
,
997 mvchip
->edge_mask_regs
[0]);
998 regmap_write(mvchip
->regs
, GPIO_LEVEL_MASK_OFF
+ mvchip
->offset
,
999 mvchip
->level_mask_regs
[0]);
1001 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
1002 for (i
= 0; i
< 2; i
++) {
1003 regmap_write(mvchip
->regs
,
1004 GPIO_EDGE_MASK_MV78200_OFF(i
),
1005 mvchip
->edge_mask_regs
[i
]);
1006 regmap_write(mvchip
->regs
,
1007 GPIO_LEVEL_MASK_MV78200_OFF(i
),
1008 mvchip
->level_mask_regs
[i
]);
1011 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
1012 for (i
= 0; i
< 4; i
++) {
1013 regmap_write(mvchip
->regs
,
1014 GPIO_EDGE_MASK_ARMADAXP_OFF(i
),
1015 mvchip
->edge_mask_regs
[i
]);
1016 regmap_write(mvchip
->regs
,
1017 GPIO_LEVEL_MASK_ARMADAXP_OFF(i
),
1018 mvchip
->level_mask_regs
[i
]);
1025 if (IS_ENABLED(CONFIG_PWM
))
1026 mvebu_pwm_resume(mvchip
);
1031 static const struct regmap_config mvebu_gpio_regmap_config
= {
1038 static int mvebu_gpio_probe_raw(struct platform_device
*pdev
,
1039 struct mvebu_gpio_chip
*mvchip
)
1041 struct resource
*res
;
1044 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1045 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1047 return PTR_ERR(base
);
1049 mvchip
->regs
= devm_regmap_init_mmio(&pdev
->dev
, base
,
1050 &mvebu_gpio_regmap_config
);
1051 if (IS_ERR(mvchip
->regs
))
1052 return PTR_ERR(mvchip
->regs
);
1055 * For the legacy SoCs, the regmap directly maps to the GPIO
1056 * registers, so no offset is needed.
1061 * The Armada XP has a second range of registers for the
1064 if (mvchip
->soc_variant
== MVEBU_GPIO_SOC_VARIANT_ARMADAXP
) {
1065 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1066 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1068 return PTR_ERR(base
);
1070 mvchip
->percpu_regs
=
1071 devm_regmap_init_mmio(&pdev
->dev
, base
,
1072 &mvebu_gpio_regmap_config
);
1073 if (IS_ERR(mvchip
->percpu_regs
))
1074 return PTR_ERR(mvchip
->percpu_regs
);
1080 static int mvebu_gpio_probe_syscon(struct platform_device
*pdev
,
1081 struct mvebu_gpio_chip
*mvchip
)
1083 mvchip
->regs
= syscon_node_to_regmap(pdev
->dev
.parent
->of_node
);
1084 if (IS_ERR(mvchip
->regs
))
1085 return PTR_ERR(mvchip
->regs
);
1087 if (of_property_read_u32(pdev
->dev
.of_node
, "offset", &mvchip
->offset
))
1093 static int mvebu_gpio_probe(struct platform_device
*pdev
)
1095 struct mvebu_gpio_chip
*mvchip
;
1096 const struct of_device_id
*match
;
1097 struct device_node
*np
= pdev
->dev
.of_node
;
1098 struct irq_chip_generic
*gc
;
1099 struct irq_chip_type
*ct
;
1100 unsigned int ngpios
;
1106 match
= of_match_device(mvebu_gpio_of_match
, &pdev
->dev
);
1108 soc_variant
= (unsigned long) match
->data
;
1110 soc_variant
= MVEBU_GPIO_SOC_VARIANT_ORION
;
1112 /* Some gpio controllers do not provide irq support */
1113 have_irqs
= of_irq_count(np
) != 0;
1115 mvchip
= devm_kzalloc(&pdev
->dev
, sizeof(struct mvebu_gpio_chip
),
1120 platform_set_drvdata(pdev
, mvchip
);
1122 if (of_property_read_u32(pdev
->dev
.of_node
, "ngpios", &ngpios
)) {
1123 dev_err(&pdev
->dev
, "Missing ngpios OF property\n");
1127 id
= of_alias_get_id(pdev
->dev
.of_node
, "gpio");
1129 dev_err(&pdev
->dev
, "Couldn't get OF id\n");
1133 mvchip
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1134 /* Not all SoCs require a clock.*/
1135 if (!IS_ERR(mvchip
->clk
))
1136 clk_prepare_enable(mvchip
->clk
);
1138 mvchip
->soc_variant
= soc_variant
;
1139 mvchip
->chip
.label
= dev_name(&pdev
->dev
);
1140 mvchip
->chip
.parent
= &pdev
->dev
;
1141 mvchip
->chip
.request
= gpiochip_generic_request
;
1142 mvchip
->chip
.free
= gpiochip_generic_free
;
1143 mvchip
->chip
.get_direction
= mvebu_gpio_get_direction
;
1144 mvchip
->chip
.direction_input
= mvebu_gpio_direction_input
;
1145 mvchip
->chip
.get
= mvebu_gpio_get
;
1146 mvchip
->chip
.direction_output
= mvebu_gpio_direction_output
;
1147 mvchip
->chip
.set
= mvebu_gpio_set
;
1149 mvchip
->chip
.to_irq
= mvebu_gpio_to_irq
;
1150 mvchip
->chip
.base
= id
* MVEBU_MAX_GPIO_PER_BANK
;
1151 mvchip
->chip
.ngpio
= ngpios
;
1152 mvchip
->chip
.can_sleep
= false;
1153 mvchip
->chip
.of_node
= np
;
1154 mvchip
->chip
.dbg_show
= mvebu_gpio_dbg_show
;
1156 if (soc_variant
== MVEBU_GPIO_SOC_VARIANT_A8K
)
1157 err
= mvebu_gpio_probe_syscon(pdev
, mvchip
);
1159 err
= mvebu_gpio_probe_raw(pdev
, mvchip
);
1165 * Mask and clear GPIO interrupts.
1167 switch (soc_variant
) {
1168 case MVEBU_GPIO_SOC_VARIANT_ORION
:
1169 case MVEBU_GPIO_SOC_VARIANT_A8K
:
1170 regmap_write(mvchip
->regs
,
1171 GPIO_EDGE_CAUSE_OFF
+ mvchip
->offset
, 0);
1172 regmap_write(mvchip
->regs
,
1173 GPIO_EDGE_MASK_OFF
+ mvchip
->offset
, 0);
1174 regmap_write(mvchip
->regs
,
1175 GPIO_LEVEL_MASK_OFF
+ mvchip
->offset
, 0);
1177 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
1178 regmap_write(mvchip
->regs
, GPIO_EDGE_CAUSE_OFF
, 0);
1179 for (cpu
= 0; cpu
< 2; cpu
++) {
1180 regmap_write(mvchip
->regs
,
1181 GPIO_EDGE_MASK_MV78200_OFF(cpu
), 0);
1182 regmap_write(mvchip
->regs
,
1183 GPIO_LEVEL_MASK_MV78200_OFF(cpu
), 0);
1186 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
1187 regmap_write(mvchip
->regs
, GPIO_EDGE_CAUSE_OFF
, 0);
1188 regmap_write(mvchip
->regs
, GPIO_EDGE_MASK_OFF
, 0);
1189 regmap_write(mvchip
->regs
, GPIO_LEVEL_MASK_OFF
, 0);
1190 for (cpu
= 0; cpu
< 4; cpu
++) {
1191 regmap_write(mvchip
->percpu_regs
,
1192 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu
), 0);
1193 regmap_write(mvchip
->percpu_regs
,
1194 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu
), 0);
1195 regmap_write(mvchip
->percpu_regs
,
1196 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu
), 0);
1203 devm_gpiochip_add_data(&pdev
->dev
, &mvchip
->chip
, mvchip
);
1205 /* Some gpio controllers do not provide irq support */
1210 irq_domain_add_linear(np
, ngpios
, &irq_generic_chip_ops
, NULL
);
1211 if (!mvchip
->domain
) {
1212 dev_err(&pdev
->dev
, "couldn't allocate irq domain %s (DT).\n",
1213 mvchip
->chip
.label
);
1217 err
= irq_alloc_domain_generic_chips(
1218 mvchip
->domain
, ngpios
, 2, np
->name
, handle_level_irq
,
1219 IRQ_NOREQUEST
| IRQ_NOPROBE
| IRQ_LEVEL
, 0, 0);
1221 dev_err(&pdev
->dev
, "couldn't allocate irq chips %s (DT).\n",
1222 mvchip
->chip
.label
);
1227 * NOTE: The common accessors cannot be used because of the percpu
1228 * access to the mask registers
1230 gc
= irq_get_domain_generic_chip(mvchip
->domain
, 0);
1231 gc
->private = mvchip
;
1232 ct
= &gc
->chip_types
[0];
1233 ct
->type
= IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
;
1234 ct
->chip
.irq_mask
= mvebu_gpio_level_irq_mask
;
1235 ct
->chip
.irq_unmask
= mvebu_gpio_level_irq_unmask
;
1236 ct
->chip
.irq_set_type
= mvebu_gpio_irq_set_type
;
1237 ct
->chip
.name
= mvchip
->chip
.label
;
1239 ct
= &gc
->chip_types
[1];
1240 ct
->type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
1241 ct
->chip
.irq_ack
= mvebu_gpio_irq_ack
;
1242 ct
->chip
.irq_mask
= mvebu_gpio_edge_irq_mask
;
1243 ct
->chip
.irq_unmask
= mvebu_gpio_edge_irq_unmask
;
1244 ct
->chip
.irq_set_type
= mvebu_gpio_irq_set_type
;
1245 ct
->handler
= handle_edge_irq
;
1246 ct
->chip
.name
= mvchip
->chip
.label
;
1249 * Setup the interrupt handlers. Each chip can have up to 4
1250 * interrupt handlers, with each handler dealing with 8 GPIO
1253 for (i
= 0; i
< 4; i
++) {
1254 int irq
= platform_get_irq(pdev
, i
);
1258 irq_set_chained_handler_and_data(irq
, mvebu_gpio_irq_handler
,
1262 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1263 if (IS_ENABLED(CONFIG_PWM
))
1264 return mvebu_pwm_probe(pdev
, mvchip
, id
);
1269 irq_domain_remove(mvchip
->domain
);
1274 static struct platform_driver mvebu_gpio_driver
= {
1276 .name
= "mvebu-gpio",
1277 .of_match_table
= mvebu_gpio_of_match
,
1279 .probe
= mvebu_gpio_probe
,
1280 .suspend
= mvebu_gpio_suspend
,
1281 .resume
= mvebu_gpio_resume
,
1283 builtin_platform_driver(mvebu_gpio_driver
);