drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/gpio.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30 #include <linux/basic_mmio_gpio.h>
  31 #include <mach/mxs.h>
  32
  33 #define MXS_SET         0x4
  34 #define MXS_CLR         0x8
  35
  36 #define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
  37 #define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
  38 #define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
  39 #define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
  40 #define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
  41 #define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
  42 #define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
  43 #define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
  44
  45 #define GPIO_INT_FALL_EDGE      0x0
  46 #define GPIO_INT_LOW_LEV        0x1
  47 #define GPIO_INT_RISE_EDGE      0x2
  48 #define GPIO_INT_HIGH_LEV       0x3
  49 #define GPIO_INT_LEV_MASK       (1 << 0)
  50 #define GPIO_INT_POL_MASK       (1 << 1)
  51
  52 #define irq_to_gpio(irq)        ((irq) - MXS_GPIO_IRQ_START)
  53
  54 struct mxs_gpio_port {
  55         void __iomem *base;
  56         int id;
  57         int irq;
  58         int virtual_irq_start;
  59         struct bgpio_chip bgc;
  60 };
  61
  62 /* Note: This driver assumes 32 GPIOs are handled in one register */
  63
  64 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  65 {
  66         u32 gpio = irq_to_gpio(d->irq);
  67         u32 pin_mask = 1 << (gpio & 31);
  68         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  69         struct mxs_gpio_port *port = gc->private;
  70         void __iomem *pin_addr;
  71         int edge;
  72
  73         switch (type) {
  74         case IRQ_TYPE_EDGE_RISING:
  75                 edge = GPIO_INT_RISE_EDGE;
  76                 break;
  77         case IRQ_TYPE_EDGE_FALLING:
  78                 edge = GPIO_INT_FALL_EDGE;
  79                 break;
  80         case IRQ_TYPE_LEVEL_LOW:
  81                 edge = GPIO_INT_LOW_LEV;
  82                 break;
  83         case IRQ_TYPE_LEVEL_HIGH:
  84                 edge = GPIO_INT_HIGH_LEV;
  85                 break;
  86         default:
  87                 return -EINVAL;
  88         }
  89
  90         /* set level or edge */
  91         pin_addr = port->base + PINCTRL_IRQLEV(port->id);
  92         if (edge & GPIO_INT_LEV_MASK)
  93                 writel(pin_mask, pin_addr + MXS_SET);
  94         else
  95                 writel(pin_mask, pin_addr + MXS_CLR);
  96
  97         /* set polarity */
  98         pin_addr = port->base + PINCTRL_IRQPOL(port->id);
  99         if (edge & GPIO_INT_POL_MASK)
 100                 writel(pin_mask, pin_addr + MXS_SET);
 101         else
 102                 writel(pin_mask, pin_addr + MXS_CLR);
 103
 104         writel(1 << (gpio & 0x1f),
 105                port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 106
 107         return 0;
 108 }
 109
 110 /* MXS has one interrupt *per* gpio port */
 111 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 112 {
 113         u32 irq_stat;
 114         struct mxs_gpio_port *port = irq_get_handler_data(irq);
 115         u32 gpio_irq_no_base = port->virtual_irq_start;
 116
 117         desc->irq_data.chip->irq_ack(&desc->irq_data);
 118
 119         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
 120                         readl(port->base + PINCTRL_IRQEN(port->id));
 121
 122         while (irq_stat != 0) {
 123                 int irqoffset = fls(irq_stat) - 1;
 124                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 125                 irq_stat &= ~(1 << irqoffset);
 126         }
 127 }
 128
 129 /*
 130  * Set interrupt number "irq" in the GPIO as a wake-up source.
 131  * While system is running, all registered GPIO interrupts need to have
 132  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 133  * need to have wake-up enabled.
 134  * @param  irq          interrupt source number
 135  * @param  enable       enable as wake-up if equal to non-zero
 136  * @return       This function returns 0 on success.
 137  */
 138 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 139 {
 140         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 141         struct mxs_gpio_port *port = gc->private;
 142
 143         if (enable)
 144                 enable_irq_wake(port->irq);
 145         else
 146                 disable_irq_wake(port->irq);
 147
 148         return 0;
 149 }
 150
 151 static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
 152 {
 153         struct irq_chip_generic *gc;
 154         struct irq_chip_type *ct;
 155
 156         gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
 157                                     port->base, handle_level_irq);
 158         gc->private = port;
 159
 160         ct = gc->chip_types;
 161         ct->chip.irq_ack = irq_gc_ack_set_bit;
 162         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 163         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 164         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 165         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 166         ct->regs.ack = PINCTRL_IRQSTAT(port->id) + MXS_CLR;
 167         ct->regs.mask = PINCTRL_IRQEN(port->id);
 168
 169         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 170 }
 171
 172 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 173 {
 174         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 175         struct mxs_gpio_port *port =
 176                 container_of(bgc, struct mxs_gpio_port, bgc);
 177
 178         return port->virtual_irq_start + offset;
 179 }
 180
 181 static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 182 {
 183         static void __iomem *base;
 184         struct mxs_gpio_port *port;
 185         struct resource *iores = NULL;
 186         int err;
 187
 188         port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
 189         if (!port)
 190                 return -ENOMEM;
 191
 192         port->id = pdev->id;
 193         port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
 194
 195         /*
 196          * map memory region only once, as all the gpio ports
 197          * share the same one
 198          */
 199         if (!base) {
 200                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 201                 if (!iores) {
 202                         err = -ENODEV;
 203                         goto out_kfree;
 204                 }
 205
 206                 if (!request_mem_region(iores->start, resource_size(iores),
 207                                         pdev->name)) {
 208                         err = -EBUSY;
 209                         goto out_kfree;
 210                 }
 211
 212                 base = ioremap(iores->start, resource_size(iores));
 213                 if (!base) {
 214                         err = -ENOMEM;
 215                         goto out_release_mem;
 216                 }
 217         }
 218         port->base = base;
 219
 220         port->irq = platform_get_irq(pdev, 0);
 221         if (port->irq < 0) {
 222                 err = -EINVAL;
 223                 goto out_iounmap;
 224         }
 225
 226         /*
 227          * select the pin interrupt functionality but initially
 228          * disable the interrupts
 229          */
 230         writel(~0U, port->base + PINCTRL_PIN2IRQ(port->id));
 231         writel(0, port->base + PINCTRL_IRQEN(port->id));
 232
 233         /* clear address has to be used to clear IRQSTAT bits */
 234         writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 235
 236         /* gpio-mxs can be a generic irq chip */
 237         mxs_gpio_init_gc(port);
 238
 239         /* setup one handler for each entry */
 240         irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
 241         irq_set_handler_data(port->irq, port);
 242
 243         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 244                          port->base + PINCTRL_DIN(port->id),
 245                          port->base + PINCTRL_DOUT(port->id), NULL,
 246                          port->base + PINCTRL_DOE(port->id), NULL, false);
 247         if (err)
 248                 goto out_iounmap;
 249
 250         port->bgc.gc.to_irq = mxs_gpio_to_irq;
 251         port->bgc.gc.base = port->id * 32;
 252
 253         err = gpiochip_add(&port->bgc.gc);
 254         if (err)
 255                 goto out_bgpio_remove;
 256
 257         return 0;
 258
 259 out_bgpio_remove:
 260         bgpio_remove(&port->bgc);
 261 out_iounmap:
 262         if (iores)
 263                 iounmap(port->base);
 264 out_release_mem:
 265         if (iores)
 266                 release_mem_region(iores->start, resource_size(iores));
 267 out_kfree:
 268         kfree(port);
 269         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 270         return err;
 271 }
 272
 273 static struct platform_driver mxs_gpio_driver = {
 274         .driver         = {
 275                 .name   = "gpio-mxs",
 276                 .owner  = THIS_MODULE,
 277         },
 278         .probe          = mxs_gpio_probe,
 279 };
 280
 281 static int __init mxs_gpio_init(void)
 282 {
 283         return platform_driver_register(&mxs_gpio_driver);
 284 }
 285 postcore_initcall(mxs_gpio_init);
 286
 287 MODULE_AUTHOR("Freescale Semiconductor, "
 288               "Daniel Mack <danielncaiaq.de>, "
 289               "Juergen Beisert <kernel@pengutronix.de>");
 290 MODULE_DESCRIPTION("Freescale MXS GPIO");
 291 MODULE_LICENSE("GPL");