2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
27 #include <linux/of_device.h>
28 #include <linux/gpio/driver.h>
29 #include <linux/bitops.h>
30 #include <linux/platform_data/gpio-omap.h>
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
34 #define OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER BIT(2)
53 struct gpio_omap_funcs
{
54 void (*idle_enable_level_quirk
)(struct gpio_bank
*bank
);
55 void (*idle_disable_level_quirk
)(struct gpio_bank
*bank
);
59 struct list_head node
;
63 u32 enabled_non_wakeup_gpios
;
64 struct gpio_regs context
;
65 struct gpio_omap_funcs funcs
;
70 raw_spinlock_t wa_lock
;
71 struct gpio_chip chip
;
73 struct notifier_block nb
;
74 unsigned int is_suspended
:1;
85 int context_loss_count
;
88 void (*set_dataout
)(struct gpio_bank
*bank
, unsigned gpio
, int enable
);
89 void (*set_dataout_multiple
)(struct gpio_bank
*bank
,
90 unsigned long *mask
, unsigned long *bits
);
91 int (*get_context_loss_count
)(struct device
*dev
);
93 struct omap_gpio_reg_offs
*regs
;
96 #define GPIO_MOD_CTRL_BIT BIT(0)
98 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
99 #define LINE_USED(line, offset) (line & (BIT(offset)))
101 static void omap_gpio_unmask_irq(struct irq_data
*d
);
103 static inline struct gpio_bank
*omap_irq_data_get_bank(struct irq_data
*d
)
105 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
106 return gpiochip_get_data(chip
);
109 static void omap_set_gpio_direction(struct gpio_bank
*bank
, int gpio
,
112 void __iomem
*reg
= bank
->base
;
115 reg
+= bank
->regs
->direction
;
116 l
= readl_relaxed(reg
);
121 writel_relaxed(l
, reg
);
122 bank
->context
.oe
= l
;
126 /* set data out value using dedicate set/clear register */
127 static void omap_set_gpio_dataout_reg(struct gpio_bank
*bank
, unsigned offset
,
130 void __iomem
*reg
= bank
->base
;
134 reg
+= bank
->regs
->set_dataout
;
135 bank
->context
.dataout
|= l
;
137 reg
+= bank
->regs
->clr_dataout
;
138 bank
->context
.dataout
&= ~l
;
141 writel_relaxed(l
, reg
);
144 /* set data out value using mask register */
145 static void omap_set_gpio_dataout_mask(struct gpio_bank
*bank
, unsigned offset
,
148 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
149 u32 gpio_bit
= BIT(offset
);
152 l
= readl_relaxed(reg
);
157 writel_relaxed(l
, reg
);
158 bank
->context
.dataout
= l
;
161 static int omap_get_gpio_datain(struct gpio_bank
*bank
, int offset
)
163 void __iomem
*reg
= bank
->base
+ bank
->regs
->datain
;
165 return (readl_relaxed(reg
) & (BIT(offset
))) != 0;
168 static int omap_get_gpio_dataout(struct gpio_bank
*bank
, int offset
)
170 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
172 return (readl_relaxed(reg
) & (BIT(offset
))) != 0;
175 /* set multiple data out values using dedicate set/clear register */
176 static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank
*bank
,
180 void __iomem
*reg
= bank
->base
;
184 writel_relaxed(l
, reg
+ bank
->regs
->set_dataout
);
185 bank
->context
.dataout
|= l
;
188 writel_relaxed(l
, reg
+ bank
->regs
->clr_dataout
);
189 bank
->context
.dataout
&= ~l
;
192 /* set multiple data out values using mask register */
193 static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank
*bank
,
197 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
198 u32 l
= (readl_relaxed(reg
) & ~*mask
) | (*bits
& *mask
);
200 writel_relaxed(l
, reg
);
201 bank
->context
.dataout
= l
;
204 static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank
*bank
,
207 void __iomem
*reg
= bank
->base
+ bank
->regs
->datain
;
209 return readl_relaxed(reg
) & *mask
;
212 static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank
*bank
,
215 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
217 return readl_relaxed(reg
) & *mask
;
220 static inline void omap_gpio_rmw(void __iomem
*base
, u32 reg
, u32 mask
, bool set
)
222 int l
= readl_relaxed(base
+ reg
);
229 writel_relaxed(l
, base
+ reg
);
232 static inline void omap_gpio_dbck_enable(struct gpio_bank
*bank
)
234 if (bank
->dbck_enable_mask
&& !bank
->dbck_enabled
) {
235 clk_enable(bank
->dbck
);
236 bank
->dbck_enabled
= true;
238 writel_relaxed(bank
->dbck_enable_mask
,
239 bank
->base
+ bank
->regs
->debounce_en
);
243 static inline void omap_gpio_dbck_disable(struct gpio_bank
*bank
)
245 if (bank
->dbck_enable_mask
&& bank
->dbck_enabled
) {
247 * Disable debounce before cutting it's clock. If debounce is
248 * enabled but the clock is not, GPIO module seems to be unable
249 * to detect events and generate interrupts at least on OMAP3.
251 writel_relaxed(0, bank
->base
+ bank
->regs
->debounce_en
);
253 clk_disable(bank
->dbck
);
254 bank
->dbck_enabled
= false;
259 * omap2_set_gpio_debounce - low level gpio debounce time
260 * @bank: the gpio bank we're acting upon
261 * @offset: the gpio number on this @bank
262 * @debounce: debounce time to use
264 * OMAP's debounce time is in 31us steps
265 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
266 * so we need to convert and round up to the closest unit.
268 * Return: 0 on success, negative error otherwise.
270 static int omap2_set_gpio_debounce(struct gpio_bank
*bank
, unsigned offset
,
276 bool enable
= !!debounce
;
278 if (!bank
->dbck_flag
)
282 debounce
= DIV_ROUND_UP(debounce
, 31) - 1;
283 if ((debounce
& OMAP4_GPIO_DEBOUNCINGTIME_MASK
) != debounce
)
289 clk_enable(bank
->dbck
);
290 reg
= bank
->base
+ bank
->regs
->debounce
;
291 writel_relaxed(debounce
, reg
);
293 reg
= bank
->base
+ bank
->regs
->debounce_en
;
294 val
= readl_relaxed(reg
);
300 bank
->dbck_enable_mask
= val
;
302 writel_relaxed(val
, reg
);
303 clk_disable(bank
->dbck
);
305 * Enable debounce clock per module.
306 * This call is mandatory because in omap_gpio_request() when
307 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
308 * runtime callbck fails to turn on dbck because dbck_enable_mask
309 * used within _gpio_dbck_enable() is still not initialized at
310 * that point. Therefore we have to enable dbck here.
312 omap_gpio_dbck_enable(bank
);
313 if (bank
->dbck_enable_mask
) {
314 bank
->context
.debounce
= debounce
;
315 bank
->context
.debounce_en
= val
;
322 * omap_clear_gpio_debounce - clear debounce settings for a gpio
323 * @bank: the gpio bank we're acting upon
324 * @offset: the gpio number on this @bank
326 * If a gpio is using debounce, then clear the debounce enable bit and if
327 * this is the only gpio in this bank using debounce, then clear the debounce
328 * time too. The debounce clock will also be disabled when calling this function
329 * if this is the only gpio in the bank using debounce.
331 static void omap_clear_gpio_debounce(struct gpio_bank
*bank
, unsigned offset
)
333 u32 gpio_bit
= BIT(offset
);
335 if (!bank
->dbck_flag
)
338 if (!(bank
->dbck_enable_mask
& gpio_bit
))
341 bank
->dbck_enable_mask
&= ~gpio_bit
;
342 bank
->context
.debounce_en
&= ~gpio_bit
;
343 writel_relaxed(bank
->context
.debounce_en
,
344 bank
->base
+ bank
->regs
->debounce_en
);
346 if (!bank
->dbck_enable_mask
) {
347 bank
->context
.debounce
= 0;
348 writel_relaxed(bank
->context
.debounce
, bank
->base
+
349 bank
->regs
->debounce
);
350 clk_disable(bank
->dbck
);
351 bank
->dbck_enabled
= false;
355 static inline void omap_set_gpio_trigger(struct gpio_bank
*bank
, int gpio
,
358 void __iomem
*base
= bank
->base
;
359 u32 gpio_bit
= BIT(gpio
);
361 omap_gpio_rmw(base
, bank
->regs
->leveldetect0
, gpio_bit
,
362 trigger
& IRQ_TYPE_LEVEL_LOW
);
363 omap_gpio_rmw(base
, bank
->regs
->leveldetect1
, gpio_bit
,
364 trigger
& IRQ_TYPE_LEVEL_HIGH
);
365 omap_gpio_rmw(base
, bank
->regs
->risingdetect
, gpio_bit
,
366 trigger
& IRQ_TYPE_EDGE_RISING
);
367 omap_gpio_rmw(base
, bank
->regs
->fallingdetect
, gpio_bit
,
368 trigger
& IRQ_TYPE_EDGE_FALLING
);
370 bank
->context
.leveldetect0
=
371 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
372 bank
->context
.leveldetect1
=
373 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
374 bank
->context
.risingdetect
=
375 readl_relaxed(bank
->base
+ bank
->regs
->risingdetect
);
376 bank
->context
.fallingdetect
=
377 readl_relaxed(bank
->base
+ bank
->regs
->fallingdetect
);
379 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
380 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, gpio_bit
, trigger
!= 0);
381 bank
->context
.wake_en
=
382 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
385 /* This part needs to be executed always for OMAP{34xx, 44xx} */
386 if (!bank
->regs
->irqctrl
) {
387 /* On omap24xx proceed only when valid GPIO bit is set */
388 if (bank
->non_wakeup_gpios
) {
389 if (!(bank
->non_wakeup_gpios
& gpio_bit
))
394 * Log the edge gpio and manually trigger the IRQ
395 * after resume if the input level changes
396 * to avoid irq lost during PER RET/OFF mode
397 * Applies for omap2 non-wakeup gpio and all omap3 gpios
399 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
400 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
402 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
407 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
) |
408 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
411 #ifdef CONFIG_ARCH_OMAP1
413 * This only applies to chips that can't do both rising and falling edge
414 * detection at once. For all other chips, this function is a noop.
416 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
418 void __iomem
*reg
= bank
->base
;
421 if (!bank
->regs
->irqctrl
)
424 reg
+= bank
->regs
->irqctrl
;
426 l
= readl_relaxed(reg
);
432 writel_relaxed(l
, reg
);
435 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
) {}
438 static int omap_set_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
441 void __iomem
*reg
= bank
->base
;
442 void __iomem
*base
= bank
->base
;
445 if (bank
->regs
->leveldetect0
&& bank
->regs
->wkup_en
) {
446 omap_set_gpio_trigger(bank
, gpio
, trigger
);
447 } else if (bank
->regs
->irqctrl
) {
448 reg
+= bank
->regs
->irqctrl
;
450 l
= readl_relaxed(reg
);
451 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
452 bank
->toggle_mask
|= BIT(gpio
);
453 if (trigger
& IRQ_TYPE_EDGE_RISING
)
455 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
460 writel_relaxed(l
, reg
);
461 } else if (bank
->regs
->edgectrl1
) {
463 reg
+= bank
->regs
->edgectrl2
;
465 reg
+= bank
->regs
->edgectrl1
;
468 l
= readl_relaxed(reg
);
469 l
&= ~(3 << (gpio
<< 1));
470 if (trigger
& IRQ_TYPE_EDGE_RISING
)
471 l
|= 2 << (gpio
<< 1);
472 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
475 /* Enable wake-up during idle for dynamic tick */
476 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, BIT(gpio
), trigger
);
477 bank
->context
.wake_en
=
478 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
479 writel_relaxed(l
, reg
);
484 static void omap_enable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
486 if (bank
->regs
->pinctrl
) {
487 void __iomem
*reg
= bank
->base
+ bank
->regs
->pinctrl
;
489 /* Claim the pin for MPU */
490 writel_relaxed(readl_relaxed(reg
) | (BIT(offset
)), reg
);
493 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
494 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
497 ctrl
= readl_relaxed(reg
);
498 /* Module is enabled, clocks are not gated */
499 ctrl
&= ~GPIO_MOD_CTRL_BIT
;
500 writel_relaxed(ctrl
, reg
);
501 bank
->context
.ctrl
= ctrl
;
505 static void omap_disable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
507 void __iomem
*base
= bank
->base
;
509 if (bank
->regs
->wkup_en
&&
510 !LINE_USED(bank
->mod_usage
, offset
) &&
511 !LINE_USED(bank
->irq_usage
, offset
)) {
512 /* Disable wake-up during idle for dynamic tick */
513 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, BIT(offset
), 0);
514 bank
->context
.wake_en
=
515 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
518 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
519 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
522 ctrl
= readl_relaxed(reg
);
523 /* Module is disabled, clocks are gated */
524 ctrl
|= GPIO_MOD_CTRL_BIT
;
525 writel_relaxed(ctrl
, reg
);
526 bank
->context
.ctrl
= ctrl
;
530 static int omap_gpio_is_input(struct gpio_bank
*bank
, unsigned offset
)
532 void __iomem
*reg
= bank
->base
+ bank
->regs
->direction
;
534 return readl_relaxed(reg
) & BIT(offset
);
537 static void omap_gpio_init_irq(struct gpio_bank
*bank
, unsigned offset
)
539 if (!LINE_USED(bank
->mod_usage
, offset
)) {
540 omap_enable_gpio_module(bank
, offset
);
541 omap_set_gpio_direction(bank
, offset
, 1);
543 bank
->irq_usage
|= BIT(offset
);
546 static int omap_gpio_irq_type(struct irq_data
*d
, unsigned type
)
548 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
551 unsigned offset
= d
->hwirq
;
553 if (type
& ~IRQ_TYPE_SENSE_MASK
)
556 if (!bank
->regs
->leveldetect0
&&
557 (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
560 raw_spin_lock_irqsave(&bank
->lock
, flags
);
561 retval
= omap_set_gpio_triggering(bank
, offset
, type
);
563 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
566 omap_gpio_init_irq(bank
, offset
);
567 if (!omap_gpio_is_input(bank
, offset
)) {
568 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
572 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
574 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
575 irq_set_handler_locked(d
, handle_level_irq
);
576 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
578 * Edge IRQs are already cleared/acked in irq_handler and
579 * not need to be masked, as result handle_edge_irq()
580 * logic is excessed here and may cause lose of interrupts.
581 * So just use handle_simple_irq.
583 irq_set_handler_locked(d
, handle_simple_irq
);
591 static void omap_clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
593 void __iomem
*reg
= bank
->base
;
595 reg
+= bank
->regs
->irqstatus
;
596 writel_relaxed(gpio_mask
, reg
);
598 /* Workaround for clearing DSP GPIO interrupts to allow retention */
599 if (bank
->regs
->irqstatus2
) {
600 reg
= bank
->base
+ bank
->regs
->irqstatus2
;
601 writel_relaxed(gpio_mask
, reg
);
604 /* Flush posted write for the irq status to avoid spurious interrupts */
608 static inline void omap_clear_gpio_irqstatus(struct gpio_bank
*bank
,
611 omap_clear_gpio_irqbank(bank
, BIT(offset
));
614 static u32
omap_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
616 void __iomem
*reg
= bank
->base
;
618 u32 mask
= (BIT(bank
->width
)) - 1;
620 reg
+= bank
->regs
->irqenable
;
621 l
= readl_relaxed(reg
);
622 if (bank
->regs
->irqenable_inv
)
628 static void omap_enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
630 void __iomem
*reg
= bank
->base
;
633 if (bank
->regs
->set_irqenable
) {
634 reg
+= bank
->regs
->set_irqenable
;
636 bank
->context
.irqenable1
|= gpio_mask
;
638 reg
+= bank
->regs
->irqenable
;
639 l
= readl_relaxed(reg
);
640 if (bank
->regs
->irqenable_inv
)
644 bank
->context
.irqenable1
= l
;
647 writel_relaxed(l
, reg
);
650 static void omap_disable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
652 void __iomem
*reg
= bank
->base
;
655 if (bank
->regs
->clr_irqenable
) {
656 reg
+= bank
->regs
->clr_irqenable
;
658 bank
->context
.irqenable1
&= ~gpio_mask
;
660 reg
+= bank
->regs
->irqenable
;
661 l
= readl_relaxed(reg
);
662 if (bank
->regs
->irqenable_inv
)
666 bank
->context
.irqenable1
= l
;
669 writel_relaxed(l
, reg
);
672 static inline void omap_set_gpio_irqenable(struct gpio_bank
*bank
,
673 unsigned offset
, int enable
)
676 omap_enable_gpio_irqbank(bank
, BIT(offset
));
678 omap_disable_gpio_irqbank(bank
, BIT(offset
));
681 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
682 static int omap_gpio_wake_enable(struct irq_data
*d
, unsigned int enable
)
684 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
686 return irq_set_irq_wake(bank
->irq
, enable
);
689 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
691 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
694 pm_runtime_get_sync(chip
->parent
);
696 raw_spin_lock_irqsave(&bank
->lock
, flags
);
697 omap_enable_gpio_module(bank
, offset
);
698 bank
->mod_usage
|= BIT(offset
);
699 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
704 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
706 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
709 raw_spin_lock_irqsave(&bank
->lock
, flags
);
710 bank
->mod_usage
&= ~(BIT(offset
));
711 if (!LINE_USED(bank
->irq_usage
, offset
)) {
712 omap_set_gpio_direction(bank
, offset
, 1);
713 omap_clear_gpio_debounce(bank
, offset
);
715 omap_disable_gpio_module(bank
, offset
);
716 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
718 pm_runtime_put(chip
->parent
);
722 * We need to unmask the GPIO bank interrupt as soon as possible to
723 * avoid missing GPIO interrupts for other lines in the bank.
724 * Then we need to mask-read-clear-unmask the triggered GPIO lines
725 * in the bank to avoid missing nested interrupts for a GPIO line.
726 * If we wait to unmask individual GPIO lines in the bank after the
727 * line's interrupt handler has been run, we may miss some nested
730 static irqreturn_t
omap_gpio_irq_handler(int irq
, void *gpiobank
)
732 void __iomem
*isr_reg
= NULL
;
733 u32 enabled
, isr
, level_mask
;
735 struct gpio_bank
*bank
= gpiobank
;
736 unsigned long wa_lock_flags
;
737 unsigned long lock_flags
;
739 isr_reg
= bank
->base
+ bank
->regs
->irqstatus
;
740 if (WARN_ON(!isr_reg
))
743 if (WARN_ONCE(!pm_runtime_active(bank
->chip
.parent
),
744 "gpio irq%i while runtime suspended?\n", irq
))
748 raw_spin_lock_irqsave(&bank
->lock
, lock_flags
);
750 enabled
= omap_get_gpio_irqbank_mask(bank
);
751 isr
= readl_relaxed(isr_reg
) & enabled
;
753 if (bank
->level_mask
)
754 level_mask
= bank
->level_mask
& enabled
;
758 /* clear edge sensitive interrupts before handler(s) are
759 called so that we don't miss any interrupt occurred while
761 if (isr
& ~level_mask
)
762 omap_clear_gpio_irqbank(bank
, isr
& ~level_mask
);
764 raw_spin_unlock_irqrestore(&bank
->lock
, lock_flags
);
773 raw_spin_lock_irqsave(&bank
->lock
, lock_flags
);
775 * Some chips can't respond to both rising and falling
776 * at the same time. If this irq was requested with
777 * both flags, we need to flip the ICR data for the IRQ
778 * to respond to the IRQ for the opposite direction.
779 * This will be indicated in the bank toggle_mask.
781 if (bank
->toggle_mask
& (BIT(bit
)))
782 omap_toggle_gpio_edge_triggering(bank
, bit
);
784 raw_spin_unlock_irqrestore(&bank
->lock
, lock_flags
);
786 raw_spin_lock_irqsave(&bank
->wa_lock
, wa_lock_flags
);
788 generic_handle_irq(irq_find_mapping(bank
->chip
.irq
.domain
,
791 raw_spin_unlock_irqrestore(&bank
->wa_lock
,
799 static unsigned int omap_gpio_irq_startup(struct irq_data
*d
)
801 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
803 unsigned offset
= d
->hwirq
;
805 raw_spin_lock_irqsave(&bank
->lock
, flags
);
807 if (!LINE_USED(bank
->mod_usage
, offset
))
808 omap_set_gpio_direction(bank
, offset
, 1);
809 else if (!omap_gpio_is_input(bank
, offset
))
811 omap_enable_gpio_module(bank
, offset
);
812 bank
->irq_usage
|= BIT(offset
);
814 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
815 omap_gpio_unmask_irq(d
);
819 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
823 static void omap_gpio_irq_shutdown(struct irq_data
*d
)
825 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
827 unsigned offset
= d
->hwirq
;
829 raw_spin_lock_irqsave(&bank
->lock
, flags
);
830 bank
->irq_usage
&= ~(BIT(offset
));
831 omap_set_gpio_irqenable(bank
, offset
, 0);
832 omap_clear_gpio_irqstatus(bank
, offset
);
833 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
834 if (!LINE_USED(bank
->mod_usage
, offset
))
835 omap_clear_gpio_debounce(bank
, offset
);
836 omap_disable_gpio_module(bank
, offset
);
837 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
840 static void omap_gpio_irq_bus_lock(struct irq_data
*data
)
842 struct gpio_bank
*bank
= omap_irq_data_get_bank(data
);
844 pm_runtime_get_sync(bank
->chip
.parent
);
847 static void gpio_irq_bus_sync_unlock(struct irq_data
*data
)
849 struct gpio_bank
*bank
= omap_irq_data_get_bank(data
);
851 pm_runtime_put(bank
->chip
.parent
);
854 static void omap_gpio_ack_irq(struct irq_data
*d
)
856 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
857 unsigned offset
= d
->hwirq
;
859 omap_clear_gpio_irqstatus(bank
, offset
);
862 static void omap_gpio_mask_irq(struct irq_data
*d
)
864 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
865 unsigned offset
= d
->hwirq
;
868 raw_spin_lock_irqsave(&bank
->lock
, flags
);
869 omap_set_gpio_irqenable(bank
, offset
, 0);
870 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
871 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
874 static void omap_gpio_unmask_irq(struct irq_data
*d
)
876 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
877 unsigned offset
= d
->hwirq
;
878 u32 trigger
= irqd_get_trigger_type(d
);
881 raw_spin_lock_irqsave(&bank
->lock
, flags
);
883 omap_set_gpio_triggering(bank
, offset
, trigger
);
885 omap_set_gpio_irqenable(bank
, offset
, 1);
888 * For level-triggered GPIOs, clearing must be done after the source
889 * is cleared, thus after the handler has run. OMAP4 needs this done
890 * after enabing the interrupt to clear the wakeup status.
892 if (bank
->level_mask
& BIT(offset
))
893 omap_clear_gpio_irqstatus(bank
, offset
);
895 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
899 * Only edges can generate a wakeup event to the PRCM.
901 * Therefore, ensure any wake-up capable GPIOs have
902 * edge-detection enabled before going idle to ensure a wakeup
903 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
906 * The normal values will be restored upon ->runtime_resume()
907 * by writing back the values saved in bank->context.
909 static void __maybe_unused
910 omap2_gpio_enable_level_quirk(struct gpio_bank
*bank
)
912 u32 wake_low
, wake_hi
;
914 /* Enable additional edge detection for level gpios for idle */
915 wake_low
= bank
->context
.leveldetect0
& bank
->context
.wake_en
;
917 writel_relaxed(wake_low
| bank
->context
.fallingdetect
,
918 bank
->base
+ bank
->regs
->fallingdetect
);
920 wake_hi
= bank
->context
.leveldetect1
& bank
->context
.wake_en
;
922 writel_relaxed(wake_hi
| bank
->context
.risingdetect
,
923 bank
->base
+ bank
->regs
->risingdetect
);
926 static void __maybe_unused
927 omap2_gpio_disable_level_quirk(struct gpio_bank
*bank
)
929 /* Disable edge detection for level gpios after idle */
930 writel_relaxed(bank
->context
.fallingdetect
,
931 bank
->base
+ bank
->regs
->fallingdetect
);
932 writel_relaxed(bank
->context
.risingdetect
,
933 bank
->base
+ bank
->regs
->risingdetect
);
936 /*---------------------------------------------------------------------*/
938 static int omap_mpuio_suspend_noirq(struct device
*dev
)
940 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
941 void __iomem
*mask_reg
= bank
->base
+
942 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
945 raw_spin_lock_irqsave(&bank
->lock
, flags
);
946 writel_relaxed(0xffff & ~bank
->context
.wake_en
, mask_reg
);
947 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
952 static int omap_mpuio_resume_noirq(struct device
*dev
)
954 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
955 void __iomem
*mask_reg
= bank
->base
+
956 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
959 raw_spin_lock_irqsave(&bank
->lock
, flags
);
960 writel_relaxed(bank
->context
.wake_en
, mask_reg
);
961 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
966 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
967 .suspend_noirq
= omap_mpuio_suspend_noirq
,
968 .resume_noirq
= omap_mpuio_resume_noirq
,
971 /* use platform_driver for this. */
972 static struct platform_driver omap_mpuio_driver
= {
975 .pm
= &omap_mpuio_dev_pm_ops
,
979 static struct platform_device omap_mpuio_device
= {
983 .driver
= &omap_mpuio_driver
.driver
,
985 /* could list the /proc/iomem resources */
988 static inline void omap_mpuio_init(struct gpio_bank
*bank
)
990 platform_set_drvdata(&omap_mpuio_device
, bank
);
992 if (platform_driver_register(&omap_mpuio_driver
) == 0)
993 (void) platform_device_register(&omap_mpuio_device
);
996 /*---------------------------------------------------------------------*/
998 static int omap_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
1000 struct gpio_bank
*bank
;
1001 unsigned long flags
;
1005 bank
= gpiochip_get_data(chip
);
1006 reg
= bank
->base
+ bank
->regs
->direction
;
1007 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1008 dir
= !!(readl_relaxed(reg
) & BIT(offset
));
1009 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1013 static int omap_gpio_input(struct gpio_chip
*chip
, unsigned offset
)
1015 struct gpio_bank
*bank
;
1016 unsigned long flags
;
1018 bank
= gpiochip_get_data(chip
);
1019 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1020 omap_set_gpio_direction(bank
, offset
, 1);
1021 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1025 static int omap_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1027 struct gpio_bank
*bank
;
1029 bank
= gpiochip_get_data(chip
);
1031 if (omap_gpio_is_input(bank
, offset
))
1032 return omap_get_gpio_datain(bank
, offset
);
1034 return omap_get_gpio_dataout(bank
, offset
);
1037 static int omap_gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
1039 struct gpio_bank
*bank
;
1040 unsigned long flags
;
1042 bank
= gpiochip_get_data(chip
);
1043 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1044 bank
->set_dataout(bank
, offset
, value
);
1045 omap_set_gpio_direction(bank
, offset
, 0);
1046 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1050 static int omap_gpio_get_multiple(struct gpio_chip
*chip
, unsigned long *mask
,
1051 unsigned long *bits
)
1053 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
1054 void __iomem
*reg
= bank
->base
+ bank
->regs
->direction
;
1055 unsigned long in
= readl_relaxed(reg
), l
;
1061 *bits
|= omap_get_gpio_datain_multiple(bank
, &l
);
1065 *bits
|= omap_get_gpio_dataout_multiple(bank
, &l
);
1070 static int omap_gpio_debounce(struct gpio_chip
*chip
, unsigned offset
,
1073 struct gpio_bank
*bank
;
1074 unsigned long flags
;
1077 bank
= gpiochip_get_data(chip
);
1079 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1080 ret
= omap2_set_gpio_debounce(bank
, offset
, debounce
);
1081 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1084 dev_info(chip
->parent
,
1085 "Could not set line %u debounce to %u microseconds (%d)",
1086 offset
, debounce
, ret
);
1091 static int omap_gpio_set_config(struct gpio_chip
*chip
, unsigned offset
,
1092 unsigned long config
)
1096 if (pinconf_to_config_param(config
) != PIN_CONFIG_INPUT_DEBOUNCE
)
1099 debounce
= pinconf_to_config_argument(config
);
1100 return omap_gpio_debounce(chip
, offset
, debounce
);
1103 static void omap_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1105 struct gpio_bank
*bank
;
1106 unsigned long flags
;
1108 bank
= gpiochip_get_data(chip
);
1109 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1110 bank
->set_dataout(bank
, offset
, value
);
1111 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1114 static void omap_gpio_set_multiple(struct gpio_chip
*chip
, unsigned long *mask
,
1115 unsigned long *bits
)
1117 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
1118 unsigned long flags
;
1120 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1121 bank
->set_dataout_multiple(bank
, mask
, bits
);
1122 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1125 /*---------------------------------------------------------------------*/
1127 static void omap_gpio_show_rev(struct gpio_bank
*bank
)
1132 if (called
|| bank
->regs
->revision
== USHRT_MAX
)
1135 rev
= readw_relaxed(bank
->base
+ bank
->regs
->revision
);
1136 pr_info("OMAP GPIO hardware version %d.%d\n",
1137 (rev
>> 4) & 0x0f, rev
& 0x0f);
1142 static void omap_gpio_mod_init(struct gpio_bank
*bank
)
1144 void __iomem
*base
= bank
->base
;
1147 if (bank
->width
== 16)
1150 if (bank
->is_mpuio
) {
1151 writel_relaxed(l
, bank
->base
+ bank
->regs
->irqenable
);
1155 omap_gpio_rmw(base
, bank
->regs
->irqenable
, l
,
1156 bank
->regs
->irqenable_inv
);
1157 omap_gpio_rmw(base
, bank
->regs
->irqstatus
, l
,
1158 !bank
->regs
->irqenable_inv
);
1159 if (bank
->regs
->debounce_en
)
1160 writel_relaxed(0, base
+ bank
->regs
->debounce_en
);
1162 /* Save OE default value (0xffffffff) in the context */
1163 bank
->context
.oe
= readl_relaxed(bank
->base
+ bank
->regs
->direction
);
1164 /* Initialize interface clk ungated, module enabled */
1165 if (bank
->regs
->ctrl
)
1166 writel_relaxed(0, base
+ bank
->regs
->ctrl
);
1169 static int omap_gpio_chip_init(struct gpio_bank
*bank
, struct irq_chip
*irqc
)
1171 struct gpio_irq_chip
*irq
;
1178 * REVISIT eventually switch from OMAP-specific gpio structs
1179 * over to the generic ones
1181 bank
->chip
.request
= omap_gpio_request
;
1182 bank
->chip
.free
= omap_gpio_free
;
1183 bank
->chip
.get_direction
= omap_gpio_get_direction
;
1184 bank
->chip
.direction_input
= omap_gpio_input
;
1185 bank
->chip
.get
= omap_gpio_get
;
1186 bank
->chip
.get_multiple
= omap_gpio_get_multiple
;
1187 bank
->chip
.direction_output
= omap_gpio_output
;
1188 bank
->chip
.set_config
= omap_gpio_set_config
;
1189 bank
->chip
.set
= omap_gpio_set
;
1190 bank
->chip
.set_multiple
= omap_gpio_set_multiple
;
1191 if (bank
->is_mpuio
) {
1192 bank
->chip
.label
= "mpuio";
1193 if (bank
->regs
->wkup_en
)
1194 bank
->chip
.parent
= &omap_mpuio_device
.dev
;
1195 bank
->chip
.base
= OMAP_MPUIO(0);
1197 label
= devm_kasprintf(bank
->chip
.parent
, GFP_KERNEL
, "gpio-%d-%d",
1198 gpio
, gpio
+ bank
->width
- 1);
1201 bank
->chip
.label
= label
;
1202 bank
->chip
.base
= gpio
;
1204 bank
->chip
.ngpio
= bank
->width
;
1206 #ifdef CONFIG_ARCH_OMAP1
1208 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1209 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1211 irq_base
= devm_irq_alloc_descs(bank
->chip
.parent
,
1212 -1, 0, bank
->width
, 0);
1214 dev_err(bank
->chip
.parent
, "Couldn't allocate IRQ numbers\n");
1219 /* MPUIO is a bit different, reading IRQ status clears it */
1220 if (bank
->is_mpuio
) {
1221 irqc
->irq_ack
= dummy_irq_chip
.irq_ack
;
1222 if (!bank
->regs
->wkup_en
)
1223 irqc
->irq_set_wake
= NULL
;
1226 irq
= &bank
->chip
.irq
;
1228 irq
->handler
= handle_bad_irq
;
1229 irq
->default_type
= IRQ_TYPE_NONE
;
1230 irq
->num_parents
= 1;
1231 irq
->parents
= &bank
->irq
;
1232 irq
->first
= irq_base
;
1234 ret
= gpiochip_add_data(&bank
->chip
, bank
);
1236 dev_err(bank
->chip
.parent
,
1237 "Could not register gpio chip %d\n", ret
);
1241 ret
= devm_request_irq(bank
->chip
.parent
, bank
->irq
,
1242 omap_gpio_irq_handler
,
1243 0, dev_name(bank
->chip
.parent
), bank
);
1245 gpiochip_remove(&bank
->chip
);
1247 if (!bank
->is_mpuio
)
1248 gpio
+= bank
->width
;
1253 static void omap_gpio_idle(struct gpio_bank
*bank
, bool may_lose_context
);
1254 static void omap_gpio_unidle(struct gpio_bank
*bank
);
1256 static int gpio_omap_cpu_notifier(struct notifier_block
*nb
,
1257 unsigned long cmd
, void *v
)
1259 struct gpio_bank
*bank
;
1260 unsigned long flags
;
1262 bank
= container_of(nb
, struct gpio_bank
, nb
);
1264 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1266 case CPU_CLUSTER_PM_ENTER
:
1267 if (bank
->is_suspended
)
1269 omap_gpio_idle(bank
, true);
1271 case CPU_CLUSTER_PM_ENTER_FAILED
:
1272 case CPU_CLUSTER_PM_EXIT
:
1273 if (bank
->is_suspended
)
1275 omap_gpio_unidle(bank
);
1278 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1283 static const struct of_device_id omap_gpio_match
[];
1285 static int omap_gpio_probe(struct platform_device
*pdev
)
1287 struct device
*dev
= &pdev
->dev
;
1288 struct device_node
*node
= dev
->of_node
;
1289 const struct of_device_id
*match
;
1290 const struct omap_gpio_platform_data
*pdata
;
1291 struct resource
*res
;
1292 struct gpio_bank
*bank
;
1293 struct irq_chip
*irqc
;
1296 match
= of_match_device(of_match_ptr(omap_gpio_match
), dev
);
1298 pdata
= match
? match
->data
: dev_get_platdata(dev
);
1302 bank
= devm_kzalloc(dev
, sizeof(*bank
), GFP_KERNEL
);
1306 irqc
= devm_kzalloc(dev
, sizeof(*irqc
), GFP_KERNEL
);
1310 irqc
->irq_startup
= omap_gpio_irq_startup
,
1311 irqc
->irq_shutdown
= omap_gpio_irq_shutdown
,
1312 irqc
->irq_ack
= omap_gpio_ack_irq
,
1313 irqc
->irq_mask
= omap_gpio_mask_irq
,
1314 irqc
->irq_unmask
= omap_gpio_unmask_irq
,
1315 irqc
->irq_set_type
= omap_gpio_irq_type
,
1316 irqc
->irq_set_wake
= omap_gpio_wake_enable
,
1317 irqc
->irq_bus_lock
= omap_gpio_irq_bus_lock
,
1318 irqc
->irq_bus_sync_unlock
= gpio_irq_bus_sync_unlock
,
1319 irqc
->name
= dev_name(&pdev
->dev
);
1320 irqc
->flags
= IRQCHIP_MASK_ON_SUSPEND
;
1321 irqc
->parent_device
= dev
;
1323 bank
->irq
= platform_get_irq(pdev
, 0);
1324 if (bank
->irq
<= 0) {
1327 if (bank
->irq
!= -EPROBE_DEFER
)
1329 "can't get irq resource ret=%d\n", bank
->irq
);
1333 bank
->chip
.parent
= dev
;
1334 bank
->chip
.owner
= THIS_MODULE
;
1335 bank
->dbck_flag
= pdata
->dbck_flag
;
1336 bank
->quirks
= pdata
->quirks
;
1337 bank
->stride
= pdata
->bank_stride
;
1338 bank
->width
= pdata
->bank_width
;
1339 bank
->is_mpuio
= pdata
->is_mpuio
;
1340 bank
->non_wakeup_gpios
= pdata
->non_wakeup_gpios
;
1341 bank
->regs
= pdata
->regs
;
1342 #ifdef CONFIG_OF_GPIO
1343 bank
->chip
.of_node
= of_node_get(node
);
1347 if (!of_property_read_bool(node
, "ti,gpio-always-on"))
1348 bank
->loses_context
= true;
1350 bank
->loses_context
= pdata
->loses_context
;
1352 if (bank
->loses_context
)
1353 bank
->get_context_loss_count
=
1354 pdata
->get_context_loss_count
;
1357 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
) {
1358 bank
->set_dataout
= omap_set_gpio_dataout_reg
;
1359 bank
->set_dataout_multiple
= omap_set_gpio_dataout_reg_multiple
;
1361 bank
->set_dataout
= omap_set_gpio_dataout_mask
;
1362 bank
->set_dataout_multiple
=
1363 omap_set_gpio_dataout_mask_multiple
;
1366 if (bank
->quirks
& OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER
) {
1367 bank
->funcs
.idle_enable_level_quirk
=
1368 omap2_gpio_enable_level_quirk
;
1369 bank
->funcs
.idle_disable_level_quirk
=
1370 omap2_gpio_disable_level_quirk
;
1373 raw_spin_lock_init(&bank
->lock
);
1374 raw_spin_lock_init(&bank
->wa_lock
);
1376 /* Static mapping, never released */
1377 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1378 bank
->base
= devm_ioremap_resource(dev
, res
);
1379 if (IS_ERR(bank
->base
)) {
1380 return PTR_ERR(bank
->base
);
1383 if (bank
->dbck_flag
) {
1384 bank
->dbck
= devm_clk_get(dev
, "dbclk");
1385 if (IS_ERR(bank
->dbck
)) {
1387 "Could not get gpio dbck. Disable debounce\n");
1388 bank
->dbck_flag
= false;
1390 clk_prepare(bank
->dbck
);
1394 platform_set_drvdata(pdev
, bank
);
1396 pm_runtime_enable(dev
);
1397 pm_runtime_get_sync(dev
);
1400 omap_mpuio_init(bank
);
1402 omap_gpio_mod_init(bank
);
1404 ret
= omap_gpio_chip_init(bank
, irqc
);
1406 pm_runtime_put_sync(dev
);
1407 pm_runtime_disable(dev
);
1408 if (bank
->dbck_flag
)
1409 clk_unprepare(bank
->dbck
);
1413 omap_gpio_show_rev(bank
);
1415 if (bank
->funcs
.idle_enable_level_quirk
&&
1416 bank
->funcs
.idle_disable_level_quirk
) {
1417 bank
->nb
.notifier_call
= gpio_omap_cpu_notifier
;
1418 cpu_pm_register_notifier(&bank
->nb
);
1421 pm_runtime_put(dev
);
1426 static int omap_gpio_remove(struct platform_device
*pdev
)
1428 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1430 if (bank
->nb
.notifier_call
)
1431 cpu_pm_unregister_notifier(&bank
->nb
);
1432 list_del(&bank
->node
);
1433 gpiochip_remove(&bank
->chip
);
1434 pm_runtime_disable(&pdev
->dev
);
1435 if (bank
->dbck_flag
)
1436 clk_unprepare(bank
->dbck
);
1441 static void omap_gpio_restore_context(struct gpio_bank
*bank
);
1443 static void omap_gpio_idle(struct gpio_bank
*bank
, bool may_lose_context
)
1445 struct device
*dev
= bank
->chip
.parent
;
1446 void __iomem
*base
= bank
->base
;
1449 bank
->saved_datain
= readl_relaxed(base
+ bank
->regs
->datain
);
1451 if (bank
->funcs
.idle_enable_level_quirk
)
1452 bank
->funcs
.idle_enable_level_quirk(bank
);
1454 if (!bank
->enabled_non_wakeup_gpios
)
1455 goto update_gpio_context_count
;
1457 if (!may_lose_context
)
1458 goto update_gpio_context_count
;
1461 * If going to OFF, remove triggering for all wkup domain
1462 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1463 * generated. See OMAP2420 Errata item 1.101.
1465 if (!bank
->loses_context
&& bank
->enabled_non_wakeup_gpios
) {
1466 nowake
= bank
->enabled_non_wakeup_gpios
;
1467 omap_gpio_rmw(base
, bank
->regs
->fallingdetect
, nowake
, ~nowake
);
1468 omap_gpio_rmw(base
, bank
->regs
->risingdetect
, nowake
, ~nowake
);
1471 update_gpio_context_count
:
1472 if (bank
->get_context_loss_count
)
1473 bank
->context_loss_count
=
1474 bank
->get_context_loss_count(dev
);
1476 omap_gpio_dbck_disable(bank
);
1479 static void omap_gpio_init_context(struct gpio_bank
*p
);
1481 static void omap_gpio_unidle(struct gpio_bank
*bank
)
1483 struct device
*dev
= bank
->chip
.parent
;
1484 u32 l
= 0, gen
, gen0
, gen1
;
1488 * On the first resume during the probe, the context has not
1489 * been initialised and so initialise it now. Also initialise
1490 * the context loss count.
1492 if (bank
->loses_context
&& !bank
->context_valid
) {
1493 omap_gpio_init_context(bank
);
1495 if (bank
->get_context_loss_count
)
1496 bank
->context_loss_count
=
1497 bank
->get_context_loss_count(dev
);
1500 omap_gpio_dbck_enable(bank
);
1502 if (bank
->funcs
.idle_disable_level_quirk
)
1503 bank
->funcs
.idle_disable_level_quirk(bank
);
1505 if (bank
->loses_context
) {
1506 if (!bank
->get_context_loss_count
) {
1507 omap_gpio_restore_context(bank
);
1509 c
= bank
->get_context_loss_count(dev
);
1510 if (c
!= bank
->context_loss_count
) {
1511 omap_gpio_restore_context(bank
);
1517 /* Restore changes done for OMAP2420 errata 1.101 */
1518 writel_relaxed(bank
->context
.fallingdetect
,
1519 bank
->base
+ bank
->regs
->fallingdetect
);
1520 writel_relaxed(bank
->context
.risingdetect
,
1521 bank
->base
+ bank
->regs
->risingdetect
);
1524 l
= readl_relaxed(bank
->base
+ bank
->regs
->datain
);
1527 * Check if any of the non-wakeup interrupt GPIOs have changed
1528 * state. If so, generate an IRQ by software. This is
1529 * horribly racy, but it's the best we can do to work around
1532 l
^= bank
->saved_datain
;
1533 l
&= bank
->enabled_non_wakeup_gpios
;
1536 * No need to generate IRQs for the rising edge for gpio IRQs
1537 * configured with falling edge only; and vice versa.
1539 gen0
= l
& bank
->context
.fallingdetect
;
1540 gen0
&= bank
->saved_datain
;
1542 gen1
= l
& bank
->context
.risingdetect
;
1543 gen1
&= ~(bank
->saved_datain
);
1545 /* FIXME: Consider GPIO IRQs with level detections properly! */
1546 gen
= l
& (~(bank
->context
.fallingdetect
) &
1547 ~(bank
->context
.risingdetect
));
1548 /* Consider all GPIO IRQs needed to be updated */
1554 old0
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
1555 old1
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
1557 if (!bank
->regs
->irqstatus_raw0
) {
1558 writel_relaxed(old0
| gen
, bank
->base
+
1559 bank
->regs
->leveldetect0
);
1560 writel_relaxed(old1
| gen
, bank
->base
+
1561 bank
->regs
->leveldetect1
);
1564 if (bank
->regs
->irqstatus_raw0
) {
1565 writel_relaxed(old0
| l
, bank
->base
+
1566 bank
->regs
->leveldetect0
);
1567 writel_relaxed(old1
| l
, bank
->base
+
1568 bank
->regs
->leveldetect1
);
1570 writel_relaxed(old0
, bank
->base
+ bank
->regs
->leveldetect0
);
1571 writel_relaxed(old1
, bank
->base
+ bank
->regs
->leveldetect1
);
1575 static void omap_gpio_init_context(struct gpio_bank
*p
)
1577 struct omap_gpio_reg_offs
*regs
= p
->regs
;
1578 void __iomem
*base
= p
->base
;
1580 p
->context
.ctrl
= readl_relaxed(base
+ regs
->ctrl
);
1581 p
->context
.oe
= readl_relaxed(base
+ regs
->direction
);
1582 p
->context
.wake_en
= readl_relaxed(base
+ regs
->wkup_en
);
1583 p
->context
.leveldetect0
= readl_relaxed(base
+ regs
->leveldetect0
);
1584 p
->context
.leveldetect1
= readl_relaxed(base
+ regs
->leveldetect1
);
1585 p
->context
.risingdetect
= readl_relaxed(base
+ regs
->risingdetect
);
1586 p
->context
.fallingdetect
= readl_relaxed(base
+ regs
->fallingdetect
);
1587 p
->context
.irqenable1
= readl_relaxed(base
+ regs
->irqenable
);
1588 p
->context
.irqenable2
= readl_relaxed(base
+ regs
->irqenable2
);
1590 if (regs
->set_dataout
&& p
->regs
->clr_dataout
)
1591 p
->context
.dataout
= readl_relaxed(base
+ regs
->set_dataout
);
1593 p
->context
.dataout
= readl_relaxed(base
+ regs
->dataout
);
1595 p
->context_valid
= true;
1598 static void omap_gpio_restore_context(struct gpio_bank
*bank
)
1600 writel_relaxed(bank
->context
.wake_en
,
1601 bank
->base
+ bank
->regs
->wkup_en
);
1602 writel_relaxed(bank
->context
.ctrl
, bank
->base
+ bank
->regs
->ctrl
);
1603 writel_relaxed(bank
->context
.leveldetect0
,
1604 bank
->base
+ bank
->regs
->leveldetect0
);
1605 writel_relaxed(bank
->context
.leveldetect1
,
1606 bank
->base
+ bank
->regs
->leveldetect1
);
1607 writel_relaxed(bank
->context
.risingdetect
,
1608 bank
->base
+ bank
->regs
->risingdetect
);
1609 writel_relaxed(bank
->context
.fallingdetect
,
1610 bank
->base
+ bank
->regs
->fallingdetect
);
1611 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
)
1612 writel_relaxed(bank
->context
.dataout
,
1613 bank
->base
+ bank
->regs
->set_dataout
);
1615 writel_relaxed(bank
->context
.dataout
,
1616 bank
->base
+ bank
->regs
->dataout
);
1617 writel_relaxed(bank
->context
.oe
, bank
->base
+ bank
->regs
->direction
);
1619 if (bank
->dbck_enable_mask
) {
1620 writel_relaxed(bank
->context
.debounce
, bank
->base
+
1621 bank
->regs
->debounce
);
1622 writel_relaxed(bank
->context
.debounce_en
,
1623 bank
->base
+ bank
->regs
->debounce_en
);
1626 writel_relaxed(bank
->context
.irqenable1
,
1627 bank
->base
+ bank
->regs
->irqenable
);
1628 writel_relaxed(bank
->context
.irqenable2
,
1629 bank
->base
+ bank
->regs
->irqenable2
);
1632 static int __maybe_unused
omap_gpio_runtime_suspend(struct device
*dev
)
1634 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
1635 unsigned long flags
;
1638 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1639 /* Must be idled only by CPU_CLUSTER_PM_ENTER? */
1640 if (bank
->irq_usage
) {
1644 omap_gpio_idle(bank
, true);
1645 bank
->is_suspended
= true;
1647 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1652 static int __maybe_unused
omap_gpio_runtime_resume(struct device
*dev
)
1654 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
1655 unsigned long flags
;
1658 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1659 /* Must be unidled only by CPU_CLUSTER_PM_ENTER? */
1660 if (bank
->irq_usage
) {
1664 omap_gpio_unidle(bank
);
1665 bank
->is_suspended
= false;
1667 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1672 #ifdef CONFIG_ARCH_OMAP2PLUS
1673 static const struct dev_pm_ops gpio_pm_ops
= {
1674 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend
, omap_gpio_runtime_resume
,
1678 static const struct dev_pm_ops gpio_pm_ops
;
1679 #endif /* CONFIG_ARCH_OMAP2PLUS */
1681 #if defined(CONFIG_OF)
1682 static struct omap_gpio_reg_offs omap2_gpio_regs
= {
1683 .revision
= OMAP24XX_GPIO_REVISION
,
1684 .direction
= OMAP24XX_GPIO_OE
,
1685 .datain
= OMAP24XX_GPIO_DATAIN
,
1686 .dataout
= OMAP24XX_GPIO_DATAOUT
,
1687 .set_dataout
= OMAP24XX_GPIO_SETDATAOUT
,
1688 .clr_dataout
= OMAP24XX_GPIO_CLEARDATAOUT
,
1689 .irqstatus
= OMAP24XX_GPIO_IRQSTATUS1
,
1690 .irqstatus2
= OMAP24XX_GPIO_IRQSTATUS2
,
1691 .irqenable
= OMAP24XX_GPIO_IRQENABLE1
,
1692 .irqenable2
= OMAP24XX_GPIO_IRQENABLE2
,
1693 .set_irqenable
= OMAP24XX_GPIO_SETIRQENABLE1
,
1694 .clr_irqenable
= OMAP24XX_GPIO_CLEARIRQENABLE1
,
1695 .debounce
= OMAP24XX_GPIO_DEBOUNCE_VAL
,
1696 .debounce_en
= OMAP24XX_GPIO_DEBOUNCE_EN
,
1697 .ctrl
= OMAP24XX_GPIO_CTRL
,
1698 .wkup_en
= OMAP24XX_GPIO_WAKE_EN
,
1699 .leveldetect0
= OMAP24XX_GPIO_LEVELDETECT0
,
1700 .leveldetect1
= OMAP24XX_GPIO_LEVELDETECT1
,
1701 .risingdetect
= OMAP24XX_GPIO_RISINGDETECT
,
1702 .fallingdetect
= OMAP24XX_GPIO_FALLINGDETECT
,
1705 static struct omap_gpio_reg_offs omap4_gpio_regs
= {
1706 .revision
= OMAP4_GPIO_REVISION
,
1707 .direction
= OMAP4_GPIO_OE
,
1708 .datain
= OMAP4_GPIO_DATAIN
,
1709 .dataout
= OMAP4_GPIO_DATAOUT
,
1710 .set_dataout
= OMAP4_GPIO_SETDATAOUT
,
1711 .clr_dataout
= OMAP4_GPIO_CLEARDATAOUT
,
1712 .irqstatus
= OMAP4_GPIO_IRQSTATUS0
,
1713 .irqstatus2
= OMAP4_GPIO_IRQSTATUS1
,
1714 .irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1715 .irqenable2
= OMAP4_GPIO_IRQSTATUSSET1
,
1716 .set_irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1717 .clr_irqenable
= OMAP4_GPIO_IRQSTATUSCLR0
,
1718 .debounce
= OMAP4_GPIO_DEBOUNCINGTIME
,
1719 .debounce_en
= OMAP4_GPIO_DEBOUNCENABLE
,
1720 .ctrl
= OMAP4_GPIO_CTRL
,
1721 .wkup_en
= OMAP4_GPIO_IRQWAKEN0
,
1722 .leveldetect0
= OMAP4_GPIO_LEVELDETECT0
,
1723 .leveldetect1
= OMAP4_GPIO_LEVELDETECT1
,
1724 .risingdetect
= OMAP4_GPIO_RISINGDETECT
,
1725 .fallingdetect
= OMAP4_GPIO_FALLINGDETECT
,
1729 * Note that omap2 does not currently support idle modes with context loss so
1730 * no need to add OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER quirk flag to save
1731 * and restore context.
1733 static const struct omap_gpio_platform_data omap2_pdata
= {
1734 .regs
= &omap2_gpio_regs
,
1739 static const struct omap_gpio_platform_data omap3_pdata
= {
1740 .regs
= &omap2_gpio_regs
,
1743 .quirks
= OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER
,
1746 static const struct omap_gpio_platform_data omap4_pdata
= {
1747 .regs
= &omap4_gpio_regs
,
1750 .quirks
= OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER
,
1753 static const struct of_device_id omap_gpio_match
[] = {
1755 .compatible
= "ti,omap4-gpio",
1756 .data
= &omap4_pdata
,
1759 .compatible
= "ti,omap3-gpio",
1760 .data
= &omap3_pdata
,
1763 .compatible
= "ti,omap2-gpio",
1764 .data
= &omap2_pdata
,
1768 MODULE_DEVICE_TABLE(of
, omap_gpio_match
);
1771 static struct platform_driver omap_gpio_driver
= {
1772 .probe
= omap_gpio_probe
,
1773 .remove
= omap_gpio_remove
,
1775 .name
= "omap_gpio",
1777 .of_match_table
= of_match_ptr(omap_gpio_match
),
1782 * gpio driver register needs to be done before
1783 * machine_init functions access gpio APIs.
1784 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1786 static int __init
omap_gpio_drv_reg(void)
1788 return platform_driver_register(&omap_gpio_driver
);
1790 postcore_initcall(omap_gpio_drv_reg
);
1792 static void __exit
omap_gpio_exit(void)
1794 platform_driver_unregister(&omap_gpio_driver
);
1796 module_exit(omap_gpio_exit
);
1798 MODULE_DESCRIPTION("omap gpio driver");
1799 MODULE_ALIAS("platform:gpio-omap");
1800 MODULE_LICENSE("GPL v2");