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[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-omap.c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
30
31 #define OFF_MODE 1
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33
34 static LIST_HEAD(omap_gpio_list);
35
36 struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49 };
50
51 struct gpio_bank {
52 struct list_head node;
53 void __iomem *base;
54 int irq;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 level_mask;
60 u32 toggle_mask;
61 raw_spinlock_t lock;
62 raw_spinlock_t wa_lock;
63 struct gpio_chip chip;
64 struct clk *dbck;
65 u32 mod_usage;
66 u32 irq_usage;
67 u32 dbck_enable_mask;
68 bool dbck_enabled;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 bool context_valid;
73 int stride;
74 u32 width;
75 int context_loss_count;
76 int power_mode;
77 bool workaround_enabled;
78
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
81
82 struct omap_gpio_reg_offs *regs;
83 };
84
85 #define GPIO_MOD_CTRL_BIT BIT(0)
86
87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88 #define LINE_USED(line, offset) (line & (BIT(offset)))
89
90 static void omap_gpio_unmask_irq(struct irq_data *d);
91
92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
93 {
94 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 return gpiochip_get_data(chip);
96 }
97
98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 int is_input)
100 {
101 void __iomem *reg = bank->base;
102 u32 l;
103
104 reg += bank->regs->direction;
105 l = readl_relaxed(reg);
106 if (is_input)
107 l |= BIT(gpio);
108 else
109 l &= ~(BIT(gpio));
110 writel_relaxed(l, reg);
111 bank->context.oe = l;
112 }
113
114
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 int enable)
118 {
119 void __iomem *reg = bank->base;
120 u32 l = BIT(offset);
121
122 if (enable) {
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
125 } else {
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
128 }
129
130 writel_relaxed(l, reg);
131 }
132
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 int enable)
136 {
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = BIT(offset);
139 u32 l;
140
141 l = readl_relaxed(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
146 writel_relaxed(l, reg);
147 bank->context.dataout = l;
148 }
149
150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
151 {
152 void __iomem *reg = bank->base + bank->regs->datain;
153
154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
155 }
156
157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
158 {
159 void __iomem *reg = bank->base + bank->regs->dataout;
160
161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
162 }
163
164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165 {
166 int l = readl_relaxed(base + reg);
167
168 if (set)
169 l |= mask;
170 else
171 l &= ~mask;
172
173 writel_relaxed(l, base + reg);
174 }
175
176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
177 {
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
181
182 writel_relaxed(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
184 }
185 }
186
187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
188 {
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
190 /*
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
194 */
195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
196
197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
199 }
200 }
201
202 /**
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
207 *
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
211 */
212 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
213 unsigned debounce)
214 {
215 void __iomem *reg;
216 u32 val;
217 u32 l;
218 bool enable = !!debounce;
219
220 if (!bank->dbck_flag)
221 return;
222
223 if (enable) {
224 debounce = DIV_ROUND_UP(debounce, 31) - 1;
225 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
226 }
227
228 l = BIT(offset);
229
230 clk_enable(bank->dbck);
231 reg = bank->base + bank->regs->debounce;
232 writel_relaxed(debounce, reg);
233
234 reg = bank->base + bank->regs->debounce_en;
235 val = readl_relaxed(reg);
236
237 if (enable)
238 val |= l;
239 else
240 val &= ~l;
241 bank->dbck_enable_mask = val;
242
243 writel_relaxed(val, reg);
244 clk_disable(bank->dbck);
245 /*
246 * Enable debounce clock per module.
247 * This call is mandatory because in omap_gpio_request() when
248 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
249 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 * used within _gpio_dbck_enable() is still not initialized at
251 * that point. Therefore we have to enable dbck here.
252 */
253 omap_gpio_dbck_enable(bank);
254 if (bank->dbck_enable_mask) {
255 bank->context.debounce = debounce;
256 bank->context.debounce_en = val;
257 }
258 }
259
260 /**
261 * omap_clear_gpio_debounce - clear debounce settings for a gpio
262 * @bank: the gpio bank we're acting upon
263 * @offset: the gpio number on this @bank
264 *
265 * If a gpio is using debounce, then clear the debounce enable bit and if
266 * this is the only gpio in this bank using debounce, then clear the debounce
267 * time too. The debounce clock will also be disabled when calling this function
268 * if this is the only gpio in the bank using debounce.
269 */
270 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
271 {
272 u32 gpio_bit = BIT(offset);
273
274 if (!bank->dbck_flag)
275 return;
276
277 if (!(bank->dbck_enable_mask & gpio_bit))
278 return;
279
280 bank->dbck_enable_mask &= ~gpio_bit;
281 bank->context.debounce_en &= ~gpio_bit;
282 writel_relaxed(bank->context.debounce_en,
283 bank->base + bank->regs->debounce_en);
284
285 if (!bank->dbck_enable_mask) {
286 bank->context.debounce = 0;
287 writel_relaxed(bank->context.debounce, bank->base +
288 bank->regs->debounce);
289 clk_disable(bank->dbck);
290 bank->dbck_enabled = false;
291 }
292 }
293
294 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
295 unsigned trigger)
296 {
297 void __iomem *base = bank->base;
298 u32 gpio_bit = BIT(gpio);
299
300 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
301 trigger & IRQ_TYPE_LEVEL_LOW);
302 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
303 trigger & IRQ_TYPE_LEVEL_HIGH);
304 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
305 trigger & IRQ_TYPE_EDGE_RISING);
306 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
307 trigger & IRQ_TYPE_EDGE_FALLING);
308
309 bank->context.leveldetect0 =
310 readl_relaxed(bank->base + bank->regs->leveldetect0);
311 bank->context.leveldetect1 =
312 readl_relaxed(bank->base + bank->regs->leveldetect1);
313 bank->context.risingdetect =
314 readl_relaxed(bank->base + bank->regs->risingdetect);
315 bank->context.fallingdetect =
316 readl_relaxed(bank->base + bank->regs->fallingdetect);
317
318 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
319 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
320 bank->context.wake_en =
321 readl_relaxed(bank->base + bank->regs->wkup_en);
322 }
323
324 /* This part needs to be executed always for OMAP{34xx, 44xx} */
325 if (!bank->regs->irqctrl) {
326 /* On omap24xx proceed only when valid GPIO bit is set */
327 if (bank->non_wakeup_gpios) {
328 if (!(bank->non_wakeup_gpios & gpio_bit))
329 goto exit;
330 }
331
332 /*
333 * Log the edge gpio and manually trigger the IRQ
334 * after resume if the input level changes
335 * to avoid irq lost during PER RET/OFF mode
336 * Applies for omap2 non-wakeup gpio and all omap3 gpios
337 */
338 if (trigger & IRQ_TYPE_EDGE_BOTH)
339 bank->enabled_non_wakeup_gpios |= gpio_bit;
340 else
341 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
342 }
343
344 exit:
345 bank->level_mask =
346 readl_relaxed(bank->base + bank->regs->leveldetect0) |
347 readl_relaxed(bank->base + bank->regs->leveldetect1);
348 }
349
350 #ifdef CONFIG_ARCH_OMAP1
351 /*
352 * This only applies to chips that can't do both rising and falling edge
353 * detection at once. For all other chips, this function is a noop.
354 */
355 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
356 {
357 void __iomem *reg = bank->base;
358 u32 l = 0;
359
360 if (!bank->regs->irqctrl)
361 return;
362
363 reg += bank->regs->irqctrl;
364
365 l = readl_relaxed(reg);
366 if ((l >> gpio) & 1)
367 l &= ~(BIT(gpio));
368 else
369 l |= BIT(gpio);
370
371 writel_relaxed(l, reg);
372 }
373 #else
374 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
375 #endif
376
377 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
378 unsigned trigger)
379 {
380 void __iomem *reg = bank->base;
381 void __iomem *base = bank->base;
382 u32 l = 0;
383
384 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
385 omap_set_gpio_trigger(bank, gpio, trigger);
386 } else if (bank->regs->irqctrl) {
387 reg += bank->regs->irqctrl;
388
389 l = readl_relaxed(reg);
390 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
391 bank->toggle_mask |= BIT(gpio);
392 if (trigger & IRQ_TYPE_EDGE_RISING)
393 l |= BIT(gpio);
394 else if (trigger & IRQ_TYPE_EDGE_FALLING)
395 l &= ~(BIT(gpio));
396 else
397 return -EINVAL;
398
399 writel_relaxed(l, reg);
400 } else if (bank->regs->edgectrl1) {
401 if (gpio & 0x08)
402 reg += bank->regs->edgectrl2;
403 else
404 reg += bank->regs->edgectrl1;
405
406 gpio &= 0x07;
407 l = readl_relaxed(reg);
408 l &= ~(3 << (gpio << 1));
409 if (trigger & IRQ_TYPE_EDGE_RISING)
410 l |= 2 << (gpio << 1);
411 if (trigger & IRQ_TYPE_EDGE_FALLING)
412 l |= BIT(gpio << 1);
413
414 /* Enable wake-up during idle for dynamic tick */
415 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
416 bank->context.wake_en =
417 readl_relaxed(bank->base + bank->regs->wkup_en);
418 writel_relaxed(l, reg);
419 }
420 return 0;
421 }
422
423 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
424 {
425 if (bank->regs->pinctrl) {
426 void __iomem *reg = bank->base + bank->regs->pinctrl;
427
428 /* Claim the pin for MPU */
429 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
430 }
431
432 if (bank->regs->ctrl && !BANK_USED(bank)) {
433 void __iomem *reg = bank->base + bank->regs->ctrl;
434 u32 ctrl;
435
436 ctrl = readl_relaxed(reg);
437 /* Module is enabled, clocks are not gated */
438 ctrl &= ~GPIO_MOD_CTRL_BIT;
439 writel_relaxed(ctrl, reg);
440 bank->context.ctrl = ctrl;
441 }
442 }
443
444 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
445 {
446 void __iomem *base = bank->base;
447
448 if (bank->regs->wkup_en &&
449 !LINE_USED(bank->mod_usage, offset) &&
450 !LINE_USED(bank->irq_usage, offset)) {
451 /* Disable wake-up during idle for dynamic tick */
452 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
453 bank->context.wake_en =
454 readl_relaxed(bank->base + bank->regs->wkup_en);
455 }
456
457 if (bank->regs->ctrl && !BANK_USED(bank)) {
458 void __iomem *reg = bank->base + bank->regs->ctrl;
459 u32 ctrl;
460
461 ctrl = readl_relaxed(reg);
462 /* Module is disabled, clocks are gated */
463 ctrl |= GPIO_MOD_CTRL_BIT;
464 writel_relaxed(ctrl, reg);
465 bank->context.ctrl = ctrl;
466 }
467 }
468
469 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
470 {
471 void __iomem *reg = bank->base + bank->regs->direction;
472
473 return readl_relaxed(reg) & BIT(offset);
474 }
475
476 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
477 {
478 if (!LINE_USED(bank->mod_usage, offset)) {
479 omap_enable_gpio_module(bank, offset);
480 omap_set_gpio_direction(bank, offset, 1);
481 }
482 bank->irq_usage |= BIT(offset);
483 }
484
485 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
486 {
487 struct gpio_bank *bank = omap_irq_data_get_bank(d);
488 int retval;
489 unsigned long flags;
490 unsigned offset = d->hwirq;
491
492 if (type & ~IRQ_TYPE_SENSE_MASK)
493 return -EINVAL;
494
495 if (!bank->regs->leveldetect0 &&
496 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
497 return -EINVAL;
498
499 raw_spin_lock_irqsave(&bank->lock, flags);
500 retval = omap_set_gpio_triggering(bank, offset, type);
501 if (retval) {
502 raw_spin_unlock_irqrestore(&bank->lock, flags);
503 goto error;
504 }
505 omap_gpio_init_irq(bank, offset);
506 if (!omap_gpio_is_input(bank, offset)) {
507 raw_spin_unlock_irqrestore(&bank->lock, flags);
508 retval = -EINVAL;
509 goto error;
510 }
511 raw_spin_unlock_irqrestore(&bank->lock, flags);
512
513 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
514 irq_set_handler_locked(d, handle_level_irq);
515 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
516 irq_set_handler_locked(d, handle_edge_irq);
517
518 return 0;
519
520 error:
521 return retval;
522 }
523
524 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
525 {
526 void __iomem *reg = bank->base;
527
528 reg += bank->regs->irqstatus;
529 writel_relaxed(gpio_mask, reg);
530
531 /* Workaround for clearing DSP GPIO interrupts to allow retention */
532 if (bank->regs->irqstatus2) {
533 reg = bank->base + bank->regs->irqstatus2;
534 writel_relaxed(gpio_mask, reg);
535 }
536
537 /* Flush posted write for the irq status to avoid spurious interrupts */
538 readl_relaxed(reg);
539 }
540
541 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
542 unsigned offset)
543 {
544 omap_clear_gpio_irqbank(bank, BIT(offset));
545 }
546
547 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
548 {
549 void __iomem *reg = bank->base;
550 u32 l;
551 u32 mask = (BIT(bank->width)) - 1;
552
553 reg += bank->regs->irqenable;
554 l = readl_relaxed(reg);
555 if (bank->regs->irqenable_inv)
556 l = ~l;
557 l &= mask;
558 return l;
559 }
560
561 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
562 {
563 void __iomem *reg = bank->base;
564 u32 l;
565
566 if (bank->regs->set_irqenable) {
567 reg += bank->regs->set_irqenable;
568 l = gpio_mask;
569 bank->context.irqenable1 |= gpio_mask;
570 } else {
571 reg += bank->regs->irqenable;
572 l = readl_relaxed(reg);
573 if (bank->regs->irqenable_inv)
574 l &= ~gpio_mask;
575 else
576 l |= gpio_mask;
577 bank->context.irqenable1 = l;
578 }
579
580 writel_relaxed(l, reg);
581 }
582
583 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
584 {
585 void __iomem *reg = bank->base;
586 u32 l;
587
588 if (bank->regs->clr_irqenable) {
589 reg += bank->regs->clr_irqenable;
590 l = gpio_mask;
591 bank->context.irqenable1 &= ~gpio_mask;
592 } else {
593 reg += bank->regs->irqenable;
594 l = readl_relaxed(reg);
595 if (bank->regs->irqenable_inv)
596 l |= gpio_mask;
597 else
598 l &= ~gpio_mask;
599 bank->context.irqenable1 = l;
600 }
601
602 writel_relaxed(l, reg);
603 }
604
605 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
606 unsigned offset, int enable)
607 {
608 if (enable)
609 omap_enable_gpio_irqbank(bank, BIT(offset));
610 else
611 omap_disable_gpio_irqbank(bank, BIT(offset));
612 }
613
614 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
615 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
616 {
617 struct gpio_bank *bank = omap_irq_data_get_bank(d);
618
619 return irq_set_irq_wake(bank->irq, enable);
620 }
621
622 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
623 {
624 struct gpio_bank *bank = gpiochip_get_data(chip);
625 unsigned long flags;
626
627 /*
628 * If this is the first gpio_request for the bank,
629 * enable the bank module.
630 */
631 if (!BANK_USED(bank))
632 pm_runtime_get_sync(chip->parent);
633
634 raw_spin_lock_irqsave(&bank->lock, flags);
635 omap_enable_gpio_module(bank, offset);
636 bank->mod_usage |= BIT(offset);
637 raw_spin_unlock_irqrestore(&bank->lock, flags);
638
639 return 0;
640 }
641
642 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
643 {
644 struct gpio_bank *bank = gpiochip_get_data(chip);
645 unsigned long flags;
646
647 raw_spin_lock_irqsave(&bank->lock, flags);
648 bank->mod_usage &= ~(BIT(offset));
649 if (!LINE_USED(bank->irq_usage, offset)) {
650 omap_set_gpio_direction(bank, offset, 1);
651 omap_clear_gpio_debounce(bank, offset);
652 }
653 omap_disable_gpio_module(bank, offset);
654 raw_spin_unlock_irqrestore(&bank->lock, flags);
655
656 /*
657 * If this is the last gpio to be freed in the bank,
658 * disable the bank module.
659 */
660 if (!BANK_USED(bank))
661 pm_runtime_put(chip->parent);
662 }
663
664 /*
665 * We need to unmask the GPIO bank interrupt as soon as possible to
666 * avoid missing GPIO interrupts for other lines in the bank.
667 * Then we need to mask-read-clear-unmask the triggered GPIO lines
668 * in the bank to avoid missing nested interrupts for a GPIO line.
669 * If we wait to unmask individual GPIO lines in the bank after the
670 * line's interrupt handler has been run, we may miss some nested
671 * interrupts.
672 */
673 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
674 {
675 void __iomem *isr_reg = NULL;
676 u32 isr;
677 unsigned int bit;
678 struct gpio_bank *bank = gpiobank;
679 unsigned long wa_lock_flags;
680 unsigned long lock_flags;
681
682 isr_reg = bank->base + bank->regs->irqstatus;
683 if (WARN_ON(!isr_reg))
684 goto exit;
685
686 pm_runtime_get_sync(bank->chip.parent);
687
688 while (1) {
689 u32 isr_saved, level_mask = 0;
690 u32 enabled;
691
692 raw_spin_lock_irqsave(&bank->lock, lock_flags);
693
694 enabled = omap_get_gpio_irqbank_mask(bank);
695 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
696
697 if (bank->level_mask)
698 level_mask = bank->level_mask & enabled;
699
700 /* clear edge sensitive interrupts before handler(s) are
701 called so that we don't miss any interrupt occurred while
702 executing them */
703 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
704 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
705 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
706
707 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
708
709 if (!isr)
710 break;
711
712 while (isr) {
713 bit = __ffs(isr);
714 isr &= ~(BIT(bit));
715
716 raw_spin_lock_irqsave(&bank->lock, lock_flags);
717 /*
718 * Some chips can't respond to both rising and falling
719 * at the same time. If this irq was requested with
720 * both flags, we need to flip the ICR data for the IRQ
721 * to respond to the IRQ for the opposite direction.
722 * This will be indicated in the bank toggle_mask.
723 */
724 if (bank->toggle_mask & (BIT(bit)))
725 omap_toggle_gpio_edge_triggering(bank, bit);
726
727 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
728
729 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
730
731 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
732 bit));
733
734 raw_spin_unlock_irqrestore(&bank->wa_lock,
735 wa_lock_flags);
736 }
737 }
738 exit:
739 pm_runtime_put(bank->chip.parent);
740 return IRQ_HANDLED;
741 }
742
743 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
744 {
745 struct gpio_bank *bank = omap_irq_data_get_bank(d);
746 unsigned long flags;
747 unsigned offset = d->hwirq;
748
749 raw_spin_lock_irqsave(&bank->lock, flags);
750
751 if (!LINE_USED(bank->mod_usage, offset))
752 omap_set_gpio_direction(bank, offset, 1);
753 else if (!omap_gpio_is_input(bank, offset))
754 goto err;
755 omap_enable_gpio_module(bank, offset);
756 bank->irq_usage |= BIT(offset);
757
758 raw_spin_unlock_irqrestore(&bank->lock, flags);
759 omap_gpio_unmask_irq(d);
760
761 return 0;
762 err:
763 raw_spin_unlock_irqrestore(&bank->lock, flags);
764 return -EINVAL;
765 }
766
767 static void omap_gpio_irq_shutdown(struct irq_data *d)
768 {
769 struct gpio_bank *bank = omap_irq_data_get_bank(d);
770 unsigned long flags;
771 unsigned offset = d->hwirq;
772
773 raw_spin_lock_irqsave(&bank->lock, flags);
774 bank->irq_usage &= ~(BIT(offset));
775 omap_set_gpio_irqenable(bank, offset, 0);
776 omap_clear_gpio_irqstatus(bank, offset);
777 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
778 if (!LINE_USED(bank->mod_usage, offset))
779 omap_clear_gpio_debounce(bank, offset);
780 omap_disable_gpio_module(bank, offset);
781 raw_spin_unlock_irqrestore(&bank->lock, flags);
782 }
783
784 static void omap_gpio_irq_bus_lock(struct irq_data *data)
785 {
786 struct gpio_bank *bank = omap_irq_data_get_bank(data);
787
788 if (!BANK_USED(bank))
789 pm_runtime_get_sync(bank->chip.parent);
790 }
791
792 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
793 {
794 struct gpio_bank *bank = omap_irq_data_get_bank(data);
795
796 /*
797 * If this is the last IRQ to be freed in the bank,
798 * disable the bank module.
799 */
800 if (!BANK_USED(bank))
801 pm_runtime_put(bank->chip.parent);
802 }
803
804 static void omap_gpio_ack_irq(struct irq_data *d)
805 {
806 struct gpio_bank *bank = omap_irq_data_get_bank(d);
807 unsigned offset = d->hwirq;
808
809 omap_clear_gpio_irqstatus(bank, offset);
810 }
811
812 static void omap_gpio_mask_irq(struct irq_data *d)
813 {
814 struct gpio_bank *bank = omap_irq_data_get_bank(d);
815 unsigned offset = d->hwirq;
816 unsigned long flags;
817
818 raw_spin_lock_irqsave(&bank->lock, flags);
819 omap_set_gpio_irqenable(bank, offset, 0);
820 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
821 raw_spin_unlock_irqrestore(&bank->lock, flags);
822 }
823
824 static void omap_gpio_unmask_irq(struct irq_data *d)
825 {
826 struct gpio_bank *bank = omap_irq_data_get_bank(d);
827 unsigned offset = d->hwirq;
828 u32 trigger = irqd_get_trigger_type(d);
829 unsigned long flags;
830
831 raw_spin_lock_irqsave(&bank->lock, flags);
832 if (trigger)
833 omap_set_gpio_triggering(bank, offset, trigger);
834
835 /* For level-triggered GPIOs, the clearing must be done after
836 * the HW source is cleared, thus after the handler has run */
837 if (bank->level_mask & BIT(offset)) {
838 omap_set_gpio_irqenable(bank, offset, 0);
839 omap_clear_gpio_irqstatus(bank, offset);
840 }
841
842 omap_set_gpio_irqenable(bank, offset, 1);
843 raw_spin_unlock_irqrestore(&bank->lock, flags);
844 }
845
846 /*---------------------------------------------------------------------*/
847
848 static int omap_mpuio_suspend_noirq(struct device *dev)
849 {
850 struct platform_device *pdev = to_platform_device(dev);
851 struct gpio_bank *bank = platform_get_drvdata(pdev);
852 void __iomem *mask_reg = bank->base +
853 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
854 unsigned long flags;
855
856 raw_spin_lock_irqsave(&bank->lock, flags);
857 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
858 raw_spin_unlock_irqrestore(&bank->lock, flags);
859
860 return 0;
861 }
862
863 static int omap_mpuio_resume_noirq(struct device *dev)
864 {
865 struct platform_device *pdev = to_platform_device(dev);
866 struct gpio_bank *bank = platform_get_drvdata(pdev);
867 void __iomem *mask_reg = bank->base +
868 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
869 unsigned long flags;
870
871 raw_spin_lock_irqsave(&bank->lock, flags);
872 writel_relaxed(bank->context.wake_en, mask_reg);
873 raw_spin_unlock_irqrestore(&bank->lock, flags);
874
875 return 0;
876 }
877
878 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
879 .suspend_noirq = omap_mpuio_suspend_noirq,
880 .resume_noirq = omap_mpuio_resume_noirq,
881 };
882
883 /* use platform_driver for this. */
884 static struct platform_driver omap_mpuio_driver = {
885 .driver = {
886 .name = "mpuio",
887 .pm = &omap_mpuio_dev_pm_ops,
888 },
889 };
890
891 static struct platform_device omap_mpuio_device = {
892 .name = "mpuio",
893 .id = -1,
894 .dev = {
895 .driver = &omap_mpuio_driver.driver,
896 }
897 /* could list the /proc/iomem resources */
898 };
899
900 static inline void omap_mpuio_init(struct gpio_bank *bank)
901 {
902 platform_set_drvdata(&omap_mpuio_device, bank);
903
904 if (platform_driver_register(&omap_mpuio_driver) == 0)
905 (void) platform_device_register(&omap_mpuio_device);
906 }
907
908 /*---------------------------------------------------------------------*/
909
910 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
911 {
912 struct gpio_bank *bank;
913 unsigned long flags;
914 void __iomem *reg;
915 int dir;
916
917 bank = gpiochip_get_data(chip);
918 reg = bank->base + bank->regs->direction;
919 raw_spin_lock_irqsave(&bank->lock, flags);
920 dir = !!(readl_relaxed(reg) & BIT(offset));
921 raw_spin_unlock_irqrestore(&bank->lock, flags);
922 return dir;
923 }
924
925 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
926 {
927 struct gpio_bank *bank;
928 unsigned long flags;
929
930 bank = gpiochip_get_data(chip);
931 raw_spin_lock_irqsave(&bank->lock, flags);
932 omap_set_gpio_direction(bank, offset, 1);
933 raw_spin_unlock_irqrestore(&bank->lock, flags);
934 return 0;
935 }
936
937 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
938 {
939 struct gpio_bank *bank;
940
941 bank = gpiochip_get_data(chip);
942
943 if (omap_gpio_is_input(bank, offset))
944 return omap_get_gpio_datain(bank, offset);
945 else
946 return omap_get_gpio_dataout(bank, offset);
947 }
948
949 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
950 {
951 struct gpio_bank *bank;
952 unsigned long flags;
953
954 bank = gpiochip_get_data(chip);
955 raw_spin_lock_irqsave(&bank->lock, flags);
956 bank->set_dataout(bank, offset, value);
957 omap_set_gpio_direction(bank, offset, 0);
958 raw_spin_unlock_irqrestore(&bank->lock, flags);
959 return 0;
960 }
961
962 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
963 unsigned debounce)
964 {
965 struct gpio_bank *bank;
966 unsigned long flags;
967
968 bank = gpiochip_get_data(chip);
969
970 raw_spin_lock_irqsave(&bank->lock, flags);
971 omap2_set_gpio_debounce(bank, offset, debounce);
972 raw_spin_unlock_irqrestore(&bank->lock, flags);
973
974 return 0;
975 }
976
977 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
978 unsigned long config)
979 {
980 u32 debounce;
981
982 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
983 return -ENOTSUPP;
984
985 debounce = pinconf_to_config_argument(config);
986 return omap_gpio_debounce(chip, offset, debounce);
987 }
988
989 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
990 {
991 struct gpio_bank *bank;
992 unsigned long flags;
993
994 bank = gpiochip_get_data(chip);
995 raw_spin_lock_irqsave(&bank->lock, flags);
996 bank->set_dataout(bank, offset, value);
997 raw_spin_unlock_irqrestore(&bank->lock, flags);
998 }
999
1000 /*---------------------------------------------------------------------*/
1001
1002 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1003 {
1004 static bool called;
1005 u32 rev;
1006
1007 if (called || bank->regs->revision == USHRT_MAX)
1008 return;
1009
1010 rev = readw_relaxed(bank->base + bank->regs->revision);
1011 pr_info("OMAP GPIO hardware version %d.%d\n",
1012 (rev >> 4) & 0x0f, rev & 0x0f);
1013
1014 called = true;
1015 }
1016
1017 static void omap_gpio_mod_init(struct gpio_bank *bank)
1018 {
1019 void __iomem *base = bank->base;
1020 u32 l = 0xffffffff;
1021
1022 if (bank->width == 16)
1023 l = 0xffff;
1024
1025 if (bank->is_mpuio) {
1026 writel_relaxed(l, bank->base + bank->regs->irqenable);
1027 return;
1028 }
1029
1030 omap_gpio_rmw(base, bank->regs->irqenable, l,
1031 bank->regs->irqenable_inv);
1032 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1033 !bank->regs->irqenable_inv);
1034 if (bank->regs->debounce_en)
1035 writel_relaxed(0, base + bank->regs->debounce_en);
1036
1037 /* Save OE default value (0xffffffff) in the context */
1038 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1039 /* Initialize interface clk ungated, module enabled */
1040 if (bank->regs->ctrl)
1041 writel_relaxed(0, base + bank->regs->ctrl);
1042 }
1043
1044 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1045 {
1046 static int gpio;
1047 int irq_base = 0;
1048 int ret;
1049
1050 /*
1051 * REVISIT eventually switch from OMAP-specific gpio structs
1052 * over to the generic ones
1053 */
1054 bank->chip.request = omap_gpio_request;
1055 bank->chip.free = omap_gpio_free;
1056 bank->chip.get_direction = omap_gpio_get_direction;
1057 bank->chip.direction_input = omap_gpio_input;
1058 bank->chip.get = omap_gpio_get;
1059 bank->chip.direction_output = omap_gpio_output;
1060 bank->chip.set_config = omap_gpio_set_config;
1061 bank->chip.set = omap_gpio_set;
1062 if (bank->is_mpuio) {
1063 bank->chip.label = "mpuio";
1064 if (bank->regs->wkup_en)
1065 bank->chip.parent = &omap_mpuio_device.dev;
1066 bank->chip.base = OMAP_MPUIO(0);
1067 } else {
1068 bank->chip.label = "gpio";
1069 bank->chip.base = gpio;
1070 }
1071 bank->chip.ngpio = bank->width;
1072
1073 ret = gpiochip_add_data(&bank->chip, bank);
1074 if (ret) {
1075 dev_err(bank->chip.parent,
1076 "Could not register gpio chip %d\n", ret);
1077 return ret;
1078 }
1079
1080 if (!bank->is_mpuio)
1081 gpio += bank->width;
1082
1083 #ifdef CONFIG_ARCH_OMAP1
1084 /*
1085 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1086 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1087 */
1088 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1089 if (irq_base < 0) {
1090 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1091 return -ENODEV;
1092 }
1093 #endif
1094
1095 /* MPUIO is a bit different, reading IRQ status clears it */
1096 if (bank->is_mpuio) {
1097 irqc->irq_ack = dummy_irq_chip.irq_ack;
1098 if (!bank->regs->wkup_en)
1099 irqc->irq_set_wake = NULL;
1100 }
1101
1102 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1103 irq_base, handle_bad_irq,
1104 IRQ_TYPE_NONE);
1105
1106 if (ret) {
1107 dev_err(bank->chip.parent,
1108 "Couldn't add irqchip to gpiochip %d\n", ret);
1109 gpiochip_remove(&bank->chip);
1110 return -ENODEV;
1111 }
1112
1113 gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1114
1115 ret = devm_request_irq(bank->chip.parent, bank->irq,
1116 omap_gpio_irq_handler,
1117 0, dev_name(bank->chip.parent), bank);
1118 if (ret)
1119 gpiochip_remove(&bank->chip);
1120
1121 return ret;
1122 }
1123
1124 static const struct of_device_id omap_gpio_match[];
1125
1126 static int omap_gpio_probe(struct platform_device *pdev)
1127 {
1128 struct device *dev = &pdev->dev;
1129 struct device_node *node = dev->of_node;
1130 const struct of_device_id *match;
1131 const struct omap_gpio_platform_data *pdata;
1132 struct resource *res;
1133 struct gpio_bank *bank;
1134 struct irq_chip *irqc;
1135 int ret;
1136
1137 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1138
1139 pdata = match ? match->data : dev_get_platdata(dev);
1140 if (!pdata)
1141 return -EINVAL;
1142
1143 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1144 if (!bank) {
1145 dev_err(dev, "Memory alloc failed\n");
1146 return -ENOMEM;
1147 }
1148
1149 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1150 if (!irqc)
1151 return -ENOMEM;
1152
1153 irqc->irq_startup = omap_gpio_irq_startup,
1154 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1155 irqc->irq_ack = omap_gpio_ack_irq,
1156 irqc->irq_mask = omap_gpio_mask_irq,
1157 irqc->irq_unmask = omap_gpio_unmask_irq,
1158 irqc->irq_set_type = omap_gpio_irq_type,
1159 irqc->irq_set_wake = omap_gpio_wake_enable,
1160 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1161 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1162 irqc->name = dev_name(&pdev->dev);
1163 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1164
1165 bank->irq = platform_get_irq(pdev, 0);
1166 if (bank->irq <= 0) {
1167 if (!bank->irq)
1168 bank->irq = -ENXIO;
1169 if (bank->irq != -EPROBE_DEFER)
1170 dev_err(dev,
1171 "can't get irq resource ret=%d\n", bank->irq);
1172 return bank->irq;
1173 }
1174
1175 bank->chip.parent = dev;
1176 bank->chip.owner = THIS_MODULE;
1177 bank->dbck_flag = pdata->dbck_flag;
1178 bank->stride = pdata->bank_stride;
1179 bank->width = pdata->bank_width;
1180 bank->is_mpuio = pdata->is_mpuio;
1181 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1182 bank->regs = pdata->regs;
1183 #ifdef CONFIG_OF_GPIO
1184 bank->chip.of_node = of_node_get(node);
1185 #endif
1186 if (node) {
1187 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1188 bank->loses_context = true;
1189 } else {
1190 bank->loses_context = pdata->loses_context;
1191
1192 if (bank->loses_context)
1193 bank->get_context_loss_count =
1194 pdata->get_context_loss_count;
1195 }
1196
1197 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1198 bank->set_dataout = omap_set_gpio_dataout_reg;
1199 else
1200 bank->set_dataout = omap_set_gpio_dataout_mask;
1201
1202 raw_spin_lock_init(&bank->lock);
1203 raw_spin_lock_init(&bank->wa_lock);
1204
1205 /* Static mapping, never released */
1206 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207 bank->base = devm_ioremap_resource(dev, res);
1208 if (IS_ERR(bank->base)) {
1209 return PTR_ERR(bank->base);
1210 }
1211
1212 if (bank->dbck_flag) {
1213 bank->dbck = devm_clk_get(dev, "dbclk");
1214 if (IS_ERR(bank->dbck)) {
1215 dev_err(dev,
1216 "Could not get gpio dbck. Disable debounce\n");
1217 bank->dbck_flag = false;
1218 } else {
1219 clk_prepare(bank->dbck);
1220 }
1221 }
1222
1223 platform_set_drvdata(pdev, bank);
1224
1225 pm_runtime_enable(dev);
1226 pm_runtime_irq_safe(dev);
1227 pm_runtime_get_sync(dev);
1228
1229 if (bank->is_mpuio)
1230 omap_mpuio_init(bank);
1231
1232 omap_gpio_mod_init(bank);
1233
1234 ret = omap_gpio_chip_init(bank, irqc);
1235 if (ret) {
1236 pm_runtime_put_sync(dev);
1237 pm_runtime_disable(dev);
1238 return ret;
1239 }
1240
1241 omap_gpio_show_rev(bank);
1242
1243 pm_runtime_put(dev);
1244
1245 list_add_tail(&bank->node, &omap_gpio_list);
1246
1247 return 0;
1248 }
1249
1250 static int omap_gpio_remove(struct platform_device *pdev)
1251 {
1252 struct gpio_bank *bank = platform_get_drvdata(pdev);
1253
1254 list_del(&bank->node);
1255 gpiochip_remove(&bank->chip);
1256 pm_runtime_disable(&pdev->dev);
1257 if (bank->dbck_flag)
1258 clk_unprepare(bank->dbck);
1259
1260 return 0;
1261 }
1262
1263 #ifdef CONFIG_ARCH_OMAP2PLUS
1264
1265 #if defined(CONFIG_PM)
1266 static void omap_gpio_restore_context(struct gpio_bank *bank);
1267
1268 static int omap_gpio_runtime_suspend(struct device *dev)
1269 {
1270 struct platform_device *pdev = to_platform_device(dev);
1271 struct gpio_bank *bank = platform_get_drvdata(pdev);
1272 u32 l1 = 0, l2 = 0;
1273 unsigned long flags;
1274 u32 wake_low, wake_hi;
1275
1276 raw_spin_lock_irqsave(&bank->lock, flags);
1277
1278 /*
1279 * Only edges can generate a wakeup event to the PRCM.
1280 *
1281 * Therefore, ensure any wake-up capable GPIOs have
1282 * edge-detection enabled before going idle to ensure a wakeup
1283 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1284 * NDA TRM 25.5.3.1)
1285 *
1286 * The normal values will be restored upon ->runtime_resume()
1287 * by writing back the values saved in bank->context.
1288 */
1289 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1290 if (wake_low)
1291 writel_relaxed(wake_low | bank->context.fallingdetect,
1292 bank->base + bank->regs->fallingdetect);
1293 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1294 if (wake_hi)
1295 writel_relaxed(wake_hi | bank->context.risingdetect,
1296 bank->base + bank->regs->risingdetect);
1297
1298 if (!bank->enabled_non_wakeup_gpios)
1299 goto update_gpio_context_count;
1300
1301 if (bank->power_mode != OFF_MODE) {
1302 bank->power_mode = 0;
1303 goto update_gpio_context_count;
1304 }
1305 /*
1306 * If going to OFF, remove triggering for all
1307 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1308 * generated. See OMAP2420 Errata item 1.101.
1309 */
1310 bank->saved_datain = readl_relaxed(bank->base +
1311 bank->regs->datain);
1312 l1 = bank->context.fallingdetect;
1313 l2 = bank->context.risingdetect;
1314
1315 l1 &= ~bank->enabled_non_wakeup_gpios;
1316 l2 &= ~bank->enabled_non_wakeup_gpios;
1317
1318 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1319 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1320
1321 bank->workaround_enabled = true;
1322
1323 update_gpio_context_count:
1324 if (bank->get_context_loss_count)
1325 bank->context_loss_count =
1326 bank->get_context_loss_count(dev);
1327
1328 omap_gpio_dbck_disable(bank);
1329 raw_spin_unlock_irqrestore(&bank->lock, flags);
1330
1331 return 0;
1332 }
1333
1334 static void omap_gpio_init_context(struct gpio_bank *p);
1335
1336 static int omap_gpio_runtime_resume(struct device *dev)
1337 {
1338 struct platform_device *pdev = to_platform_device(dev);
1339 struct gpio_bank *bank = platform_get_drvdata(pdev);
1340 u32 l = 0, gen, gen0, gen1;
1341 unsigned long flags;
1342 int c;
1343
1344 raw_spin_lock_irqsave(&bank->lock, flags);
1345
1346 /*
1347 * On the first resume during the probe, the context has not
1348 * been initialised and so initialise it now. Also initialise
1349 * the context loss count.
1350 */
1351 if (bank->loses_context && !bank->context_valid) {
1352 omap_gpio_init_context(bank);
1353
1354 if (bank->get_context_loss_count)
1355 bank->context_loss_count =
1356 bank->get_context_loss_count(dev);
1357 }
1358
1359 omap_gpio_dbck_enable(bank);
1360
1361 /*
1362 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1363 * GPIOs were set to edge trigger also in order to be able to
1364 * generate a PRCM wakeup. Here we restore the
1365 * pre-runtime_suspend() values for edge triggering.
1366 */
1367 writel_relaxed(bank->context.fallingdetect,
1368 bank->base + bank->regs->fallingdetect);
1369 writel_relaxed(bank->context.risingdetect,
1370 bank->base + bank->regs->risingdetect);
1371
1372 if (bank->loses_context) {
1373 if (!bank->get_context_loss_count) {
1374 omap_gpio_restore_context(bank);
1375 } else {
1376 c = bank->get_context_loss_count(dev);
1377 if (c != bank->context_loss_count) {
1378 omap_gpio_restore_context(bank);
1379 } else {
1380 raw_spin_unlock_irqrestore(&bank->lock, flags);
1381 return 0;
1382 }
1383 }
1384 }
1385
1386 if (!bank->workaround_enabled) {
1387 raw_spin_unlock_irqrestore(&bank->lock, flags);
1388 return 0;
1389 }
1390
1391 l = readl_relaxed(bank->base + bank->regs->datain);
1392
1393 /*
1394 * Check if any of the non-wakeup interrupt GPIOs have changed
1395 * state. If so, generate an IRQ by software. This is
1396 * horribly racy, but it's the best we can do to work around
1397 * this silicon bug.
1398 */
1399 l ^= bank->saved_datain;
1400 l &= bank->enabled_non_wakeup_gpios;
1401
1402 /*
1403 * No need to generate IRQs for the rising edge for gpio IRQs
1404 * configured with falling edge only; and vice versa.
1405 */
1406 gen0 = l & bank->context.fallingdetect;
1407 gen0 &= bank->saved_datain;
1408
1409 gen1 = l & bank->context.risingdetect;
1410 gen1 &= ~(bank->saved_datain);
1411
1412 /* FIXME: Consider GPIO IRQs with level detections properly! */
1413 gen = l & (~(bank->context.fallingdetect) &
1414 ~(bank->context.risingdetect));
1415 /* Consider all GPIO IRQs needed to be updated */
1416 gen |= gen0 | gen1;
1417
1418 if (gen) {
1419 u32 old0, old1;
1420
1421 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1422 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1423
1424 if (!bank->regs->irqstatus_raw0) {
1425 writel_relaxed(old0 | gen, bank->base +
1426 bank->regs->leveldetect0);
1427 writel_relaxed(old1 | gen, bank->base +
1428 bank->regs->leveldetect1);
1429 }
1430
1431 if (bank->regs->irqstatus_raw0) {
1432 writel_relaxed(old0 | l, bank->base +
1433 bank->regs->leveldetect0);
1434 writel_relaxed(old1 | l, bank->base +
1435 bank->regs->leveldetect1);
1436 }
1437 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1438 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1439 }
1440
1441 bank->workaround_enabled = false;
1442 raw_spin_unlock_irqrestore(&bank->lock, flags);
1443
1444 return 0;
1445 }
1446 #endif /* CONFIG_PM */
1447
1448 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1449 void omap2_gpio_prepare_for_idle(int pwr_mode)
1450 {
1451 struct gpio_bank *bank;
1452
1453 list_for_each_entry(bank, &omap_gpio_list, node) {
1454 if (!BANK_USED(bank) || !bank->loses_context)
1455 continue;
1456
1457 bank->power_mode = pwr_mode;
1458
1459 pm_runtime_put_sync_suspend(bank->chip.parent);
1460 }
1461 }
1462
1463 void omap2_gpio_resume_after_idle(void)
1464 {
1465 struct gpio_bank *bank;
1466
1467 list_for_each_entry(bank, &omap_gpio_list, node) {
1468 if (!BANK_USED(bank) || !bank->loses_context)
1469 continue;
1470
1471 pm_runtime_get_sync(bank->chip.parent);
1472 }
1473 }
1474 #endif
1475
1476 #if defined(CONFIG_PM)
1477 static void omap_gpio_init_context(struct gpio_bank *p)
1478 {
1479 struct omap_gpio_reg_offs *regs = p->regs;
1480 void __iomem *base = p->base;
1481
1482 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1483 p->context.oe = readl_relaxed(base + regs->direction);
1484 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1485 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1486 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1487 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1488 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1489 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1490 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1491
1492 if (regs->set_dataout && p->regs->clr_dataout)
1493 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1494 else
1495 p->context.dataout = readl_relaxed(base + regs->dataout);
1496
1497 p->context_valid = true;
1498 }
1499
1500 static void omap_gpio_restore_context(struct gpio_bank *bank)
1501 {
1502 writel_relaxed(bank->context.wake_en,
1503 bank->base + bank->regs->wkup_en);
1504 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1505 writel_relaxed(bank->context.leveldetect0,
1506 bank->base + bank->regs->leveldetect0);
1507 writel_relaxed(bank->context.leveldetect1,
1508 bank->base + bank->regs->leveldetect1);
1509 writel_relaxed(bank->context.risingdetect,
1510 bank->base + bank->regs->risingdetect);
1511 writel_relaxed(bank->context.fallingdetect,
1512 bank->base + bank->regs->fallingdetect);
1513 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1514 writel_relaxed(bank->context.dataout,
1515 bank->base + bank->regs->set_dataout);
1516 else
1517 writel_relaxed(bank->context.dataout,
1518 bank->base + bank->regs->dataout);
1519 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1520
1521 if (bank->dbck_enable_mask) {
1522 writel_relaxed(bank->context.debounce, bank->base +
1523 bank->regs->debounce);
1524 writel_relaxed(bank->context.debounce_en,
1525 bank->base + bank->regs->debounce_en);
1526 }
1527
1528 writel_relaxed(bank->context.irqenable1,
1529 bank->base + bank->regs->irqenable);
1530 writel_relaxed(bank->context.irqenable2,
1531 bank->base + bank->regs->irqenable2);
1532 }
1533 #endif /* CONFIG_PM */
1534 #else
1535 #define omap_gpio_runtime_suspend NULL
1536 #define omap_gpio_runtime_resume NULL
1537 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1538 #endif
1539
1540 static const struct dev_pm_ops gpio_pm_ops = {
1541 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1542 NULL)
1543 };
1544
1545 #if defined(CONFIG_OF)
1546 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1547 .revision = OMAP24XX_GPIO_REVISION,
1548 .direction = OMAP24XX_GPIO_OE,
1549 .datain = OMAP24XX_GPIO_DATAIN,
1550 .dataout = OMAP24XX_GPIO_DATAOUT,
1551 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1552 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1553 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1554 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1555 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1556 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1557 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1558 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1559 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1560 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1561 .ctrl = OMAP24XX_GPIO_CTRL,
1562 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1563 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1564 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1565 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1566 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1567 };
1568
1569 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1570 .revision = OMAP4_GPIO_REVISION,
1571 .direction = OMAP4_GPIO_OE,
1572 .datain = OMAP4_GPIO_DATAIN,
1573 .dataout = OMAP4_GPIO_DATAOUT,
1574 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1575 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1576 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1577 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1578 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1579 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1580 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1581 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1582 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1583 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1584 .ctrl = OMAP4_GPIO_CTRL,
1585 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1586 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1587 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1588 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1589 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1590 };
1591
1592 static const struct omap_gpio_platform_data omap2_pdata = {
1593 .regs = &omap2_gpio_regs,
1594 .bank_width = 32,
1595 .dbck_flag = false,
1596 };
1597
1598 static const struct omap_gpio_platform_data omap3_pdata = {
1599 .regs = &omap2_gpio_regs,
1600 .bank_width = 32,
1601 .dbck_flag = true,
1602 };
1603
1604 static const struct omap_gpio_platform_data omap4_pdata = {
1605 .regs = &omap4_gpio_regs,
1606 .bank_width = 32,
1607 .dbck_flag = true,
1608 };
1609
1610 static const struct of_device_id omap_gpio_match[] = {
1611 {
1612 .compatible = "ti,omap4-gpio",
1613 .data = &omap4_pdata,
1614 },
1615 {
1616 .compatible = "ti,omap3-gpio",
1617 .data = &omap3_pdata,
1618 },
1619 {
1620 .compatible = "ti,omap2-gpio",
1621 .data = &omap2_pdata,
1622 },
1623 { },
1624 };
1625 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1626 #endif
1627
1628 static struct platform_driver omap_gpio_driver = {
1629 .probe = omap_gpio_probe,
1630 .remove = omap_gpio_remove,
1631 .driver = {
1632 .name = "omap_gpio",
1633 .pm = &gpio_pm_ops,
1634 .of_match_table = of_match_ptr(omap_gpio_match),
1635 },
1636 };
1637
1638 /*
1639 * gpio driver register needs to be done before
1640 * machine_init functions access gpio APIs.
1641 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1642 */
1643 static int __init omap_gpio_drv_reg(void)
1644 {
1645 return platform_driver_register(&omap_gpio_driver);
1646 }
1647 postcore_initcall(omap_gpio_drv_reg);
1648
1649 static void __exit omap_gpio_exit(void)
1650 {
1651 platform_driver_unregister(&omap_gpio_driver);
1652 }
1653 module_exit(omap_gpio_exit);
1654
1655 MODULE_DESCRIPTION("omap gpio driver");
1656 MODULE_ALIAS("platform:gpio-omap");
1657 MODULE_LICENSE("GPL v2");
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