1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support functions for OMAP GPIO
5 * Copyright (C) 2003-2005 Nokia Corporation
6 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/syscore_ops.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/device.h>
21 #include <linux/pm_runtime.h>
24 #include <linux/of_device.h>
25 #include <linux/gpio/driver.h>
26 #include <linux/bitops.h>
27 #include <linux/platform_data/gpio-omap.h>
29 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
48 const struct omap_gpio_reg_offs
*regs
;
52 u32 enabled_non_wakeup_gpios
;
53 struct gpio_regs context
;
58 raw_spinlock_t wa_lock
;
59 struct gpio_chip chip
;
61 struct notifier_block nb
;
62 unsigned int is_suspended
:1;
63 unsigned int needs_resume
:1;
74 int context_loss_count
;
76 void (*set_dataout
)(struct gpio_bank
*bank
, unsigned gpio
, int enable
);
77 int (*get_context_loss_count
)(struct device
*dev
);
80 #define GPIO_MOD_CTRL_BIT BIT(0)
82 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
83 #define LINE_USED(line, offset) (line & (BIT(offset)))
85 static void omap_gpio_unmask_irq(struct irq_data
*d
);
87 static inline struct gpio_bank
*omap_irq_data_get_bank(struct irq_data
*d
)
89 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
90 return gpiochip_get_data(chip
);
93 static inline u32
omap_gpio_rmw(void __iomem
*reg
, u32 mask
, bool set
)
95 u32 val
= readl_relaxed(reg
);
102 writel_relaxed(val
, reg
);
107 static void omap_set_gpio_direction(struct gpio_bank
*bank
, int gpio
,
110 bank
->context
.oe
= omap_gpio_rmw(bank
->base
+ bank
->regs
->direction
,
111 BIT(gpio
), is_input
);
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank
*bank
, unsigned offset
,
119 void __iomem
*reg
= bank
->base
;
123 reg
+= bank
->regs
->set_dataout
;
124 bank
->context
.dataout
|= l
;
126 reg
+= bank
->regs
->clr_dataout
;
127 bank
->context
.dataout
&= ~l
;
130 writel_relaxed(l
, reg
);
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank
*bank
, unsigned offset
,
137 bank
->context
.dataout
= omap_gpio_rmw(bank
->base
+ bank
->regs
->dataout
,
138 BIT(offset
), enable
);
141 static inline void omap_gpio_dbck_enable(struct gpio_bank
*bank
)
143 if (bank
->dbck_enable_mask
&& !bank
->dbck_enabled
) {
144 clk_enable(bank
->dbck
);
145 bank
->dbck_enabled
= true;
147 writel_relaxed(bank
->dbck_enable_mask
,
148 bank
->base
+ bank
->regs
->debounce_en
);
152 static inline void omap_gpio_dbck_disable(struct gpio_bank
*bank
)
154 if (bank
->dbck_enable_mask
&& bank
->dbck_enabled
) {
156 * Disable debounce before cutting it's clock. If debounce is
157 * enabled but the clock is not, GPIO module seems to be unable
158 * to detect events and generate interrupts at least on OMAP3.
160 writel_relaxed(0, bank
->base
+ bank
->regs
->debounce_en
);
162 clk_disable(bank
->dbck
);
163 bank
->dbck_enabled
= false;
168 * omap2_set_gpio_debounce - low level gpio debounce time
169 * @bank: the gpio bank we're acting upon
170 * @offset: the gpio number on this @bank
171 * @debounce: debounce time to use
173 * OMAP's debounce time is in 31us steps
174 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
175 * so we need to convert and round up to the closest unit.
177 * Return: 0 on success, negative error otherwise.
179 static int omap2_set_gpio_debounce(struct gpio_bank
*bank
, unsigned offset
,
184 bool enable
= !!debounce
;
186 if (!bank
->dbck_flag
)
190 debounce
= DIV_ROUND_UP(debounce
, 31) - 1;
191 if ((debounce
& OMAP4_GPIO_DEBOUNCINGTIME_MASK
) != debounce
)
197 clk_enable(bank
->dbck
);
198 writel_relaxed(debounce
, bank
->base
+ bank
->regs
->debounce
);
200 val
= omap_gpio_rmw(bank
->base
+ bank
->regs
->debounce_en
, l
, enable
);
201 bank
->dbck_enable_mask
= val
;
203 clk_disable(bank
->dbck
);
205 * Enable debounce clock per module.
206 * This call is mandatory because in omap_gpio_request() when
207 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
208 * runtime callbck fails to turn on dbck because dbck_enable_mask
209 * used within _gpio_dbck_enable() is still not initialized at
210 * that point. Therefore we have to enable dbck here.
212 omap_gpio_dbck_enable(bank
);
213 if (bank
->dbck_enable_mask
) {
214 bank
->context
.debounce
= debounce
;
215 bank
->context
.debounce_en
= val
;
222 * omap_clear_gpio_debounce - clear debounce settings for a gpio
223 * @bank: the gpio bank we're acting upon
224 * @offset: the gpio number on this @bank
226 * If a gpio is using debounce, then clear the debounce enable bit and if
227 * this is the only gpio in this bank using debounce, then clear the debounce
228 * time too. The debounce clock will also be disabled when calling this function
229 * if this is the only gpio in the bank using debounce.
231 static void omap_clear_gpio_debounce(struct gpio_bank
*bank
, unsigned offset
)
233 u32 gpio_bit
= BIT(offset
);
235 if (!bank
->dbck_flag
)
238 if (!(bank
->dbck_enable_mask
& gpio_bit
))
241 bank
->dbck_enable_mask
&= ~gpio_bit
;
242 bank
->context
.debounce_en
&= ~gpio_bit
;
243 writel_relaxed(bank
->context
.debounce_en
,
244 bank
->base
+ bank
->regs
->debounce_en
);
246 if (!bank
->dbck_enable_mask
) {
247 bank
->context
.debounce
= 0;
248 writel_relaxed(bank
->context
.debounce
, bank
->base
+
249 bank
->regs
->debounce
);
250 clk_disable(bank
->dbck
);
251 bank
->dbck_enabled
= false;
256 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
257 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
258 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
259 * are capable waking up the system from off mode.
261 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank
*bank
, u32 gpio_mask
)
263 u32 no_wake
= bank
->non_wakeup_gpios
;
266 return !!(~no_wake
& gpio_mask
);
271 static inline void omap_set_gpio_trigger(struct gpio_bank
*bank
, int gpio
,
274 void __iomem
*base
= bank
->base
;
275 u32 gpio_bit
= BIT(gpio
);
277 omap_gpio_rmw(base
+ bank
->regs
->leveldetect0
, gpio_bit
,
278 trigger
& IRQ_TYPE_LEVEL_LOW
);
279 omap_gpio_rmw(base
+ bank
->regs
->leveldetect1
, gpio_bit
,
280 trigger
& IRQ_TYPE_LEVEL_HIGH
);
283 * We need the edge detection enabled for to allow the GPIO block
284 * to be woken from idle state. Set the appropriate edge detection
285 * in addition to the level detection.
287 omap_gpio_rmw(base
+ bank
->regs
->risingdetect
, gpio_bit
,
288 trigger
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH
));
289 omap_gpio_rmw(base
+ bank
->regs
->fallingdetect
, gpio_bit
,
290 trigger
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_LEVEL_LOW
));
292 bank
->context
.leveldetect0
=
293 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
294 bank
->context
.leveldetect1
=
295 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
296 bank
->context
.risingdetect
=
297 readl_relaxed(bank
->base
+ bank
->regs
->risingdetect
);
298 bank
->context
.fallingdetect
=
299 readl_relaxed(bank
->base
+ bank
->regs
->fallingdetect
);
301 bank
->level_mask
= bank
->context
.leveldetect0
|
302 bank
->context
.leveldetect1
;
304 /* This part needs to be executed always for OMAP{34xx, 44xx} */
305 if (!bank
->regs
->irqctrl
&& !omap_gpio_is_off_wakeup_capable(bank
, gpio
)) {
307 * Log the edge gpio and manually trigger the IRQ
308 * after resume if the input level changes
309 * to avoid irq lost during PER RET/OFF mode
310 * Applies for omap2 non-wakeup gpio and all omap3 gpios
312 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
313 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
315 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
320 * This only applies to chips that can't do both rising and falling edge
321 * detection at once. For all other chips, this function is a noop.
323 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
325 if (IS_ENABLED(CONFIG_ARCH_OMAP1
) && bank
->regs
->irqctrl
) {
326 void __iomem
*reg
= bank
->base
+ bank
->regs
->irqctrl
;
328 writel_relaxed(readl_relaxed(reg
) ^ BIT(gpio
), reg
);
332 static int omap_set_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
335 void __iomem
*reg
= bank
->base
;
338 if (bank
->regs
->leveldetect0
&& bank
->regs
->wkup_en
) {
339 omap_set_gpio_trigger(bank
, gpio
, trigger
);
340 } else if (bank
->regs
->irqctrl
) {
341 reg
+= bank
->regs
->irqctrl
;
343 l
= readl_relaxed(reg
);
344 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
345 bank
->toggle_mask
|= BIT(gpio
);
346 if (trigger
& IRQ_TYPE_EDGE_RISING
)
348 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
353 writel_relaxed(l
, reg
);
354 } else if (bank
->regs
->edgectrl1
) {
356 reg
+= bank
->regs
->edgectrl2
;
358 reg
+= bank
->regs
->edgectrl1
;
361 l
= readl_relaxed(reg
);
362 l
&= ~(3 << (gpio
<< 1));
363 if (trigger
& IRQ_TYPE_EDGE_RISING
)
364 l
|= 2 << (gpio
<< 1);
365 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
367 writel_relaxed(l
, reg
);
372 static void omap_enable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
374 if (bank
->regs
->pinctrl
) {
375 void __iomem
*reg
= bank
->base
+ bank
->regs
->pinctrl
;
377 /* Claim the pin for MPU */
378 writel_relaxed(readl_relaxed(reg
) | (BIT(offset
)), reg
);
381 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
382 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
385 ctrl
= readl_relaxed(reg
);
386 /* Module is enabled, clocks are not gated */
387 ctrl
&= ~GPIO_MOD_CTRL_BIT
;
388 writel_relaxed(ctrl
, reg
);
389 bank
->context
.ctrl
= ctrl
;
393 static void omap_disable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
395 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
396 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
399 ctrl
= readl_relaxed(reg
);
400 /* Module is disabled, clocks are gated */
401 ctrl
|= GPIO_MOD_CTRL_BIT
;
402 writel_relaxed(ctrl
, reg
);
403 bank
->context
.ctrl
= ctrl
;
407 static int omap_gpio_is_input(struct gpio_bank
*bank
, unsigned offset
)
409 void __iomem
*reg
= bank
->base
+ bank
->regs
->direction
;
411 return readl_relaxed(reg
) & BIT(offset
);
414 static void omap_gpio_init_irq(struct gpio_bank
*bank
, unsigned offset
)
416 if (!LINE_USED(bank
->mod_usage
, offset
)) {
417 omap_enable_gpio_module(bank
, offset
);
418 omap_set_gpio_direction(bank
, offset
, 1);
420 bank
->irq_usage
|= BIT(offset
);
423 static int omap_gpio_irq_type(struct irq_data
*d
, unsigned type
)
425 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
428 unsigned offset
= d
->hwirq
;
430 if (type
& ~IRQ_TYPE_SENSE_MASK
)
433 if (!bank
->regs
->leveldetect0
&&
434 (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
437 raw_spin_lock_irqsave(&bank
->lock
, flags
);
438 retval
= omap_set_gpio_triggering(bank
, offset
, type
);
440 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
443 omap_gpio_init_irq(bank
, offset
);
444 if (!omap_gpio_is_input(bank
, offset
)) {
445 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
449 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
451 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
452 irq_set_handler_locked(d
, handle_level_irq
);
453 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
455 * Edge IRQs are already cleared/acked in irq_handler and
456 * not need to be masked, as result handle_edge_irq()
457 * logic is excessed here and may cause lose of interrupts.
458 * So just use handle_simple_irq.
460 irq_set_handler_locked(d
, handle_simple_irq
);
468 static void omap_clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
470 void __iomem
*reg
= bank
->base
;
472 reg
+= bank
->regs
->irqstatus
;
473 writel_relaxed(gpio_mask
, reg
);
475 /* Workaround for clearing DSP GPIO interrupts to allow retention */
476 if (bank
->regs
->irqstatus2
) {
477 reg
= bank
->base
+ bank
->regs
->irqstatus2
;
478 writel_relaxed(gpio_mask
, reg
);
481 /* Flush posted write for the irq status to avoid spurious interrupts */
485 static inline void omap_clear_gpio_irqstatus(struct gpio_bank
*bank
,
488 omap_clear_gpio_irqbank(bank
, BIT(offset
));
491 static u32
omap_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
493 void __iomem
*reg
= bank
->base
;
495 u32 mask
= (BIT(bank
->width
)) - 1;
497 reg
+= bank
->regs
->irqenable
;
498 l
= readl_relaxed(reg
);
499 if (bank
->regs
->irqenable_inv
)
505 static inline void omap_set_gpio_irqenable(struct gpio_bank
*bank
,
506 unsigned offset
, int enable
)
508 void __iomem
*reg
= bank
->base
;
509 u32 gpio_mask
= BIT(offset
);
511 if (bank
->regs
->set_irqenable
&& bank
->regs
->clr_irqenable
) {
513 reg
+= bank
->regs
->set_irqenable
;
514 bank
->context
.irqenable1
|= gpio_mask
;
516 reg
+= bank
->regs
->clr_irqenable
;
517 bank
->context
.irqenable1
&= ~gpio_mask
;
519 writel_relaxed(gpio_mask
, reg
);
521 bank
->context
.irqenable1
=
522 omap_gpio_rmw(reg
+ bank
->regs
->irqenable
, gpio_mask
,
523 enable
^ bank
->regs
->irqenable_inv
);
527 * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
528 * note requiring correlation between the IRQ enable registers and
529 * the wakeup registers. In any case, we want wakeup from idle
530 * enabled for the GPIOs which support this feature.
532 if (bank
->regs
->wkup_en
&&
533 (bank
->regs
->edgectrl1
|| !(bank
->non_wakeup_gpios
& gpio_mask
))) {
534 bank
->context
.wake_en
=
535 omap_gpio_rmw(bank
->base
+ bank
->regs
->wkup_en
,
540 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
541 static int omap_gpio_wake_enable(struct irq_data
*d
, unsigned int enable
)
543 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
545 return irq_set_irq_wake(bank
->irq
, enable
);
549 * We need to unmask the GPIO bank interrupt as soon as possible to
550 * avoid missing GPIO interrupts for other lines in the bank.
551 * Then we need to mask-read-clear-unmask the triggered GPIO lines
552 * in the bank to avoid missing nested interrupts for a GPIO line.
553 * If we wait to unmask individual GPIO lines in the bank after the
554 * line's interrupt handler has been run, we may miss some nested
557 static irqreturn_t
omap_gpio_irq_handler(int irq
, void *gpiobank
)
559 void __iomem
*isr_reg
= NULL
;
560 u32 enabled
, isr
, edge
;
562 struct gpio_bank
*bank
= gpiobank
;
563 unsigned long wa_lock_flags
;
564 unsigned long lock_flags
;
566 isr_reg
= bank
->base
+ bank
->regs
->irqstatus
;
567 if (WARN_ON(!isr_reg
))
570 if (WARN_ONCE(!pm_runtime_active(bank
->chip
.parent
),
571 "gpio irq%i while runtime suspended?\n", irq
))
575 raw_spin_lock_irqsave(&bank
->lock
, lock_flags
);
577 enabled
= omap_get_gpio_irqbank_mask(bank
);
578 isr
= readl_relaxed(isr_reg
) & enabled
;
581 * Clear edge sensitive interrupts before calling handler(s)
582 * so subsequent edge transitions are not missed while the
583 * handlers are running.
585 edge
= isr
& ~bank
->level_mask
;
587 omap_clear_gpio_irqbank(bank
, edge
);
589 raw_spin_unlock_irqrestore(&bank
->lock
, lock_flags
);
598 raw_spin_lock_irqsave(&bank
->lock
, lock_flags
);
600 * Some chips can't respond to both rising and falling
601 * at the same time. If this irq was requested with
602 * both flags, we need to flip the ICR data for the IRQ
603 * to respond to the IRQ for the opposite direction.
604 * This will be indicated in the bank toggle_mask.
606 if (bank
->toggle_mask
& (BIT(bit
)))
607 omap_toggle_gpio_edge_triggering(bank
, bit
);
609 raw_spin_unlock_irqrestore(&bank
->lock
, lock_flags
);
611 raw_spin_lock_irqsave(&bank
->wa_lock
, wa_lock_flags
);
613 generic_handle_irq(irq_find_mapping(bank
->chip
.irq
.domain
,
616 raw_spin_unlock_irqrestore(&bank
->wa_lock
,
624 static unsigned int omap_gpio_irq_startup(struct irq_data
*d
)
626 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
628 unsigned offset
= d
->hwirq
;
630 raw_spin_lock_irqsave(&bank
->lock
, flags
);
632 if (!LINE_USED(bank
->mod_usage
, offset
))
633 omap_set_gpio_direction(bank
, offset
, 1);
634 omap_enable_gpio_module(bank
, offset
);
635 bank
->irq_usage
|= BIT(offset
);
637 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
638 omap_gpio_unmask_irq(d
);
643 static void omap_gpio_irq_shutdown(struct irq_data
*d
)
645 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
647 unsigned offset
= d
->hwirq
;
649 raw_spin_lock_irqsave(&bank
->lock
, flags
);
650 bank
->irq_usage
&= ~(BIT(offset
));
651 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
652 omap_clear_gpio_irqstatus(bank
, offset
);
653 omap_set_gpio_irqenable(bank
, offset
, 0);
654 if (!LINE_USED(bank
->mod_usage
, offset
))
655 omap_clear_gpio_debounce(bank
, offset
);
656 omap_disable_gpio_module(bank
, offset
);
657 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
660 static void omap_gpio_irq_bus_lock(struct irq_data
*data
)
662 struct gpio_bank
*bank
= omap_irq_data_get_bank(data
);
664 pm_runtime_get_sync(bank
->chip
.parent
);
667 static void gpio_irq_bus_sync_unlock(struct irq_data
*data
)
669 struct gpio_bank
*bank
= omap_irq_data_get_bank(data
);
671 pm_runtime_put(bank
->chip
.parent
);
674 static void omap_gpio_mask_irq(struct irq_data
*d
)
676 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
677 unsigned offset
= d
->hwirq
;
680 raw_spin_lock_irqsave(&bank
->lock
, flags
);
681 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
682 omap_set_gpio_irqenable(bank
, offset
, 0);
683 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
686 static void omap_gpio_unmask_irq(struct irq_data
*d
)
688 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
689 unsigned offset
= d
->hwirq
;
690 u32 trigger
= irqd_get_trigger_type(d
);
693 raw_spin_lock_irqsave(&bank
->lock
, flags
);
694 omap_set_gpio_irqenable(bank
, offset
, 1);
697 * For level-triggered GPIOs, clearing must be done after the source
698 * is cleared, thus after the handler has run. OMAP4 needs this done
699 * after enabing the interrupt to clear the wakeup status.
701 if (bank
->regs
->leveldetect0
&& bank
->regs
->wkup_en
&&
702 trigger
& (IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
))
703 omap_clear_gpio_irqstatus(bank
, offset
);
706 omap_set_gpio_triggering(bank
, offset
, trigger
);
708 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
711 /*---------------------------------------------------------------------*/
713 static int omap_mpuio_suspend_noirq(struct device
*dev
)
715 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
716 void __iomem
*mask_reg
= bank
->base
+
717 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
720 raw_spin_lock_irqsave(&bank
->lock
, flags
);
721 writel_relaxed(0xffff & ~bank
->context
.wake_en
, mask_reg
);
722 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
727 static int omap_mpuio_resume_noirq(struct device
*dev
)
729 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
730 void __iomem
*mask_reg
= bank
->base
+
731 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
734 raw_spin_lock_irqsave(&bank
->lock
, flags
);
735 writel_relaxed(bank
->context
.wake_en
, mask_reg
);
736 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
741 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
742 .suspend_noirq
= omap_mpuio_suspend_noirq
,
743 .resume_noirq
= omap_mpuio_resume_noirq
,
746 /* use platform_driver for this. */
747 static struct platform_driver omap_mpuio_driver
= {
750 .pm
= &omap_mpuio_dev_pm_ops
,
754 static struct platform_device omap_mpuio_device
= {
758 .driver
= &omap_mpuio_driver
.driver
,
760 /* could list the /proc/iomem resources */
763 static inline void omap_mpuio_init(struct gpio_bank
*bank
)
765 platform_set_drvdata(&omap_mpuio_device
, bank
);
767 if (platform_driver_register(&omap_mpuio_driver
) == 0)
768 (void) platform_device_register(&omap_mpuio_device
);
771 /*---------------------------------------------------------------------*/
773 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
775 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
778 pm_runtime_get_sync(chip
->parent
);
780 raw_spin_lock_irqsave(&bank
->lock
, flags
);
781 omap_enable_gpio_module(bank
, offset
);
782 bank
->mod_usage
|= BIT(offset
);
783 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
788 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
790 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
793 raw_spin_lock_irqsave(&bank
->lock
, flags
);
794 bank
->mod_usage
&= ~(BIT(offset
));
795 if (!LINE_USED(bank
->irq_usage
, offset
)) {
796 omap_set_gpio_direction(bank
, offset
, 1);
797 omap_clear_gpio_debounce(bank
, offset
);
799 omap_disable_gpio_module(bank
, offset
);
800 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
802 pm_runtime_put(chip
->parent
);
805 static int omap_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
807 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
809 if (readl_relaxed(bank
->base
+ bank
->regs
->direction
) & BIT(offset
))
810 return GPIO_LINE_DIRECTION_IN
;
812 return GPIO_LINE_DIRECTION_OUT
;
815 static int omap_gpio_input(struct gpio_chip
*chip
, unsigned offset
)
817 struct gpio_bank
*bank
;
820 bank
= gpiochip_get_data(chip
);
821 raw_spin_lock_irqsave(&bank
->lock
, flags
);
822 omap_set_gpio_direction(bank
, offset
, 1);
823 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
827 static int omap_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
829 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
832 if (omap_gpio_is_input(bank
, offset
))
833 reg
= bank
->base
+ bank
->regs
->datain
;
835 reg
= bank
->base
+ bank
->regs
->dataout
;
837 return (readl_relaxed(reg
) & BIT(offset
)) != 0;
840 static int omap_gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
842 struct gpio_bank
*bank
;
845 bank
= gpiochip_get_data(chip
);
846 raw_spin_lock_irqsave(&bank
->lock
, flags
);
847 bank
->set_dataout(bank
, offset
, value
);
848 omap_set_gpio_direction(bank
, offset
, 0);
849 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
853 static int omap_gpio_get_multiple(struct gpio_chip
*chip
, unsigned long *mask
,
856 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
857 void __iomem
*base
= bank
->base
;
858 u32 direction
, m
, val
= 0;
860 direction
= readl_relaxed(base
+ bank
->regs
->direction
);
862 m
= direction
& *mask
;
864 val
|= readl_relaxed(base
+ bank
->regs
->datain
) & m
;
866 m
= ~direction
& *mask
;
868 val
|= readl_relaxed(base
+ bank
->regs
->dataout
) & m
;
875 static int omap_gpio_debounce(struct gpio_chip
*chip
, unsigned offset
,
878 struct gpio_bank
*bank
;
882 bank
= gpiochip_get_data(chip
);
884 raw_spin_lock_irqsave(&bank
->lock
, flags
);
885 ret
= omap2_set_gpio_debounce(bank
, offset
, debounce
);
886 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
889 dev_info(chip
->parent
,
890 "Could not set line %u debounce to %u microseconds (%d)",
891 offset
, debounce
, ret
);
896 static int omap_gpio_set_config(struct gpio_chip
*chip
, unsigned offset
,
897 unsigned long config
)
902 switch (pinconf_to_config_param(config
)) {
903 case PIN_CONFIG_BIAS_DISABLE
:
904 case PIN_CONFIG_BIAS_PULL_UP
:
905 case PIN_CONFIG_BIAS_PULL_DOWN
:
906 ret
= gpiochip_generic_config(chip
, offset
, config
);
908 case PIN_CONFIG_INPUT_DEBOUNCE
:
909 debounce
= pinconf_to_config_argument(config
);
910 ret
= omap_gpio_debounce(chip
, offset
, debounce
);
919 static void omap_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
921 struct gpio_bank
*bank
;
924 bank
= gpiochip_get_data(chip
);
925 raw_spin_lock_irqsave(&bank
->lock
, flags
);
926 bank
->set_dataout(bank
, offset
, value
);
927 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
930 static void omap_gpio_set_multiple(struct gpio_chip
*chip
, unsigned long *mask
,
933 struct gpio_bank
*bank
= gpiochip_get_data(chip
);
934 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
938 raw_spin_lock_irqsave(&bank
->lock
, flags
);
939 l
= (readl_relaxed(reg
) & ~*mask
) | (*bits
& *mask
);
940 writel_relaxed(l
, reg
);
941 bank
->context
.dataout
= l
;
942 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
945 /*---------------------------------------------------------------------*/
947 static void omap_gpio_show_rev(struct gpio_bank
*bank
)
952 if (called
|| bank
->regs
->revision
== USHRT_MAX
)
955 rev
= readw_relaxed(bank
->base
+ bank
->regs
->revision
);
956 pr_info("OMAP GPIO hardware version %d.%d\n",
957 (rev
>> 4) & 0x0f, rev
& 0x0f);
962 static void omap_gpio_mod_init(struct gpio_bank
*bank
)
964 void __iomem
*base
= bank
->base
;
967 if (bank
->width
== 16)
970 if (bank
->is_mpuio
) {
971 writel_relaxed(l
, bank
->base
+ bank
->regs
->irqenable
);
975 omap_gpio_rmw(base
+ bank
->regs
->irqenable
, l
,
976 bank
->regs
->irqenable_inv
);
977 omap_gpio_rmw(base
+ bank
->regs
->irqstatus
, l
,
978 !bank
->regs
->irqenable_inv
);
979 if (bank
->regs
->debounce_en
)
980 writel_relaxed(0, base
+ bank
->regs
->debounce_en
);
982 /* Save OE default value (0xffffffff) in the context */
983 bank
->context
.oe
= readl_relaxed(bank
->base
+ bank
->regs
->direction
);
984 /* Initialize interface clk ungated, module enabled */
985 if (bank
->regs
->ctrl
)
986 writel_relaxed(0, base
+ bank
->regs
->ctrl
);
989 static int omap_gpio_chip_init(struct gpio_bank
*bank
, struct irq_chip
*irqc
)
991 struct gpio_irq_chip
*irq
;
998 * REVISIT eventually switch from OMAP-specific gpio structs
999 * over to the generic ones
1001 bank
->chip
.request
= omap_gpio_request
;
1002 bank
->chip
.free
= omap_gpio_free
;
1003 bank
->chip
.get_direction
= omap_gpio_get_direction
;
1004 bank
->chip
.direction_input
= omap_gpio_input
;
1005 bank
->chip
.get
= omap_gpio_get
;
1006 bank
->chip
.get_multiple
= omap_gpio_get_multiple
;
1007 bank
->chip
.direction_output
= omap_gpio_output
;
1008 bank
->chip
.set_config
= omap_gpio_set_config
;
1009 bank
->chip
.set
= omap_gpio_set
;
1010 bank
->chip
.set_multiple
= omap_gpio_set_multiple
;
1011 if (bank
->is_mpuio
) {
1012 bank
->chip
.label
= "mpuio";
1013 if (bank
->regs
->wkup_en
)
1014 bank
->chip
.parent
= &omap_mpuio_device
.dev
;
1015 bank
->chip
.base
= OMAP_MPUIO(0);
1017 label
= devm_kasprintf(bank
->chip
.parent
, GFP_KERNEL
, "gpio-%d-%d",
1018 gpio
, gpio
+ bank
->width
- 1);
1021 bank
->chip
.label
= label
;
1022 bank
->chip
.base
= gpio
;
1024 bank
->chip
.ngpio
= bank
->width
;
1026 #ifdef CONFIG_ARCH_OMAP1
1028 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1029 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1031 irq_base
= devm_irq_alloc_descs(bank
->chip
.parent
,
1032 -1, 0, bank
->width
, 0);
1034 dev_err(bank
->chip
.parent
, "Couldn't allocate IRQ numbers\n");
1039 /* MPUIO is a bit different, reading IRQ status clears it */
1040 if (bank
->is_mpuio
&& !bank
->regs
->wkup_en
)
1041 irqc
->irq_set_wake
= NULL
;
1043 irq
= &bank
->chip
.irq
;
1045 irq
->handler
= handle_bad_irq
;
1046 irq
->default_type
= IRQ_TYPE_NONE
;
1047 irq
->num_parents
= 1;
1048 irq
->parents
= &bank
->irq
;
1049 irq
->first
= irq_base
;
1051 ret
= gpiochip_add_data(&bank
->chip
, bank
);
1053 dev_err(bank
->chip
.parent
,
1054 "Could not register gpio chip %d\n", ret
);
1058 ret
= devm_request_irq(bank
->chip
.parent
, bank
->irq
,
1059 omap_gpio_irq_handler
,
1060 0, dev_name(bank
->chip
.parent
), bank
);
1062 gpiochip_remove(&bank
->chip
);
1064 if (!bank
->is_mpuio
)
1065 gpio
+= bank
->width
;
1070 static void omap_gpio_init_context(struct gpio_bank
*p
)
1072 const struct omap_gpio_reg_offs
*regs
= p
->regs
;
1073 void __iomem
*base
= p
->base
;
1075 p
->context
.ctrl
= readl_relaxed(base
+ regs
->ctrl
);
1076 p
->context
.oe
= readl_relaxed(base
+ regs
->direction
);
1077 p
->context
.wake_en
= readl_relaxed(base
+ regs
->wkup_en
);
1078 p
->context
.leveldetect0
= readl_relaxed(base
+ regs
->leveldetect0
);
1079 p
->context
.leveldetect1
= readl_relaxed(base
+ regs
->leveldetect1
);
1080 p
->context
.risingdetect
= readl_relaxed(base
+ regs
->risingdetect
);
1081 p
->context
.fallingdetect
= readl_relaxed(base
+ regs
->fallingdetect
);
1082 p
->context
.irqenable1
= readl_relaxed(base
+ regs
->irqenable
);
1083 p
->context
.irqenable2
= readl_relaxed(base
+ regs
->irqenable2
);
1084 p
->context
.dataout
= readl_relaxed(base
+ regs
->dataout
);
1086 p
->context_valid
= true;
1089 static void omap_gpio_restore_context(struct gpio_bank
*bank
)
1091 const struct omap_gpio_reg_offs
*regs
= bank
->regs
;
1092 void __iomem
*base
= bank
->base
;
1094 writel_relaxed(bank
->context
.wake_en
, base
+ regs
->wkup_en
);
1095 writel_relaxed(bank
->context
.ctrl
, base
+ regs
->ctrl
);
1096 writel_relaxed(bank
->context
.leveldetect0
, base
+ regs
->leveldetect0
);
1097 writel_relaxed(bank
->context
.leveldetect1
, base
+ regs
->leveldetect1
);
1098 writel_relaxed(bank
->context
.risingdetect
, base
+ regs
->risingdetect
);
1099 writel_relaxed(bank
->context
.fallingdetect
, base
+ regs
->fallingdetect
);
1100 writel_relaxed(bank
->context
.dataout
, base
+ regs
->dataout
);
1101 writel_relaxed(bank
->context
.oe
, base
+ regs
->direction
);
1103 if (bank
->dbck_enable_mask
) {
1104 writel_relaxed(bank
->context
.debounce
, base
+ regs
->debounce
);
1105 writel_relaxed(bank
->context
.debounce_en
,
1106 base
+ regs
->debounce_en
);
1109 writel_relaxed(bank
->context
.irqenable1
, base
+ regs
->irqenable
);
1110 writel_relaxed(bank
->context
.irqenable2
, base
+ regs
->irqenable2
);
1113 static void omap_gpio_idle(struct gpio_bank
*bank
, bool may_lose_context
)
1115 struct device
*dev
= bank
->chip
.parent
;
1116 void __iomem
*base
= bank
->base
;
1119 bank
->saved_datain
= readl_relaxed(base
+ bank
->regs
->datain
);
1121 if (!bank
->enabled_non_wakeup_gpios
)
1122 goto update_gpio_context_count
;
1124 /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
1125 mask
= bank
->enabled_non_wakeup_gpios
& bank
->context
.fallingdetect
;
1126 mask
&= ~bank
->context
.risingdetect
;
1127 bank
->saved_datain
|= mask
;
1129 /* Check for pending EDGE_RISING, ignore EDGE_BOTH */
1130 mask
= bank
->enabled_non_wakeup_gpios
& bank
->context
.risingdetect
;
1131 mask
&= ~bank
->context
.fallingdetect
;
1132 bank
->saved_datain
&= ~mask
;
1134 if (!may_lose_context
)
1135 goto update_gpio_context_count
;
1138 * If going to OFF, remove triggering for all wkup domain
1139 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1140 * generated. See OMAP2420 Errata item 1.101.
1142 if (!bank
->loses_context
&& bank
->enabled_non_wakeup_gpios
) {
1143 nowake
= bank
->enabled_non_wakeup_gpios
;
1144 omap_gpio_rmw(base
+ bank
->regs
->fallingdetect
, nowake
, ~nowake
);
1145 omap_gpio_rmw(base
+ bank
->regs
->risingdetect
, nowake
, ~nowake
);
1148 update_gpio_context_count
:
1149 if (bank
->get_context_loss_count
)
1150 bank
->context_loss_count
=
1151 bank
->get_context_loss_count(dev
);
1153 omap_gpio_dbck_disable(bank
);
1156 static void omap_gpio_unidle(struct gpio_bank
*bank
)
1158 struct device
*dev
= bank
->chip
.parent
;
1159 u32 l
= 0, gen
, gen0
, gen1
;
1163 * On the first resume during the probe, the context has not
1164 * been initialised and so initialise it now. Also initialise
1165 * the context loss count.
1167 if (bank
->loses_context
&& !bank
->context_valid
) {
1168 omap_gpio_init_context(bank
);
1170 if (bank
->get_context_loss_count
)
1171 bank
->context_loss_count
=
1172 bank
->get_context_loss_count(dev
);
1175 omap_gpio_dbck_enable(bank
);
1177 if (bank
->loses_context
) {
1178 if (!bank
->get_context_loss_count
) {
1179 omap_gpio_restore_context(bank
);
1181 c
= bank
->get_context_loss_count(dev
);
1182 if (c
!= bank
->context_loss_count
) {
1183 omap_gpio_restore_context(bank
);
1189 /* Restore changes done for OMAP2420 errata 1.101 */
1190 writel_relaxed(bank
->context
.fallingdetect
,
1191 bank
->base
+ bank
->regs
->fallingdetect
);
1192 writel_relaxed(bank
->context
.risingdetect
,
1193 bank
->base
+ bank
->regs
->risingdetect
);
1196 l
= readl_relaxed(bank
->base
+ bank
->regs
->datain
);
1199 * Check if any of the non-wakeup interrupt GPIOs have changed
1200 * state. If so, generate an IRQ by software. This is
1201 * horribly racy, but it's the best we can do to work around
1204 l
^= bank
->saved_datain
;
1205 l
&= bank
->enabled_non_wakeup_gpios
;
1208 * No need to generate IRQs for the rising edge for gpio IRQs
1209 * configured with falling edge only; and vice versa.
1211 gen0
= l
& bank
->context
.fallingdetect
;
1212 gen0
&= bank
->saved_datain
;
1214 gen1
= l
& bank
->context
.risingdetect
;
1215 gen1
&= ~(bank
->saved_datain
);
1217 /* FIXME: Consider GPIO IRQs with level detections properly! */
1218 gen
= l
& (~(bank
->context
.fallingdetect
) &
1219 ~(bank
->context
.risingdetect
));
1220 /* Consider all GPIO IRQs needed to be updated */
1226 old0
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
1227 old1
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
1229 if (!bank
->regs
->irqstatus_raw0
) {
1230 writel_relaxed(old0
| gen
, bank
->base
+
1231 bank
->regs
->leveldetect0
);
1232 writel_relaxed(old1
| gen
, bank
->base
+
1233 bank
->regs
->leveldetect1
);
1236 if (bank
->regs
->irqstatus_raw0
) {
1237 writel_relaxed(old0
| l
, bank
->base
+
1238 bank
->regs
->leveldetect0
);
1239 writel_relaxed(old1
| l
, bank
->base
+
1240 bank
->regs
->leveldetect1
);
1242 writel_relaxed(old0
, bank
->base
+ bank
->regs
->leveldetect0
);
1243 writel_relaxed(old1
, bank
->base
+ bank
->regs
->leveldetect1
);
1247 static int gpio_omap_cpu_notifier(struct notifier_block
*nb
,
1248 unsigned long cmd
, void *v
)
1250 struct gpio_bank
*bank
;
1251 unsigned long flags
;
1252 int ret
= NOTIFY_OK
;
1255 bank
= container_of(nb
, struct gpio_bank
, nb
);
1257 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1258 if (bank
->is_suspended
)
1262 case CPU_CLUSTER_PM_ENTER
:
1263 mask
= omap_get_gpio_irqbank_mask(bank
);
1264 isr
= readl_relaxed(bank
->base
+ bank
->regs
->irqstatus
) & mask
;
1269 omap_gpio_idle(bank
, true);
1271 case CPU_CLUSTER_PM_ENTER_FAILED
:
1272 case CPU_CLUSTER_PM_EXIT
:
1273 omap_gpio_unidle(bank
);
1278 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1283 static const struct omap_gpio_reg_offs omap2_gpio_regs
= {
1284 .revision
= OMAP24XX_GPIO_REVISION
,
1285 .direction
= OMAP24XX_GPIO_OE
,
1286 .datain
= OMAP24XX_GPIO_DATAIN
,
1287 .dataout
= OMAP24XX_GPIO_DATAOUT
,
1288 .set_dataout
= OMAP24XX_GPIO_SETDATAOUT
,
1289 .clr_dataout
= OMAP24XX_GPIO_CLEARDATAOUT
,
1290 .irqstatus
= OMAP24XX_GPIO_IRQSTATUS1
,
1291 .irqstatus2
= OMAP24XX_GPIO_IRQSTATUS2
,
1292 .irqenable
= OMAP24XX_GPIO_IRQENABLE1
,
1293 .irqenable2
= OMAP24XX_GPIO_IRQENABLE2
,
1294 .set_irqenable
= OMAP24XX_GPIO_SETIRQENABLE1
,
1295 .clr_irqenable
= OMAP24XX_GPIO_CLEARIRQENABLE1
,
1296 .debounce
= OMAP24XX_GPIO_DEBOUNCE_VAL
,
1297 .debounce_en
= OMAP24XX_GPIO_DEBOUNCE_EN
,
1298 .ctrl
= OMAP24XX_GPIO_CTRL
,
1299 .wkup_en
= OMAP24XX_GPIO_WAKE_EN
,
1300 .leveldetect0
= OMAP24XX_GPIO_LEVELDETECT0
,
1301 .leveldetect1
= OMAP24XX_GPIO_LEVELDETECT1
,
1302 .risingdetect
= OMAP24XX_GPIO_RISINGDETECT
,
1303 .fallingdetect
= OMAP24XX_GPIO_FALLINGDETECT
,
1306 static const struct omap_gpio_reg_offs omap4_gpio_regs
= {
1307 .revision
= OMAP4_GPIO_REVISION
,
1308 .direction
= OMAP4_GPIO_OE
,
1309 .datain
= OMAP4_GPIO_DATAIN
,
1310 .dataout
= OMAP4_GPIO_DATAOUT
,
1311 .set_dataout
= OMAP4_GPIO_SETDATAOUT
,
1312 .clr_dataout
= OMAP4_GPIO_CLEARDATAOUT
,
1313 .irqstatus
= OMAP4_GPIO_IRQSTATUS0
,
1314 .irqstatus2
= OMAP4_GPIO_IRQSTATUS1
,
1315 .irqstatus_raw0
= OMAP4_GPIO_IRQSTATUSRAW0
,
1316 .irqstatus_raw1
= OMAP4_GPIO_IRQSTATUSRAW1
,
1317 .irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1318 .irqenable2
= OMAP4_GPIO_IRQSTATUSSET1
,
1319 .set_irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1320 .clr_irqenable
= OMAP4_GPIO_IRQSTATUSCLR0
,
1321 .debounce
= OMAP4_GPIO_DEBOUNCINGTIME
,
1322 .debounce_en
= OMAP4_GPIO_DEBOUNCENABLE
,
1323 .ctrl
= OMAP4_GPIO_CTRL
,
1324 .wkup_en
= OMAP4_GPIO_IRQWAKEN0
,
1325 .leveldetect0
= OMAP4_GPIO_LEVELDETECT0
,
1326 .leveldetect1
= OMAP4_GPIO_LEVELDETECT1
,
1327 .risingdetect
= OMAP4_GPIO_RISINGDETECT
,
1328 .fallingdetect
= OMAP4_GPIO_FALLINGDETECT
,
1331 static const struct omap_gpio_platform_data omap2_pdata
= {
1332 .regs
= &omap2_gpio_regs
,
1337 static const struct omap_gpio_platform_data omap3_pdata
= {
1338 .regs
= &omap2_gpio_regs
,
1343 static const struct omap_gpio_platform_data omap4_pdata
= {
1344 .regs
= &omap4_gpio_regs
,
1349 static const struct of_device_id omap_gpio_match
[] = {
1351 .compatible
= "ti,omap4-gpio",
1352 .data
= &omap4_pdata
,
1355 .compatible
= "ti,omap3-gpio",
1356 .data
= &omap3_pdata
,
1359 .compatible
= "ti,omap2-gpio",
1360 .data
= &omap2_pdata
,
1364 MODULE_DEVICE_TABLE(of
, omap_gpio_match
);
1366 static int omap_gpio_probe(struct platform_device
*pdev
)
1368 struct device
*dev
= &pdev
->dev
;
1369 struct device_node
*node
= dev
->of_node
;
1370 const struct of_device_id
*match
;
1371 const struct omap_gpio_platform_data
*pdata
;
1372 struct gpio_bank
*bank
;
1373 struct irq_chip
*irqc
;
1376 match
= of_match_device(of_match_ptr(omap_gpio_match
), dev
);
1378 pdata
= match
? match
->data
: dev_get_platdata(dev
);
1382 bank
= devm_kzalloc(dev
, sizeof(*bank
), GFP_KERNEL
);
1386 irqc
= devm_kzalloc(dev
, sizeof(*irqc
), GFP_KERNEL
);
1390 irqc
->irq_startup
= omap_gpio_irq_startup
,
1391 irqc
->irq_shutdown
= omap_gpio_irq_shutdown
,
1392 irqc
->irq_ack
= dummy_irq_chip
.irq_ack
,
1393 irqc
->irq_mask
= omap_gpio_mask_irq
,
1394 irqc
->irq_unmask
= omap_gpio_unmask_irq
,
1395 irqc
->irq_set_type
= omap_gpio_irq_type
,
1396 irqc
->irq_set_wake
= omap_gpio_wake_enable
,
1397 irqc
->irq_bus_lock
= omap_gpio_irq_bus_lock
,
1398 irqc
->irq_bus_sync_unlock
= gpio_irq_bus_sync_unlock
,
1399 irqc
->name
= dev_name(&pdev
->dev
);
1400 irqc
->flags
= IRQCHIP_MASK_ON_SUSPEND
;
1401 irqc
->parent_device
= dev
;
1403 bank
->irq
= platform_get_irq(pdev
, 0);
1404 if (bank
->irq
<= 0) {
1407 return dev_err_probe(dev
, bank
->irq
, "can't get irq resource\n");
1410 bank
->chip
.parent
= dev
;
1411 bank
->chip
.owner
= THIS_MODULE
;
1412 bank
->dbck_flag
= pdata
->dbck_flag
;
1413 bank
->stride
= pdata
->bank_stride
;
1414 bank
->width
= pdata
->bank_width
;
1415 bank
->is_mpuio
= pdata
->is_mpuio
;
1416 bank
->non_wakeup_gpios
= pdata
->non_wakeup_gpios
;
1417 bank
->regs
= pdata
->regs
;
1418 #ifdef CONFIG_OF_GPIO
1419 bank
->chip
.of_node
= of_node_get(node
);
1423 if (!of_property_read_bool(node
, "ti,gpio-always-on"))
1424 bank
->loses_context
= true;
1426 bank
->loses_context
= pdata
->loses_context
;
1428 if (bank
->loses_context
)
1429 bank
->get_context_loss_count
=
1430 pdata
->get_context_loss_count
;
1433 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
)
1434 bank
->set_dataout
= omap_set_gpio_dataout_reg
;
1436 bank
->set_dataout
= omap_set_gpio_dataout_mask
;
1438 raw_spin_lock_init(&bank
->lock
);
1439 raw_spin_lock_init(&bank
->wa_lock
);
1441 /* Static mapping, never released */
1442 bank
->base
= devm_platform_ioremap_resource(pdev
, 0);
1443 if (IS_ERR(bank
->base
)) {
1444 return PTR_ERR(bank
->base
);
1447 if (bank
->dbck_flag
) {
1448 bank
->dbck
= devm_clk_get(dev
, "dbclk");
1449 if (IS_ERR(bank
->dbck
)) {
1451 "Could not get gpio dbck. Disable debounce\n");
1452 bank
->dbck_flag
= false;
1454 clk_prepare(bank
->dbck
);
1458 platform_set_drvdata(pdev
, bank
);
1460 pm_runtime_enable(dev
);
1461 pm_runtime_get_sync(dev
);
1464 omap_mpuio_init(bank
);
1466 omap_gpio_mod_init(bank
);
1468 ret
= omap_gpio_chip_init(bank
, irqc
);
1470 pm_runtime_put_sync(dev
);
1471 pm_runtime_disable(dev
);
1472 if (bank
->dbck_flag
)
1473 clk_unprepare(bank
->dbck
);
1477 omap_gpio_show_rev(bank
);
1479 bank
->nb
.notifier_call
= gpio_omap_cpu_notifier
;
1480 cpu_pm_register_notifier(&bank
->nb
);
1482 pm_runtime_put(dev
);
1487 static int omap_gpio_remove(struct platform_device
*pdev
)
1489 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1491 cpu_pm_unregister_notifier(&bank
->nb
);
1492 gpiochip_remove(&bank
->chip
);
1493 pm_runtime_disable(&pdev
->dev
);
1494 if (bank
->dbck_flag
)
1495 clk_unprepare(bank
->dbck
);
1500 static int __maybe_unused
omap_gpio_runtime_suspend(struct device
*dev
)
1502 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
1503 unsigned long flags
;
1505 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1506 omap_gpio_idle(bank
, true);
1507 bank
->is_suspended
= true;
1508 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1513 static int __maybe_unused
omap_gpio_runtime_resume(struct device
*dev
)
1515 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
1516 unsigned long flags
;
1518 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1519 omap_gpio_unidle(bank
);
1520 bank
->is_suspended
= false;
1521 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1526 static int __maybe_unused
omap_gpio_suspend(struct device
*dev
)
1528 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
1530 if (bank
->is_suspended
)
1533 bank
->needs_resume
= 1;
1535 return omap_gpio_runtime_suspend(dev
);
1538 static int __maybe_unused
omap_gpio_resume(struct device
*dev
)
1540 struct gpio_bank
*bank
= dev_get_drvdata(dev
);
1542 if (!bank
->needs_resume
)
1545 bank
->needs_resume
= 0;
1547 return omap_gpio_runtime_resume(dev
);
1550 static const struct dev_pm_ops gpio_pm_ops
= {
1551 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend
, omap_gpio_runtime_resume
,
1553 SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend
, omap_gpio_resume
)
1556 static struct platform_driver omap_gpio_driver
= {
1557 .probe
= omap_gpio_probe
,
1558 .remove
= omap_gpio_remove
,
1560 .name
= "omap_gpio",
1562 .of_match_table
= omap_gpio_match
,
1567 * gpio driver register needs to be done before
1568 * machine_init functions access gpio APIs.
1569 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1571 static int __init
omap_gpio_drv_reg(void)
1573 return platform_driver_register(&omap_gpio_driver
);
1575 postcore_initcall(omap_gpio_drv_reg
);
1577 static void __exit
omap_gpio_exit(void)
1579 platform_driver_unregister(&omap_gpio_driver
);
1581 module_exit(omap_gpio_exit
);
1583 MODULE_DESCRIPTION("omap gpio driver");
1584 MODULE_ALIAS("platform:gpio-omap");
1585 MODULE_LICENSE("GPL v2");