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Merge tag 'regmap-fix-v4.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-omap.c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
30
31 #define OFF_MODE 1
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33
34 static LIST_HEAD(omap_gpio_list);
35
36 struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49 };
50
51 struct gpio_bank {
52 struct list_head node;
53 void __iomem *base;
54 u16 irq;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 level_mask;
60 u32 toggle_mask;
61 raw_spinlock_t lock;
62 struct gpio_chip chip;
63 struct clk *dbck;
64 u32 mod_usage;
65 u32 irq_usage;
66 u32 dbck_enable_mask;
67 bool dbck_enabled;
68 struct device *dev;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 bool context_valid;
73 int stride;
74 u32 width;
75 int context_loss_count;
76 int power_mode;
77 bool workaround_enabled;
78
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
81
82 struct omap_gpio_reg_offs *regs;
83 };
84
85 #define GPIO_MOD_CTRL_BIT BIT(0)
86
87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88 #define LINE_USED(line, offset) (line & (BIT(offset)))
89
90 static void omap_gpio_unmask_irq(struct irq_data *d);
91
92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
93 {
94 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 return container_of(chip, struct gpio_bank, chip);
96 }
97
98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 int is_input)
100 {
101 void __iomem *reg = bank->base;
102 u32 l;
103
104 reg += bank->regs->direction;
105 l = readl_relaxed(reg);
106 if (is_input)
107 l |= BIT(gpio);
108 else
109 l &= ~(BIT(gpio));
110 writel_relaxed(l, reg);
111 bank->context.oe = l;
112 }
113
114
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 int enable)
118 {
119 void __iomem *reg = bank->base;
120 u32 l = BIT(offset);
121
122 if (enable) {
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
125 } else {
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
128 }
129
130 writel_relaxed(l, reg);
131 }
132
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 int enable)
136 {
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = BIT(offset);
139 u32 l;
140
141 l = readl_relaxed(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
146 writel_relaxed(l, reg);
147 bank->context.dataout = l;
148 }
149
150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
151 {
152 void __iomem *reg = bank->base + bank->regs->datain;
153
154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
155 }
156
157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
158 {
159 void __iomem *reg = bank->base + bank->regs->dataout;
160
161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
162 }
163
164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165 {
166 int l = readl_relaxed(base + reg);
167
168 if (set)
169 l |= mask;
170 else
171 l &= ~mask;
172
173 writel_relaxed(l, base + reg);
174 }
175
176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
177 {
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
181
182 writel_relaxed(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
184 }
185 }
186
187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
188 {
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
190 /*
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
194 */
195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
196
197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
199 }
200 }
201
202 /**
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
207 *
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
211 */
212 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
213 unsigned debounce)
214 {
215 void __iomem *reg;
216 u32 val;
217 u32 l;
218 bool enable = !!debounce;
219
220 if (!bank->dbck_flag)
221 return;
222
223 if (enable) {
224 debounce = DIV_ROUND_UP(debounce, 31) - 1;
225 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
226 }
227
228 l = BIT(offset);
229
230 clk_enable(bank->dbck);
231 reg = bank->base + bank->regs->debounce;
232 writel_relaxed(debounce, reg);
233
234 reg = bank->base + bank->regs->debounce_en;
235 val = readl_relaxed(reg);
236
237 if (enable)
238 val |= l;
239 else
240 val &= ~l;
241 bank->dbck_enable_mask = val;
242
243 writel_relaxed(val, reg);
244 clk_disable(bank->dbck);
245 /*
246 * Enable debounce clock per module.
247 * This call is mandatory because in omap_gpio_request() when
248 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
249 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 * used within _gpio_dbck_enable() is still not initialized at
251 * that point. Therefore we have to enable dbck here.
252 */
253 omap_gpio_dbck_enable(bank);
254 if (bank->dbck_enable_mask) {
255 bank->context.debounce = debounce;
256 bank->context.debounce_en = val;
257 }
258 }
259
260 /**
261 * omap_clear_gpio_debounce - clear debounce settings for a gpio
262 * @bank: the gpio bank we're acting upon
263 * @offset: the gpio number on this @bank
264 *
265 * If a gpio is using debounce, then clear the debounce enable bit and if
266 * this is the only gpio in this bank using debounce, then clear the debounce
267 * time too. The debounce clock will also be disabled when calling this function
268 * if this is the only gpio in the bank using debounce.
269 */
270 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
271 {
272 u32 gpio_bit = BIT(offset);
273
274 if (!bank->dbck_flag)
275 return;
276
277 if (!(bank->dbck_enable_mask & gpio_bit))
278 return;
279
280 bank->dbck_enable_mask &= ~gpio_bit;
281 bank->context.debounce_en &= ~gpio_bit;
282 writel_relaxed(bank->context.debounce_en,
283 bank->base + bank->regs->debounce_en);
284
285 if (!bank->dbck_enable_mask) {
286 bank->context.debounce = 0;
287 writel_relaxed(bank->context.debounce, bank->base +
288 bank->regs->debounce);
289 clk_disable(bank->dbck);
290 bank->dbck_enabled = false;
291 }
292 }
293
294 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
295 unsigned trigger)
296 {
297 void __iomem *base = bank->base;
298 u32 gpio_bit = BIT(gpio);
299
300 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
301 trigger & IRQ_TYPE_LEVEL_LOW);
302 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
303 trigger & IRQ_TYPE_LEVEL_HIGH);
304 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
305 trigger & IRQ_TYPE_EDGE_RISING);
306 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
307 trigger & IRQ_TYPE_EDGE_FALLING);
308
309 bank->context.leveldetect0 =
310 readl_relaxed(bank->base + bank->regs->leveldetect0);
311 bank->context.leveldetect1 =
312 readl_relaxed(bank->base + bank->regs->leveldetect1);
313 bank->context.risingdetect =
314 readl_relaxed(bank->base + bank->regs->risingdetect);
315 bank->context.fallingdetect =
316 readl_relaxed(bank->base + bank->regs->fallingdetect);
317
318 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
319 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
320 bank->context.wake_en =
321 readl_relaxed(bank->base + bank->regs->wkup_en);
322 }
323
324 /* This part needs to be executed always for OMAP{34xx, 44xx} */
325 if (!bank->regs->irqctrl) {
326 /* On omap24xx proceed only when valid GPIO bit is set */
327 if (bank->non_wakeup_gpios) {
328 if (!(bank->non_wakeup_gpios & gpio_bit))
329 goto exit;
330 }
331
332 /*
333 * Log the edge gpio and manually trigger the IRQ
334 * after resume if the input level changes
335 * to avoid irq lost during PER RET/OFF mode
336 * Applies for omap2 non-wakeup gpio and all omap3 gpios
337 */
338 if (trigger & IRQ_TYPE_EDGE_BOTH)
339 bank->enabled_non_wakeup_gpios |= gpio_bit;
340 else
341 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
342 }
343
344 exit:
345 bank->level_mask =
346 readl_relaxed(bank->base + bank->regs->leveldetect0) |
347 readl_relaxed(bank->base + bank->regs->leveldetect1);
348 }
349
350 #ifdef CONFIG_ARCH_OMAP1
351 /*
352 * This only applies to chips that can't do both rising and falling edge
353 * detection at once. For all other chips, this function is a noop.
354 */
355 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
356 {
357 void __iomem *reg = bank->base;
358 u32 l = 0;
359
360 if (!bank->regs->irqctrl)
361 return;
362
363 reg += bank->regs->irqctrl;
364
365 l = readl_relaxed(reg);
366 if ((l >> gpio) & 1)
367 l &= ~(BIT(gpio));
368 else
369 l |= BIT(gpio);
370
371 writel_relaxed(l, reg);
372 }
373 #else
374 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
375 #endif
376
377 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
378 unsigned trigger)
379 {
380 void __iomem *reg = bank->base;
381 void __iomem *base = bank->base;
382 u32 l = 0;
383
384 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
385 omap_set_gpio_trigger(bank, gpio, trigger);
386 } else if (bank->regs->irqctrl) {
387 reg += bank->regs->irqctrl;
388
389 l = readl_relaxed(reg);
390 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
391 bank->toggle_mask |= BIT(gpio);
392 if (trigger & IRQ_TYPE_EDGE_RISING)
393 l |= BIT(gpio);
394 else if (trigger & IRQ_TYPE_EDGE_FALLING)
395 l &= ~(BIT(gpio));
396 else
397 return -EINVAL;
398
399 writel_relaxed(l, reg);
400 } else if (bank->regs->edgectrl1) {
401 if (gpio & 0x08)
402 reg += bank->regs->edgectrl2;
403 else
404 reg += bank->regs->edgectrl1;
405
406 gpio &= 0x07;
407 l = readl_relaxed(reg);
408 l &= ~(3 << (gpio << 1));
409 if (trigger & IRQ_TYPE_EDGE_RISING)
410 l |= 2 << (gpio << 1);
411 if (trigger & IRQ_TYPE_EDGE_FALLING)
412 l |= BIT(gpio << 1);
413
414 /* Enable wake-up during idle for dynamic tick */
415 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
416 bank->context.wake_en =
417 readl_relaxed(bank->base + bank->regs->wkup_en);
418 writel_relaxed(l, reg);
419 }
420 return 0;
421 }
422
423 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
424 {
425 if (bank->regs->pinctrl) {
426 void __iomem *reg = bank->base + bank->regs->pinctrl;
427
428 /* Claim the pin for MPU */
429 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
430 }
431
432 if (bank->regs->ctrl && !BANK_USED(bank)) {
433 void __iomem *reg = bank->base + bank->regs->ctrl;
434 u32 ctrl;
435
436 ctrl = readl_relaxed(reg);
437 /* Module is enabled, clocks are not gated */
438 ctrl &= ~GPIO_MOD_CTRL_BIT;
439 writel_relaxed(ctrl, reg);
440 bank->context.ctrl = ctrl;
441 }
442 }
443
444 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
445 {
446 void __iomem *base = bank->base;
447
448 if (bank->regs->wkup_en &&
449 !LINE_USED(bank->mod_usage, offset) &&
450 !LINE_USED(bank->irq_usage, offset)) {
451 /* Disable wake-up during idle for dynamic tick */
452 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
453 bank->context.wake_en =
454 readl_relaxed(bank->base + bank->regs->wkup_en);
455 }
456
457 if (bank->regs->ctrl && !BANK_USED(bank)) {
458 void __iomem *reg = bank->base + bank->regs->ctrl;
459 u32 ctrl;
460
461 ctrl = readl_relaxed(reg);
462 /* Module is disabled, clocks are gated */
463 ctrl |= GPIO_MOD_CTRL_BIT;
464 writel_relaxed(ctrl, reg);
465 bank->context.ctrl = ctrl;
466 }
467 }
468
469 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
470 {
471 void __iomem *reg = bank->base + bank->regs->direction;
472
473 return readl_relaxed(reg) & BIT(offset);
474 }
475
476 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
477 {
478 if (!LINE_USED(bank->mod_usage, offset)) {
479 omap_enable_gpio_module(bank, offset);
480 omap_set_gpio_direction(bank, offset, 1);
481 }
482 bank->irq_usage |= BIT(offset);
483 }
484
485 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
486 {
487 struct gpio_bank *bank = omap_irq_data_get_bank(d);
488 int retval;
489 unsigned long flags;
490 unsigned offset = d->hwirq;
491
492 if (type & ~IRQ_TYPE_SENSE_MASK)
493 return -EINVAL;
494
495 if (!bank->regs->leveldetect0 &&
496 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
497 return -EINVAL;
498
499 if (!BANK_USED(bank))
500 pm_runtime_get_sync(bank->dev);
501
502 raw_spin_lock_irqsave(&bank->lock, flags);
503 retval = omap_set_gpio_triggering(bank, offset, type);
504 if (retval) {
505 raw_spin_unlock_irqrestore(&bank->lock, flags);
506 goto error;
507 }
508 omap_gpio_init_irq(bank, offset);
509 if (!omap_gpio_is_input(bank, offset)) {
510 raw_spin_unlock_irqrestore(&bank->lock, flags);
511 retval = -EINVAL;
512 goto error;
513 }
514 raw_spin_unlock_irqrestore(&bank->lock, flags);
515
516 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
517 irq_set_handler_locked(d, handle_level_irq);
518 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
519 irq_set_handler_locked(d, handle_edge_irq);
520
521 return 0;
522
523 error:
524 if (!BANK_USED(bank))
525 pm_runtime_put(bank->dev);
526 return retval;
527 }
528
529 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
530 {
531 void __iomem *reg = bank->base;
532
533 reg += bank->regs->irqstatus;
534 writel_relaxed(gpio_mask, reg);
535
536 /* Workaround for clearing DSP GPIO interrupts to allow retention */
537 if (bank->regs->irqstatus2) {
538 reg = bank->base + bank->regs->irqstatus2;
539 writel_relaxed(gpio_mask, reg);
540 }
541
542 /* Flush posted write for the irq status to avoid spurious interrupts */
543 readl_relaxed(reg);
544 }
545
546 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
547 unsigned offset)
548 {
549 omap_clear_gpio_irqbank(bank, BIT(offset));
550 }
551
552 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
553 {
554 void __iomem *reg = bank->base;
555 u32 l;
556 u32 mask = (BIT(bank->width)) - 1;
557
558 reg += bank->regs->irqenable;
559 l = readl_relaxed(reg);
560 if (bank->regs->irqenable_inv)
561 l = ~l;
562 l &= mask;
563 return l;
564 }
565
566 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
567 {
568 void __iomem *reg = bank->base;
569 u32 l;
570
571 if (bank->regs->set_irqenable) {
572 reg += bank->regs->set_irqenable;
573 l = gpio_mask;
574 bank->context.irqenable1 |= gpio_mask;
575 } else {
576 reg += bank->regs->irqenable;
577 l = readl_relaxed(reg);
578 if (bank->regs->irqenable_inv)
579 l &= ~gpio_mask;
580 else
581 l |= gpio_mask;
582 bank->context.irqenable1 = l;
583 }
584
585 writel_relaxed(l, reg);
586 }
587
588 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
589 {
590 void __iomem *reg = bank->base;
591 u32 l;
592
593 if (bank->regs->clr_irqenable) {
594 reg += bank->regs->clr_irqenable;
595 l = gpio_mask;
596 bank->context.irqenable1 &= ~gpio_mask;
597 } else {
598 reg += bank->regs->irqenable;
599 l = readl_relaxed(reg);
600 if (bank->regs->irqenable_inv)
601 l |= gpio_mask;
602 else
603 l &= ~gpio_mask;
604 bank->context.irqenable1 = l;
605 }
606
607 writel_relaxed(l, reg);
608 }
609
610 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
611 unsigned offset, int enable)
612 {
613 if (enable)
614 omap_enable_gpio_irqbank(bank, BIT(offset));
615 else
616 omap_disable_gpio_irqbank(bank, BIT(offset));
617 }
618
619 /*
620 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
621 * 1510 does not seem to have a wake-up register. If JTAG is connected
622 * to the target, system will wake up always on GPIO events. While
623 * system is running all registered GPIO interrupts need to have wake-up
624 * enabled. When system is suspended, only selected GPIO interrupts need
625 * to have wake-up enabled.
626 */
627 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
628 int enable)
629 {
630 u32 gpio_bit = BIT(offset);
631 unsigned long flags;
632
633 if (bank->non_wakeup_gpios & gpio_bit) {
634 dev_err(bank->dev,
635 "Unable to modify wakeup on non-wakeup GPIO%d\n",
636 offset);
637 return -EINVAL;
638 }
639
640 raw_spin_lock_irqsave(&bank->lock, flags);
641 if (enable)
642 bank->context.wake_en |= gpio_bit;
643 else
644 bank->context.wake_en &= ~gpio_bit;
645
646 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
647 raw_spin_unlock_irqrestore(&bank->lock, flags);
648
649 return 0;
650 }
651
652 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
653 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
654 {
655 struct gpio_bank *bank = omap_irq_data_get_bank(d);
656 unsigned offset = d->hwirq;
657
658 return omap_set_gpio_wakeup(bank, offset, enable);
659 }
660
661 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
662 {
663 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
664 unsigned long flags;
665
666 /*
667 * If this is the first gpio_request for the bank,
668 * enable the bank module.
669 */
670 if (!BANK_USED(bank))
671 pm_runtime_get_sync(bank->dev);
672
673 raw_spin_lock_irqsave(&bank->lock, flags);
674 omap_enable_gpio_module(bank, offset);
675 bank->mod_usage |= BIT(offset);
676 raw_spin_unlock_irqrestore(&bank->lock, flags);
677
678 return 0;
679 }
680
681 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
682 {
683 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
684 unsigned long flags;
685
686 raw_spin_lock_irqsave(&bank->lock, flags);
687 bank->mod_usage &= ~(BIT(offset));
688 if (!LINE_USED(bank->irq_usage, offset)) {
689 omap_set_gpio_direction(bank, offset, 1);
690 omap_clear_gpio_debounce(bank, offset);
691 }
692 omap_disable_gpio_module(bank, offset);
693 raw_spin_unlock_irqrestore(&bank->lock, flags);
694
695 /*
696 * If this is the last gpio to be freed in the bank,
697 * disable the bank module.
698 */
699 if (!BANK_USED(bank))
700 pm_runtime_put(bank->dev);
701 }
702
703 /*
704 * We need to unmask the GPIO bank interrupt as soon as possible to
705 * avoid missing GPIO interrupts for other lines in the bank.
706 * Then we need to mask-read-clear-unmask the triggered GPIO lines
707 * in the bank to avoid missing nested interrupts for a GPIO line.
708 * If we wait to unmask individual GPIO lines in the bank after the
709 * line's interrupt handler has been run, we may miss some nested
710 * interrupts.
711 */
712 static void omap_gpio_irq_handler(struct irq_desc *desc)
713 {
714 void __iomem *isr_reg = NULL;
715 u32 isr;
716 unsigned int bit;
717 struct gpio_bank *bank;
718 int unmasked = 0;
719 struct irq_chip *irqchip = irq_desc_get_chip(desc);
720 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
721 unsigned long lock_flags;
722
723 chained_irq_enter(irqchip, desc);
724
725 bank = container_of(chip, struct gpio_bank, chip);
726 isr_reg = bank->base + bank->regs->irqstatus;
727 pm_runtime_get_sync(bank->dev);
728
729 if (WARN_ON(!isr_reg))
730 goto exit;
731
732 while (1) {
733 u32 isr_saved, level_mask = 0;
734 u32 enabled;
735
736 raw_spin_lock_irqsave(&bank->lock, lock_flags);
737
738 enabled = omap_get_gpio_irqbank_mask(bank);
739 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
740
741 if (bank->level_mask)
742 level_mask = bank->level_mask & enabled;
743
744 /* clear edge sensitive interrupts before handler(s) are
745 called so that we don't miss any interrupt occurred while
746 executing them */
747 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
748 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
749 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
750
751 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
752
753 /* if there is only edge sensitive GPIO pin interrupts
754 configured, we could unmask GPIO bank interrupt immediately */
755 if (!level_mask && !unmasked) {
756 unmasked = 1;
757 chained_irq_exit(irqchip, desc);
758 }
759
760 if (!isr)
761 break;
762
763 while (isr) {
764 bit = __ffs(isr);
765 isr &= ~(BIT(bit));
766
767 raw_spin_lock_irqsave(&bank->lock, lock_flags);
768 /*
769 * Some chips can't respond to both rising and falling
770 * at the same time. If this irq was requested with
771 * both flags, we need to flip the ICR data for the IRQ
772 * to respond to the IRQ for the opposite direction.
773 * This will be indicated in the bank toggle_mask.
774 */
775 if (bank->toggle_mask & (BIT(bit)))
776 omap_toggle_gpio_edge_triggering(bank, bit);
777
778 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
779
780 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
781 bit));
782 }
783 }
784 /* if bank has any level sensitive GPIO pin interrupt
785 configured, we must unmask the bank interrupt only after
786 handler(s) are executed in order to avoid spurious bank
787 interrupt */
788 exit:
789 if (!unmasked)
790 chained_irq_exit(irqchip, desc);
791 pm_runtime_put(bank->dev);
792 }
793
794 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
795 {
796 struct gpio_bank *bank = omap_irq_data_get_bank(d);
797 unsigned long flags;
798 unsigned offset = d->hwirq;
799
800 if (!BANK_USED(bank))
801 pm_runtime_get_sync(bank->dev);
802
803 raw_spin_lock_irqsave(&bank->lock, flags);
804
805 if (!LINE_USED(bank->mod_usage, offset))
806 omap_set_gpio_direction(bank, offset, 1);
807 else if (!omap_gpio_is_input(bank, offset))
808 goto err;
809 omap_enable_gpio_module(bank, offset);
810 bank->irq_usage |= BIT(offset);
811
812 raw_spin_unlock_irqrestore(&bank->lock, flags);
813 omap_gpio_unmask_irq(d);
814
815 return 0;
816 err:
817 raw_spin_unlock_irqrestore(&bank->lock, flags);
818 if (!BANK_USED(bank))
819 pm_runtime_put(bank->dev);
820 return -EINVAL;
821 }
822
823 static void omap_gpio_irq_shutdown(struct irq_data *d)
824 {
825 struct gpio_bank *bank = omap_irq_data_get_bank(d);
826 unsigned long flags;
827 unsigned offset = d->hwirq;
828
829 raw_spin_lock_irqsave(&bank->lock, flags);
830 bank->irq_usage &= ~(BIT(offset));
831 omap_set_gpio_irqenable(bank, offset, 0);
832 omap_clear_gpio_irqstatus(bank, offset);
833 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
834 if (!LINE_USED(bank->mod_usage, offset))
835 omap_clear_gpio_debounce(bank, offset);
836 omap_disable_gpio_module(bank, offset);
837 raw_spin_unlock_irqrestore(&bank->lock, flags);
838
839 /*
840 * If this is the last IRQ to be freed in the bank,
841 * disable the bank module.
842 */
843 if (!BANK_USED(bank))
844 pm_runtime_put(bank->dev);
845 }
846
847 static void omap_gpio_ack_irq(struct irq_data *d)
848 {
849 struct gpio_bank *bank = omap_irq_data_get_bank(d);
850 unsigned offset = d->hwirq;
851
852 omap_clear_gpio_irqstatus(bank, offset);
853 }
854
855 static void omap_gpio_mask_irq(struct irq_data *d)
856 {
857 struct gpio_bank *bank = omap_irq_data_get_bank(d);
858 unsigned offset = d->hwirq;
859 unsigned long flags;
860
861 raw_spin_lock_irqsave(&bank->lock, flags);
862 omap_set_gpio_irqenable(bank, offset, 0);
863 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
864 raw_spin_unlock_irqrestore(&bank->lock, flags);
865 }
866
867 static void omap_gpio_unmask_irq(struct irq_data *d)
868 {
869 struct gpio_bank *bank = omap_irq_data_get_bank(d);
870 unsigned offset = d->hwirq;
871 u32 trigger = irqd_get_trigger_type(d);
872 unsigned long flags;
873
874 raw_spin_lock_irqsave(&bank->lock, flags);
875 if (trigger)
876 omap_set_gpio_triggering(bank, offset, trigger);
877
878 /* For level-triggered GPIOs, the clearing must be done after
879 * the HW source is cleared, thus after the handler has run */
880 if (bank->level_mask & BIT(offset)) {
881 omap_set_gpio_irqenable(bank, offset, 0);
882 omap_clear_gpio_irqstatus(bank, offset);
883 }
884
885 omap_set_gpio_irqenable(bank, offset, 1);
886 raw_spin_unlock_irqrestore(&bank->lock, flags);
887 }
888
889 /*---------------------------------------------------------------------*/
890
891 static int omap_mpuio_suspend_noirq(struct device *dev)
892 {
893 struct platform_device *pdev = to_platform_device(dev);
894 struct gpio_bank *bank = platform_get_drvdata(pdev);
895 void __iomem *mask_reg = bank->base +
896 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
897 unsigned long flags;
898
899 raw_spin_lock_irqsave(&bank->lock, flags);
900 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
901 raw_spin_unlock_irqrestore(&bank->lock, flags);
902
903 return 0;
904 }
905
906 static int omap_mpuio_resume_noirq(struct device *dev)
907 {
908 struct platform_device *pdev = to_platform_device(dev);
909 struct gpio_bank *bank = platform_get_drvdata(pdev);
910 void __iomem *mask_reg = bank->base +
911 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
912 unsigned long flags;
913
914 raw_spin_lock_irqsave(&bank->lock, flags);
915 writel_relaxed(bank->context.wake_en, mask_reg);
916 raw_spin_unlock_irqrestore(&bank->lock, flags);
917
918 return 0;
919 }
920
921 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
922 .suspend_noirq = omap_mpuio_suspend_noirq,
923 .resume_noirq = omap_mpuio_resume_noirq,
924 };
925
926 /* use platform_driver for this. */
927 static struct platform_driver omap_mpuio_driver = {
928 .driver = {
929 .name = "mpuio",
930 .pm = &omap_mpuio_dev_pm_ops,
931 },
932 };
933
934 static struct platform_device omap_mpuio_device = {
935 .name = "mpuio",
936 .id = -1,
937 .dev = {
938 .driver = &omap_mpuio_driver.driver,
939 }
940 /* could list the /proc/iomem resources */
941 };
942
943 static inline void omap_mpuio_init(struct gpio_bank *bank)
944 {
945 platform_set_drvdata(&omap_mpuio_device, bank);
946
947 if (platform_driver_register(&omap_mpuio_driver) == 0)
948 (void) platform_device_register(&omap_mpuio_device);
949 }
950
951 /*---------------------------------------------------------------------*/
952
953 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
954 {
955 struct gpio_bank *bank;
956 unsigned long flags;
957 void __iomem *reg;
958 int dir;
959
960 bank = container_of(chip, struct gpio_bank, chip);
961 reg = bank->base + bank->regs->direction;
962 raw_spin_lock_irqsave(&bank->lock, flags);
963 dir = !!(readl_relaxed(reg) & BIT(offset));
964 raw_spin_unlock_irqrestore(&bank->lock, flags);
965 return dir;
966 }
967
968 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
969 {
970 struct gpio_bank *bank;
971 unsigned long flags;
972
973 bank = container_of(chip, struct gpio_bank, chip);
974 raw_spin_lock_irqsave(&bank->lock, flags);
975 omap_set_gpio_direction(bank, offset, 1);
976 raw_spin_unlock_irqrestore(&bank->lock, flags);
977 return 0;
978 }
979
980 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
981 {
982 struct gpio_bank *bank;
983
984 bank = container_of(chip, struct gpio_bank, chip);
985
986 if (omap_gpio_is_input(bank, offset))
987 return omap_get_gpio_datain(bank, offset);
988 else
989 return omap_get_gpio_dataout(bank, offset);
990 }
991
992 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
993 {
994 struct gpio_bank *bank;
995 unsigned long flags;
996
997 bank = container_of(chip, struct gpio_bank, chip);
998 raw_spin_lock_irqsave(&bank->lock, flags);
999 bank->set_dataout(bank, offset, value);
1000 omap_set_gpio_direction(bank, offset, 0);
1001 raw_spin_unlock_irqrestore(&bank->lock, flags);
1002 return 0;
1003 }
1004
1005 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1006 unsigned debounce)
1007 {
1008 struct gpio_bank *bank;
1009 unsigned long flags;
1010
1011 bank = container_of(chip, struct gpio_bank, chip);
1012
1013 raw_spin_lock_irqsave(&bank->lock, flags);
1014 omap2_set_gpio_debounce(bank, offset, debounce);
1015 raw_spin_unlock_irqrestore(&bank->lock, flags);
1016
1017 return 0;
1018 }
1019
1020 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1021 {
1022 struct gpio_bank *bank;
1023 unsigned long flags;
1024
1025 bank = container_of(chip, struct gpio_bank, chip);
1026 raw_spin_lock_irqsave(&bank->lock, flags);
1027 bank->set_dataout(bank, offset, value);
1028 raw_spin_unlock_irqrestore(&bank->lock, flags);
1029 }
1030
1031 /*---------------------------------------------------------------------*/
1032
1033 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1034 {
1035 static bool called;
1036 u32 rev;
1037
1038 if (called || bank->regs->revision == USHRT_MAX)
1039 return;
1040
1041 rev = readw_relaxed(bank->base + bank->regs->revision);
1042 pr_info("OMAP GPIO hardware version %d.%d\n",
1043 (rev >> 4) & 0x0f, rev & 0x0f);
1044
1045 called = true;
1046 }
1047
1048 static void omap_gpio_mod_init(struct gpio_bank *bank)
1049 {
1050 void __iomem *base = bank->base;
1051 u32 l = 0xffffffff;
1052
1053 if (bank->width == 16)
1054 l = 0xffff;
1055
1056 if (bank->is_mpuio) {
1057 writel_relaxed(l, bank->base + bank->regs->irqenable);
1058 return;
1059 }
1060
1061 omap_gpio_rmw(base, bank->regs->irqenable, l,
1062 bank->regs->irqenable_inv);
1063 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1064 !bank->regs->irqenable_inv);
1065 if (bank->regs->debounce_en)
1066 writel_relaxed(0, base + bank->regs->debounce_en);
1067
1068 /* Save OE default value (0xffffffff) in the context */
1069 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1070 /* Initialize interface clk ungated, module enabled */
1071 if (bank->regs->ctrl)
1072 writel_relaxed(0, base + bank->regs->ctrl);
1073 }
1074
1075 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1076 {
1077 static int gpio;
1078 int irq_base = 0;
1079 int ret;
1080
1081 /*
1082 * REVISIT eventually switch from OMAP-specific gpio structs
1083 * over to the generic ones
1084 */
1085 bank->chip.request = omap_gpio_request;
1086 bank->chip.free = omap_gpio_free;
1087 bank->chip.get_direction = omap_gpio_get_direction;
1088 bank->chip.direction_input = omap_gpio_input;
1089 bank->chip.get = omap_gpio_get;
1090 bank->chip.direction_output = omap_gpio_output;
1091 bank->chip.set_debounce = omap_gpio_debounce;
1092 bank->chip.set = omap_gpio_set;
1093 if (bank->is_mpuio) {
1094 bank->chip.label = "mpuio";
1095 if (bank->regs->wkup_en)
1096 bank->chip.dev = &omap_mpuio_device.dev;
1097 bank->chip.base = OMAP_MPUIO(0);
1098 } else {
1099 bank->chip.label = "gpio";
1100 bank->chip.base = gpio;
1101 }
1102 bank->chip.ngpio = bank->width;
1103
1104 ret = gpiochip_add(&bank->chip);
1105 if (ret) {
1106 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1107 return ret;
1108 }
1109
1110 if (!bank->is_mpuio)
1111 gpio += bank->width;
1112
1113 #ifdef CONFIG_ARCH_OMAP1
1114 /*
1115 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1116 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1117 */
1118 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1119 if (irq_base < 0) {
1120 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1121 return -ENODEV;
1122 }
1123 #endif
1124
1125 /* MPUIO is a bit different, reading IRQ status clears it */
1126 if (bank->is_mpuio) {
1127 irqc->irq_ack = dummy_irq_chip.irq_ack;
1128 irqc->irq_mask = irq_gc_mask_set_bit;
1129 irqc->irq_unmask = irq_gc_mask_clr_bit;
1130 if (!bank->regs->wkup_en)
1131 irqc->irq_set_wake = NULL;
1132 }
1133
1134 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1135 irq_base, omap_gpio_irq_handler,
1136 IRQ_TYPE_NONE);
1137
1138 if (ret) {
1139 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1140 gpiochip_remove(&bank->chip);
1141 return -ENODEV;
1142 }
1143
1144 gpiochip_set_chained_irqchip(&bank->chip, irqc,
1145 bank->irq, omap_gpio_irq_handler);
1146
1147 return 0;
1148 }
1149
1150 static const struct of_device_id omap_gpio_match[];
1151
1152 static int omap_gpio_probe(struct platform_device *pdev)
1153 {
1154 struct device *dev = &pdev->dev;
1155 struct device_node *node = dev->of_node;
1156 const struct of_device_id *match;
1157 const struct omap_gpio_platform_data *pdata;
1158 struct resource *res;
1159 struct gpio_bank *bank;
1160 struct irq_chip *irqc;
1161 int ret;
1162
1163 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1164
1165 pdata = match ? match->data : dev_get_platdata(dev);
1166 if (!pdata)
1167 return -EINVAL;
1168
1169 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1170 if (!bank) {
1171 dev_err(dev, "Memory alloc failed\n");
1172 return -ENOMEM;
1173 }
1174
1175 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1176 if (!irqc)
1177 return -ENOMEM;
1178
1179 irqc->irq_startup = omap_gpio_irq_startup,
1180 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1181 irqc->irq_ack = omap_gpio_ack_irq,
1182 irqc->irq_mask = omap_gpio_mask_irq,
1183 irqc->irq_unmask = omap_gpio_unmask_irq,
1184 irqc->irq_set_type = omap_gpio_irq_type,
1185 irqc->irq_set_wake = omap_gpio_wake_enable,
1186 irqc->name = dev_name(&pdev->dev);
1187
1188 bank->irq = platform_get_irq(pdev, 0);
1189 if (bank->irq <= 0) {
1190 if (!bank->irq)
1191 bank->irq = -ENXIO;
1192 if (bank->irq != -EPROBE_DEFER)
1193 dev_err(dev,
1194 "can't get irq resource ret=%d\n", bank->irq);
1195 return bank->irq;
1196 }
1197
1198 bank->dev = dev;
1199 bank->chip.dev = dev;
1200 bank->chip.owner = THIS_MODULE;
1201 bank->dbck_flag = pdata->dbck_flag;
1202 bank->stride = pdata->bank_stride;
1203 bank->width = pdata->bank_width;
1204 bank->is_mpuio = pdata->is_mpuio;
1205 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1206 bank->regs = pdata->regs;
1207 #ifdef CONFIG_OF_GPIO
1208 bank->chip.of_node = of_node_get(node);
1209 #endif
1210 if (node) {
1211 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1212 bank->loses_context = true;
1213 } else {
1214 bank->loses_context = pdata->loses_context;
1215
1216 if (bank->loses_context)
1217 bank->get_context_loss_count =
1218 pdata->get_context_loss_count;
1219 }
1220
1221 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1222 bank->set_dataout = omap_set_gpio_dataout_reg;
1223 else
1224 bank->set_dataout = omap_set_gpio_dataout_mask;
1225
1226 raw_spin_lock_init(&bank->lock);
1227
1228 /* Static mapping, never released */
1229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1230 bank->base = devm_ioremap_resource(dev, res);
1231 if (IS_ERR(bank->base)) {
1232 return PTR_ERR(bank->base);
1233 }
1234
1235 if (bank->dbck_flag) {
1236 bank->dbck = devm_clk_get(bank->dev, "dbclk");
1237 if (IS_ERR(bank->dbck)) {
1238 dev_err(bank->dev,
1239 "Could not get gpio dbck. Disable debounce\n");
1240 bank->dbck_flag = false;
1241 } else {
1242 clk_prepare(bank->dbck);
1243 }
1244 }
1245
1246 platform_set_drvdata(pdev, bank);
1247
1248 pm_runtime_enable(bank->dev);
1249 pm_runtime_irq_safe(bank->dev);
1250 pm_runtime_get_sync(bank->dev);
1251
1252 if (bank->is_mpuio)
1253 omap_mpuio_init(bank);
1254
1255 omap_gpio_mod_init(bank);
1256
1257 ret = omap_gpio_chip_init(bank, irqc);
1258 if (ret) {
1259 pm_runtime_put_sync(bank->dev);
1260 pm_runtime_disable(bank->dev);
1261 return ret;
1262 }
1263
1264 omap_gpio_show_rev(bank);
1265
1266 pm_runtime_put(bank->dev);
1267
1268 list_add_tail(&bank->node, &omap_gpio_list);
1269
1270 return 0;
1271 }
1272
1273 static int omap_gpio_remove(struct platform_device *pdev)
1274 {
1275 struct gpio_bank *bank = platform_get_drvdata(pdev);
1276
1277 list_del(&bank->node);
1278 gpiochip_remove(&bank->chip);
1279 pm_runtime_disable(bank->dev);
1280 if (bank->dbck_flag)
1281 clk_unprepare(bank->dbck);
1282
1283 return 0;
1284 }
1285
1286 #ifdef CONFIG_ARCH_OMAP2PLUS
1287
1288 #if defined(CONFIG_PM)
1289 static void omap_gpio_restore_context(struct gpio_bank *bank);
1290
1291 static int omap_gpio_runtime_suspend(struct device *dev)
1292 {
1293 struct platform_device *pdev = to_platform_device(dev);
1294 struct gpio_bank *bank = platform_get_drvdata(pdev);
1295 u32 l1 = 0, l2 = 0;
1296 unsigned long flags;
1297 u32 wake_low, wake_hi;
1298
1299 raw_spin_lock_irqsave(&bank->lock, flags);
1300
1301 /*
1302 * Only edges can generate a wakeup event to the PRCM.
1303 *
1304 * Therefore, ensure any wake-up capable GPIOs have
1305 * edge-detection enabled before going idle to ensure a wakeup
1306 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1307 * NDA TRM 25.5.3.1)
1308 *
1309 * The normal values will be restored upon ->runtime_resume()
1310 * by writing back the values saved in bank->context.
1311 */
1312 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1313 if (wake_low)
1314 writel_relaxed(wake_low | bank->context.fallingdetect,
1315 bank->base + bank->regs->fallingdetect);
1316 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1317 if (wake_hi)
1318 writel_relaxed(wake_hi | bank->context.risingdetect,
1319 bank->base + bank->regs->risingdetect);
1320
1321 if (!bank->enabled_non_wakeup_gpios)
1322 goto update_gpio_context_count;
1323
1324 if (bank->power_mode != OFF_MODE) {
1325 bank->power_mode = 0;
1326 goto update_gpio_context_count;
1327 }
1328 /*
1329 * If going to OFF, remove triggering for all
1330 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1331 * generated. See OMAP2420 Errata item 1.101.
1332 */
1333 bank->saved_datain = readl_relaxed(bank->base +
1334 bank->regs->datain);
1335 l1 = bank->context.fallingdetect;
1336 l2 = bank->context.risingdetect;
1337
1338 l1 &= ~bank->enabled_non_wakeup_gpios;
1339 l2 &= ~bank->enabled_non_wakeup_gpios;
1340
1341 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1342 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1343
1344 bank->workaround_enabled = true;
1345
1346 update_gpio_context_count:
1347 if (bank->get_context_loss_count)
1348 bank->context_loss_count =
1349 bank->get_context_loss_count(bank->dev);
1350
1351 omap_gpio_dbck_disable(bank);
1352 raw_spin_unlock_irqrestore(&bank->lock, flags);
1353
1354 return 0;
1355 }
1356
1357 static void omap_gpio_init_context(struct gpio_bank *p);
1358
1359 static int omap_gpio_runtime_resume(struct device *dev)
1360 {
1361 struct platform_device *pdev = to_platform_device(dev);
1362 struct gpio_bank *bank = platform_get_drvdata(pdev);
1363 u32 l = 0, gen, gen0, gen1;
1364 unsigned long flags;
1365 int c;
1366
1367 raw_spin_lock_irqsave(&bank->lock, flags);
1368
1369 /*
1370 * On the first resume during the probe, the context has not
1371 * been initialised and so initialise it now. Also initialise
1372 * the context loss count.
1373 */
1374 if (bank->loses_context && !bank->context_valid) {
1375 omap_gpio_init_context(bank);
1376
1377 if (bank->get_context_loss_count)
1378 bank->context_loss_count =
1379 bank->get_context_loss_count(bank->dev);
1380 }
1381
1382 omap_gpio_dbck_enable(bank);
1383
1384 /*
1385 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1386 * GPIOs were set to edge trigger also in order to be able to
1387 * generate a PRCM wakeup. Here we restore the
1388 * pre-runtime_suspend() values for edge triggering.
1389 */
1390 writel_relaxed(bank->context.fallingdetect,
1391 bank->base + bank->regs->fallingdetect);
1392 writel_relaxed(bank->context.risingdetect,
1393 bank->base + bank->regs->risingdetect);
1394
1395 if (bank->loses_context) {
1396 if (!bank->get_context_loss_count) {
1397 omap_gpio_restore_context(bank);
1398 } else {
1399 c = bank->get_context_loss_count(bank->dev);
1400 if (c != bank->context_loss_count) {
1401 omap_gpio_restore_context(bank);
1402 } else {
1403 raw_spin_unlock_irqrestore(&bank->lock, flags);
1404 return 0;
1405 }
1406 }
1407 }
1408
1409 if (!bank->workaround_enabled) {
1410 raw_spin_unlock_irqrestore(&bank->lock, flags);
1411 return 0;
1412 }
1413
1414 l = readl_relaxed(bank->base + bank->regs->datain);
1415
1416 /*
1417 * Check if any of the non-wakeup interrupt GPIOs have changed
1418 * state. If so, generate an IRQ by software. This is
1419 * horribly racy, but it's the best we can do to work around
1420 * this silicon bug.
1421 */
1422 l ^= bank->saved_datain;
1423 l &= bank->enabled_non_wakeup_gpios;
1424
1425 /*
1426 * No need to generate IRQs for the rising edge for gpio IRQs
1427 * configured with falling edge only; and vice versa.
1428 */
1429 gen0 = l & bank->context.fallingdetect;
1430 gen0 &= bank->saved_datain;
1431
1432 gen1 = l & bank->context.risingdetect;
1433 gen1 &= ~(bank->saved_datain);
1434
1435 /* FIXME: Consider GPIO IRQs with level detections properly! */
1436 gen = l & (~(bank->context.fallingdetect) &
1437 ~(bank->context.risingdetect));
1438 /* Consider all GPIO IRQs needed to be updated */
1439 gen |= gen0 | gen1;
1440
1441 if (gen) {
1442 u32 old0, old1;
1443
1444 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1445 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1446
1447 if (!bank->regs->irqstatus_raw0) {
1448 writel_relaxed(old0 | gen, bank->base +
1449 bank->regs->leveldetect0);
1450 writel_relaxed(old1 | gen, bank->base +
1451 bank->regs->leveldetect1);
1452 }
1453
1454 if (bank->regs->irqstatus_raw0) {
1455 writel_relaxed(old0 | l, bank->base +
1456 bank->regs->leveldetect0);
1457 writel_relaxed(old1 | l, bank->base +
1458 bank->regs->leveldetect1);
1459 }
1460 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1461 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1462 }
1463
1464 bank->workaround_enabled = false;
1465 raw_spin_unlock_irqrestore(&bank->lock, flags);
1466
1467 return 0;
1468 }
1469 #endif /* CONFIG_PM */
1470
1471 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1472 void omap2_gpio_prepare_for_idle(int pwr_mode)
1473 {
1474 struct gpio_bank *bank;
1475
1476 list_for_each_entry(bank, &omap_gpio_list, node) {
1477 if (!BANK_USED(bank) || !bank->loses_context)
1478 continue;
1479
1480 bank->power_mode = pwr_mode;
1481
1482 pm_runtime_put_sync_suspend(bank->dev);
1483 }
1484 }
1485
1486 void omap2_gpio_resume_after_idle(void)
1487 {
1488 struct gpio_bank *bank;
1489
1490 list_for_each_entry(bank, &omap_gpio_list, node) {
1491 if (!BANK_USED(bank) || !bank->loses_context)
1492 continue;
1493
1494 pm_runtime_get_sync(bank->dev);
1495 }
1496 }
1497 #endif
1498
1499 #if defined(CONFIG_PM)
1500 static void omap_gpio_init_context(struct gpio_bank *p)
1501 {
1502 struct omap_gpio_reg_offs *regs = p->regs;
1503 void __iomem *base = p->base;
1504
1505 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1506 p->context.oe = readl_relaxed(base + regs->direction);
1507 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1508 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1509 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1510 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1511 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1512 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1513 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1514
1515 if (regs->set_dataout && p->regs->clr_dataout)
1516 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1517 else
1518 p->context.dataout = readl_relaxed(base + regs->dataout);
1519
1520 p->context_valid = true;
1521 }
1522
1523 static void omap_gpio_restore_context(struct gpio_bank *bank)
1524 {
1525 writel_relaxed(bank->context.wake_en,
1526 bank->base + bank->regs->wkup_en);
1527 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1528 writel_relaxed(bank->context.leveldetect0,
1529 bank->base + bank->regs->leveldetect0);
1530 writel_relaxed(bank->context.leveldetect1,
1531 bank->base + bank->regs->leveldetect1);
1532 writel_relaxed(bank->context.risingdetect,
1533 bank->base + bank->regs->risingdetect);
1534 writel_relaxed(bank->context.fallingdetect,
1535 bank->base + bank->regs->fallingdetect);
1536 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1537 writel_relaxed(bank->context.dataout,
1538 bank->base + bank->regs->set_dataout);
1539 else
1540 writel_relaxed(bank->context.dataout,
1541 bank->base + bank->regs->dataout);
1542 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1543
1544 if (bank->dbck_enable_mask) {
1545 writel_relaxed(bank->context.debounce, bank->base +
1546 bank->regs->debounce);
1547 writel_relaxed(bank->context.debounce_en,
1548 bank->base + bank->regs->debounce_en);
1549 }
1550
1551 writel_relaxed(bank->context.irqenable1,
1552 bank->base + bank->regs->irqenable);
1553 writel_relaxed(bank->context.irqenable2,
1554 bank->base + bank->regs->irqenable2);
1555 }
1556 #endif /* CONFIG_PM */
1557 #else
1558 #define omap_gpio_runtime_suspend NULL
1559 #define omap_gpio_runtime_resume NULL
1560 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1561 #endif
1562
1563 static const struct dev_pm_ops gpio_pm_ops = {
1564 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1565 NULL)
1566 };
1567
1568 #if defined(CONFIG_OF)
1569 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1570 .revision = OMAP24XX_GPIO_REVISION,
1571 .direction = OMAP24XX_GPIO_OE,
1572 .datain = OMAP24XX_GPIO_DATAIN,
1573 .dataout = OMAP24XX_GPIO_DATAOUT,
1574 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1575 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1576 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1577 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1578 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1579 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1580 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1581 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1582 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1583 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1584 .ctrl = OMAP24XX_GPIO_CTRL,
1585 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1586 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1587 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1588 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1589 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1590 };
1591
1592 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1593 .revision = OMAP4_GPIO_REVISION,
1594 .direction = OMAP4_GPIO_OE,
1595 .datain = OMAP4_GPIO_DATAIN,
1596 .dataout = OMAP4_GPIO_DATAOUT,
1597 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1598 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1599 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1600 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1601 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1602 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1603 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1604 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1605 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1606 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1607 .ctrl = OMAP4_GPIO_CTRL,
1608 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1609 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1610 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1611 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1612 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1613 };
1614
1615 static const struct omap_gpio_platform_data omap2_pdata = {
1616 .regs = &omap2_gpio_regs,
1617 .bank_width = 32,
1618 .dbck_flag = false,
1619 };
1620
1621 static const struct omap_gpio_platform_data omap3_pdata = {
1622 .regs = &omap2_gpio_regs,
1623 .bank_width = 32,
1624 .dbck_flag = true,
1625 };
1626
1627 static const struct omap_gpio_platform_data omap4_pdata = {
1628 .regs = &omap4_gpio_regs,
1629 .bank_width = 32,
1630 .dbck_flag = true,
1631 };
1632
1633 static const struct of_device_id omap_gpio_match[] = {
1634 {
1635 .compatible = "ti,omap4-gpio",
1636 .data = &omap4_pdata,
1637 },
1638 {
1639 .compatible = "ti,omap3-gpio",
1640 .data = &omap3_pdata,
1641 },
1642 {
1643 .compatible = "ti,omap2-gpio",
1644 .data = &omap2_pdata,
1645 },
1646 { },
1647 };
1648 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1649 #endif
1650
1651 static struct platform_driver omap_gpio_driver = {
1652 .probe = omap_gpio_probe,
1653 .remove = omap_gpio_remove,
1654 .driver = {
1655 .name = "omap_gpio",
1656 .pm = &gpio_pm_ops,
1657 .of_match_table = of_match_ptr(omap_gpio_match),
1658 },
1659 };
1660
1661 /*
1662 * gpio driver register needs to be done before
1663 * machine_init functions access gpio APIs.
1664 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1665 */
1666 static int __init omap_gpio_drv_reg(void)
1667 {
1668 return platform_driver_register(&omap_gpio_driver);
1669 }
1670 postcore_initcall(omap_gpio_drv_reg);
1671
1672 static void __exit omap_gpio_exit(void)
1673 {
1674 platform_driver_unregister(&omap_gpio_driver);
1675 }
1676 module_exit(omap_gpio_exit);
1677
1678 MODULE_DESCRIPTION("omap gpio driver");
1679 MODULE_ALIAS("platform:gpio-omap");
1680 MODULE_LICENSE("GPL v2");
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