drivers/gpio/gpio-pl061.c

   1 /*
   2  * Copyright (C) 2008, 2009 Provigent Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
   9  *
  10  * Data sheet: ARM DDI 0190B, September 2000
  11  */
  12 #include <linux/spinlock.h>
  13 #include <linux/errno.h>
  14 #include <linux/module.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqchip/chained_irq.h>
  19 #include <linux/bitops.h>
  20 #include <linux/gpio.h>
  21 #include <linux/device.h>
  22 #include <linux/amba/bus.h>
  23 #include <linux/amba/pl061.h>
  24 #include <linux/slab.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/pm.h>
  27
  28 #define GPIODIR 0x400
  29 #define GPIOIS  0x404
  30 #define GPIOIBE 0x408
  31 #define GPIOIEV 0x40C
  32 #define GPIOIE  0x410
  33 #define GPIORIS 0x414
  34 #define GPIOMIS 0x418
  35 #define GPIOIC  0x41C
  36
  37 #define PL061_GPIO_NR   8
  38
  39 #ifdef CONFIG_PM
  40 struct pl061_context_save_regs {
  41         u8 gpio_data;
  42         u8 gpio_dir;
  43         u8 gpio_is;
  44         u8 gpio_ibe;
  45         u8 gpio_iev;
  46         u8 gpio_ie;
  47 };
  48 #endif
  49
  50 struct pl061_gpio {
  51         spinlock_t              lock;
  52
  53         void __iomem            *base;
  54         struct gpio_chip        gc;
  55
  56 #ifdef CONFIG_PM
  57         struct pl061_context_save_regs csave_regs;
  58 #endif
  59 };
  60
  61 static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
  62 {
  63         /*
  64          * Map back to global GPIO space and request muxing, the direction
  65          * parameter does not matter for this controller.
  66          */
  67         int gpio = chip->base + offset;
  68
  69         return pinctrl_request_gpio(gpio);
  70 }
  71
  72 static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
  73 {
  74         int gpio = chip->base + offset;
  75
  76         pinctrl_free_gpio(gpio);
  77 }
  78
  79 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
  80 {
  81         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
  82         unsigned long flags;
  83         unsigned char gpiodir;
  84
  85         if (offset >= gc->ngpio)
  86                 return -EINVAL;
  87
  88         spin_lock_irqsave(&chip->lock, flags);
  89         gpiodir = readb(chip->base + GPIODIR);
  90         gpiodir &= ~(BIT(offset));
  91         writeb(gpiodir, chip->base + GPIODIR);
  92         spin_unlock_irqrestore(&chip->lock, flags);
  93
  94         return 0;
  95 }
  96
  97 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
  98                 int value)
  99 {
 100         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 101         unsigned long flags;
 102         unsigned char gpiodir;
 103
 104         if (offset >= gc->ngpio)
 105                 return -EINVAL;
 106
 107         spin_lock_irqsave(&chip->lock, flags);
 108         writeb(!!value << offset, chip->base + (BIT(offset + 2)));
 109         gpiodir = readb(chip->base + GPIODIR);
 110         gpiodir |= BIT(offset);
 111         writeb(gpiodir, chip->base + GPIODIR);
 112
 113         /*
 114          * gpio value is set again, because pl061 doesn't allow to set value of
 115          * a gpio pin before configuring it in OUT mode.
 116          */
 117         writeb(!!value << offset, chip->base + (BIT(offset + 2)));
 118         spin_unlock_irqrestore(&chip->lock, flags);
 119
 120         return 0;
 121 }
 122
 123 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
 124 {
 125         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 126
 127         return !!readb(chip->base + (BIT(offset + 2)));
 128 }
 129
 130 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
 131 {
 132         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 133
 134         writeb(!!value << offset, chip->base + (BIT(offset + 2)));
 135 }
 136
 137 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
 138 {
 139         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 140         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 141         int offset = irqd_to_hwirq(d);
 142         unsigned long flags;
 143         u8 gpiois, gpioibe, gpioiev;
 144         u8 bit = BIT(offset);
 145
 146         if (offset < 0 || offset >= PL061_GPIO_NR)
 147                 return -EINVAL;
 148
 149         spin_lock_irqsave(&chip->lock, flags);
 150
 151         gpioiev = readb(chip->base + GPIOIEV);
 152         gpiois = readb(chip->base + GPIOIS);
 153         gpioibe = readb(chip->base + GPIOIBE);
 154
 155         if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 156                 gpiois |= bit;
 157                 if (trigger & IRQ_TYPE_LEVEL_HIGH)
 158                         gpioiev |= bit;
 159                 else
 160                         gpioiev &= ~bit;
 161         } else
 162                 gpiois &= ~bit;
 163
 164         if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
 165                 /* Setting this makes GPIOEV be ignored */
 166                 gpioibe |= bit;
 167         else {
 168                 gpioibe &= ~bit;
 169                 if (trigger & IRQ_TYPE_EDGE_RISING)
 170                         gpioiev |= bit;
 171                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 172                         gpioiev &= ~bit;
 173         }
 174
 175         writeb(gpiois, chip->base + GPIOIS);
 176         writeb(gpioibe, chip->base + GPIOIBE);
 177         writeb(gpioiev, chip->base + GPIOIEV);
 178
 179         spin_unlock_irqrestore(&chip->lock, flags);
 180
 181         return 0;
 182 }
 183
 184 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
 185 {
 186         unsigned long pending;
 187         int offset;
 188         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 189         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 190         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 191
 192         chained_irq_enter(irqchip, desc);
 193
 194         pending = readb(chip->base + GPIOMIS);
 195         writeb(pending, chip->base + GPIOIC);
 196         if (pending) {
 197                 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
 198                         generic_handle_irq(irq_find_mapping(gc->irqdomain,
 199                                                             offset));
 200         }
 201
 202         chained_irq_exit(irqchip, desc);
 203 }
 204
 205 static void pl061_irq_mask(struct irq_data *d)
 206 {
 207         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 208         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 209         u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
 210         u8 gpioie;
 211
 212         spin_lock(&chip->lock);
 213         gpioie = readb(chip->base + GPIOIE) & ~mask;
 214         writeb(gpioie, chip->base + GPIOIE);
 215         spin_unlock(&chip->lock);
 216 }
 217
 218 static void pl061_irq_unmask(struct irq_data *d)
 219 {
 220         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 221         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 222         u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
 223         u8 gpioie;
 224
 225         spin_lock(&chip->lock);
 226         gpioie = readb(chip->base + GPIOIE) | mask;
 227         writeb(gpioie, chip->base + GPIOIE);
 228         spin_unlock(&chip->lock);
 229 }
 230
 231 static struct irq_chip pl061_irqchip = {
 232         .name           = "pl061",
 233         .irq_mask       = pl061_irq_mask,
 234         .irq_unmask     = pl061_irq_unmask,
 235         .irq_set_type   = pl061_irq_type,
 236 };
 237
 238 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
 239 {
 240         struct device *dev = &adev->dev;
 241         struct pl061_platform_data *pdata = dev_get_platdata(dev);
 242         struct pl061_gpio *chip;
 243         int ret, irq, i, irq_base;
 244
 245         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
 246         if (chip == NULL)
 247                 return -ENOMEM;
 248
 249         if (pdata) {
 250                 chip->gc.base = pdata->gpio_base;
 251                 irq_base = pdata->irq_base;
 252                 if (irq_base <= 0) {
 253                         dev_err(&adev->dev, "invalid IRQ base in pdata\n");
 254                         return -ENODEV;
 255                 }
 256         } else {
 257                 chip->gc.base = -1;
 258                 irq_base = 0;
 259         }
 260
 261         chip->base = devm_ioremap_resource(dev, &adev->res);
 262         if (IS_ERR(chip->base))
 263                 return PTR_ERR(chip->base);
 264
 265         spin_lock_init(&chip->lock);
 266
 267         chip->gc.request = pl061_gpio_request;
 268         chip->gc.free = pl061_gpio_free;
 269         chip->gc.direction_input = pl061_direction_input;
 270         chip->gc.direction_output = pl061_direction_output;
 271         chip->gc.get = pl061_get_value;
 272         chip->gc.set = pl061_set_value;
 273         chip->gc.ngpio = PL061_GPIO_NR;
 274         chip->gc.label = dev_name(dev);
 275         chip->gc.dev = dev;
 276         chip->gc.owner = THIS_MODULE;
 277
 278         ret = gpiochip_add(&chip->gc);
 279         if (ret)
 280                 return ret;
 281
 282         /*
 283          * irq_chip support
 284          */
 285         writeb(0, chip->base + GPIOIE); /* disable irqs */
 286         irq = adev->irq[0];
 287         if (irq < 0) {
 288                 dev_err(&adev->dev, "invalid IRQ\n");
 289                 return -ENODEV;
 290         }
 291
 292         ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
 293                                    irq_base, handle_simple_irq,
 294                                    IRQ_TYPE_NONE);
 295         if (ret) {
 296                 dev_info(&adev->dev, "could not add irqchip\n");
 297                 return ret;
 298         }
 299         gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
 300                                      irq, pl061_irq_handler);
 301
 302         for (i = 0; i < PL061_GPIO_NR; i++) {
 303                 if (pdata) {
 304                         if (pdata->directions & (BIT(i)))
 305                                 pl061_direction_output(&chip->gc, i,
 306                                                 pdata->values & (BIT(i)));
 307                         else
 308                                 pl061_direction_input(&chip->gc, i);
 309                 }
 310         }
 311
 312         amba_set_drvdata(adev, chip);
 313         dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
 314                  &adev->res.start);
 315
 316         return 0;
 317 }
 318
 319 #ifdef CONFIG_PM
 320 static int pl061_suspend(struct device *dev)
 321 {
 322         struct pl061_gpio *chip = dev_get_drvdata(dev);
 323         int offset;
 324
 325         chip->csave_regs.gpio_data = 0;
 326         chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
 327         chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
 328         chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
 329         chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
 330         chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
 331
 332         for (offset = 0; offset < PL061_GPIO_NR; offset++) {
 333                 if (chip->csave_regs.gpio_dir & (BIT(offset)))
 334                         chip->csave_regs.gpio_data |=
 335                                 pl061_get_value(&chip->gc, offset) << offset;
 336         }
 337
 338         return 0;
 339 }
 340
 341 static int pl061_resume(struct device *dev)
 342 {
 343         struct pl061_gpio *chip = dev_get_drvdata(dev);
 344         int offset;
 345
 346         for (offset = 0; offset < PL061_GPIO_NR; offset++) {
 347                 if (chip->csave_regs.gpio_dir & (BIT(offset)))
 348                         pl061_direction_output(&chip->gc, offset,
 349                                         chip->csave_regs.gpio_data &
 350                                         (BIT(offset)));
 351                 else
 352                         pl061_direction_input(&chip->gc, offset);
 353         }
 354
 355         writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
 356         writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
 357         writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
 358         writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
 359
 360         return 0;
 361 }
 362
 363 static const struct dev_pm_ops pl061_dev_pm_ops = {
 364         .suspend = pl061_suspend,
 365         .resume = pl061_resume,
 366         .freeze = pl061_suspend,
 367         .restore = pl061_resume,
 368 };
 369 #endif
 370
 371 static struct amba_id pl061_ids[] = {
 372         {
 373                 .id     = 0x00041061,
 374                 .mask   = 0x000fffff,
 375         },
 376         { 0, 0 },
 377 };
 378
 379 MODULE_DEVICE_TABLE(amba, pl061_ids);
 380
 381 static struct amba_driver pl061_gpio_driver = {
 382         .drv = {
 383                 .name   = "pl061_gpio",
 384 #ifdef CONFIG_PM
 385                 .pm     = &pl061_dev_pm_ops,
 386 #endif
 387         },
 388         .id_table       = pl061_ids,
 389         .probe          = pl061_probe,
 390 };
 391
 392 static int __init pl061_gpio_init(void)
 393 {
 394         return amba_driver_register(&pl061_gpio_driver);
 395 }
 396 module_init(pl061_gpio_init);
 397
 398 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
 399 MODULE_DESCRIPTION("PL061 GPIO driver");
 400 MODULE_LICENSE("GPL");