drivers/gpio/gpio-pxa.c

   1 /*
   2  *  linux/arch/arm/plat-pxa/gpio.c
   3  *
   4  *  Generic PXA GPIO handling
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/gpio-pxa.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/irqdomain.h>
  23 #include <linux/irqchip/chained_irq.h>
  24 #include <linux/io.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/syscore_ops.h>
  30 #include <linux/slab.h>
  31
  32 /*
  33  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
  34  * one set of registers. The register offsets are organized below:
  35  *
  36  *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
  37  * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
  38  * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
  39  * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
  40  *
  41  * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
  42  * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
  43  * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
  44  *
  45  * BANK 6 - 0x0200  0x020C  0x0218  0x0224  0x0230  0x023C  0x0248
  46  *
  47  * NOTE:
  48  *   BANK 3 is only available on PXA27x and later processors.
  49  *   BANK 4 and 5 are only available on PXA935, PXA1928
  50  *   BANK 6 is only available on PXA1928
  51  */
  52
  53 #define GPLR_OFFSET     0x00
  54 #define GPDR_OFFSET     0x0C
  55 #define GPSR_OFFSET     0x18
  56 #define GPCR_OFFSET     0x24
  57 #define GRER_OFFSET     0x30
  58 #define GFER_OFFSET     0x3C
  59 #define GEDR_OFFSET     0x48
  60 #define GAFR_OFFSET     0x54
  61 #define ED_MASK_OFFSET  0x9C    /* GPIO edge detection for AP side */
  62
  63 #define BANK_OFF(n)     (((n) / 3) << 8) + (((n) % 3) << 2)
  64
  65 int pxa_last_gpio;
  66 static int irq_base;
  67
  68 struct pxa_gpio_bank {
  69         void __iomem    *regbase;
  70         unsigned long   irq_mask;
  71         unsigned long   irq_edge_rise;
  72         unsigned long   irq_edge_fall;
  73
  74 #ifdef CONFIG_PM
  75         unsigned long   saved_gplr;
  76         unsigned long   saved_gpdr;
  77         unsigned long   saved_grer;
  78         unsigned long   saved_gfer;
  79 #endif
  80 };
  81
  82 struct pxa_gpio_chip {
  83         struct device *dev;
  84         struct gpio_chip chip;
  85         struct pxa_gpio_bank *banks;
  86         struct irq_domain *irqdomain;
  87
  88         int irq0;
  89         int irq1;
  90         int (*set_wake)(unsigned int gpio, unsigned int on);
  91 };
  92
  93 enum pxa_gpio_type {
  94         PXA25X_GPIO = 0,
  95         PXA26X_GPIO,
  96         PXA27X_GPIO,
  97         PXA3XX_GPIO,
  98         PXA93X_GPIO,
  99         MMP_GPIO = 0x10,
 100         MMP2_GPIO,
 101         PXA1928_GPIO,
 102 };
 103
 104 struct pxa_gpio_id {
 105         enum pxa_gpio_type      type;
 106         int                     gpio_nums;
 107 };
 108
 109 static DEFINE_SPINLOCK(gpio_lock);
 110 static struct pxa_gpio_chip *pxa_gpio_chip;
 111 static enum pxa_gpio_type gpio_type;
 112
 113 static struct pxa_gpio_id pxa25x_id = {
 114         .type           = PXA25X_GPIO,
 115         .gpio_nums      = 85,
 116 };
 117
 118 static struct pxa_gpio_id pxa26x_id = {
 119         .type           = PXA26X_GPIO,
 120         .gpio_nums      = 90,
 121 };
 122
 123 static struct pxa_gpio_id pxa27x_id = {
 124         .type           = PXA27X_GPIO,
 125         .gpio_nums      = 121,
 126 };
 127
 128 static struct pxa_gpio_id pxa3xx_id = {
 129         .type           = PXA3XX_GPIO,
 130         .gpio_nums      = 128,
 131 };
 132
 133 static struct pxa_gpio_id pxa93x_id = {
 134         .type           = PXA93X_GPIO,
 135         .gpio_nums      = 192,
 136 };
 137
 138 static struct pxa_gpio_id mmp_id = {
 139         .type           = MMP_GPIO,
 140         .gpio_nums      = 128,
 141 };
 142
 143 static struct pxa_gpio_id mmp2_id = {
 144         .type           = MMP2_GPIO,
 145         .gpio_nums      = 192,
 146 };
 147
 148 static struct pxa_gpio_id pxa1928_id = {
 149         .type           = PXA1928_GPIO,
 150         .gpio_nums      = 224,
 151 };
 152
 153 #define for_each_gpio_bank(i, b, pc)                                    \
 154         for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
 155
 156 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
 157 {
 158         struct pxa_gpio_chip *pxa_chip =
 159                 container_of(c, struct pxa_gpio_chip, chip);
 160
 161         return pxa_chip;
 162 }
 163 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
 164 {
 165         struct pxa_gpio_bank *bank = chip_to_pxachip(c)->banks + (gpio / 32);
 166
 167         return bank->regbase;
 168 }
 169
 170 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
 171                                                     unsigned gpio)
 172 {
 173         return chip_to_pxachip(c)->banks + gpio / 32;
 174 }
 175
 176 static inline int gpio_is_pxa_type(int type)
 177 {
 178         return (type & MMP_GPIO) == 0;
 179 }
 180
 181 static inline int gpio_is_mmp_type(int type)
 182 {
 183         return (type & MMP_GPIO) != 0;
 184 }
 185
 186 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
 187  * as well as their Alternate Function value being '1' for GPIO in GAFRx.
 188  */
 189 static inline int __gpio_is_inverted(int gpio)
 190 {
 191         if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
 192                 return 1;
 193         return 0;
 194 }
 195
 196 /*
 197  * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
 198  * function of a GPIO, and GPDRx cannot be altered once configured. It
 199  * is attributed as "occupied" here (I know this terminology isn't
 200  * accurate, you are welcome to propose a better one :-)
 201  */
 202 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
 203 {
 204         void __iomem *base;
 205         unsigned long gafr = 0, gpdr = 0;
 206         int ret, af = 0, dir = 0;
 207
 208         base = gpio_bank_base(&pchip->chip, gpio);
 209         gpdr = readl_relaxed(base + GPDR_OFFSET);
 210
 211         switch (gpio_type) {
 212         case PXA25X_GPIO:
 213         case PXA26X_GPIO:
 214         case PXA27X_GPIO:
 215                 gafr = readl_relaxed(base + GAFR_OFFSET);
 216                 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
 217                 dir = gpdr & GPIO_bit(gpio);
 218
 219                 if (__gpio_is_inverted(gpio))
 220                         ret = (af != 1) || (dir == 0);
 221                 else
 222                         ret = (af != 0) || (dir != 0);
 223                 break;
 224         default:
 225                 ret = gpdr & GPIO_bit(gpio);
 226                 break;
 227         }
 228         return ret;
 229 }
 230
 231 int pxa_irq_to_gpio(int irq)
 232 {
 233         struct pxa_gpio_chip *pchip = pxa_gpio_chip;
 234         int irq_gpio0;
 235
 236         irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
 237         if (irq_gpio0 > 0)
 238                 return irq - irq_gpio0;
 239
 240         return irq_gpio0;
 241 }
 242
 243 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 244 {
 245         struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
 246
 247         return irq_find_mapping(pchip->irqdomain, offset);
 248 }
 249
 250 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 251 {
 252         void __iomem *base = gpio_bank_base(chip, offset);
 253         uint32_t value, mask = GPIO_bit(offset);
 254         unsigned long flags;
 255         int ret;
 256
 257         ret = pinctrl_gpio_direction_input(chip->base + offset);
 258         if (!ret)
 259                 return 0;
 260
 261         spin_lock_irqsave(&gpio_lock, flags);
 262
 263         value = readl_relaxed(base + GPDR_OFFSET);
 264         if (__gpio_is_inverted(chip->base + offset))
 265                 value |= mask;
 266         else
 267                 value &= ~mask;
 268         writel_relaxed(value, base + GPDR_OFFSET);
 269
 270         spin_unlock_irqrestore(&gpio_lock, flags);
 271         return 0;
 272 }
 273
 274 static int pxa_gpio_direction_output(struct gpio_chip *chip,
 275                                      unsigned offset, int value)
 276 {
 277         void __iomem *base = gpio_bank_base(chip, offset);
 278         uint32_t tmp, mask = GPIO_bit(offset);
 279         unsigned long flags;
 280         int ret;
 281
 282         writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
 283
 284         ret = pinctrl_gpio_direction_output(chip->base + offset);
 285         if (!ret)
 286                 return 0;
 287
 288         spin_lock_irqsave(&gpio_lock, flags);
 289
 290         tmp = readl_relaxed(base + GPDR_OFFSET);
 291         if (__gpio_is_inverted(chip->base + offset))
 292                 tmp &= ~mask;
 293         else
 294                 tmp |= mask;
 295         writel_relaxed(tmp, base + GPDR_OFFSET);
 296
 297         spin_unlock_irqrestore(&gpio_lock, flags);
 298         return 0;
 299 }
 300
 301 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
 302 {
 303         void __iomem *base = gpio_bank_base(chip, offset);
 304         u32 gplr = readl_relaxed(base + GPLR_OFFSET);
 305
 306         return !!(gplr & GPIO_bit(offset));
 307 }
 308
 309 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 310 {
 311         void __iomem *base = gpio_bank_base(chip, offset);
 312
 313         writel_relaxed(GPIO_bit(offset),
 314                        base + (value ? GPSR_OFFSET : GPCR_OFFSET));
 315 }
 316
 317 #ifdef CONFIG_OF_GPIO
 318 static int pxa_gpio_of_xlate(struct gpio_chip *gc,
 319                              const struct of_phandle_args *gpiospec,
 320                              u32 *flags)
 321 {
 322         if (gpiospec->args[0] > pxa_last_gpio)
 323                 return -EINVAL;
 324
 325         if (flags)
 326                 *flags = gpiospec->args[1];
 327
 328         return gpiospec->args[0];
 329 }
 330 #endif
 331
 332 static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset)
 333 {
 334         return pinctrl_request_gpio(chip->base + offset);
 335 }
 336
 337 static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset)
 338 {
 339         pinctrl_free_gpio(chip->base + offset);
 340 }
 341
 342 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
 343                               struct device_node *np, void __iomem *regbase)
 344 {
 345         int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
 346         struct pxa_gpio_bank *bank;
 347
 348         pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
 349                                     GFP_KERNEL);
 350         if (!pchip->banks)
 351                 return -ENOMEM;
 352
 353         pchip->chip.label = "gpio-pxa";
 354         pchip->chip.direction_input  = pxa_gpio_direction_input;
 355         pchip->chip.direction_output = pxa_gpio_direction_output;
 356         pchip->chip.get = pxa_gpio_get;
 357         pchip->chip.set = pxa_gpio_set;
 358         pchip->chip.to_irq = pxa_gpio_to_irq;
 359         pchip->chip.ngpio = ngpio;
 360         pchip->chip.request = pxa_gpio_request;
 361         pchip->chip.free = pxa_gpio_free;
 362 #ifdef CONFIG_OF_GPIO
 363         pchip->chip.of_node = np;
 364         pchip->chip.of_xlate = pxa_gpio_of_xlate;
 365         pchip->chip.of_gpio_n_cells = 2;
 366 #endif
 367
 368         for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
 369                 bank = pchip->banks + i;
 370                 bank->regbase = regbase + BANK_OFF(i);
 371         }
 372
 373         return gpiochip_add(&pchip->chip);
 374 }
 375
 376 /* Update only those GRERx and GFERx edge detection register bits if those
 377  * bits are set in c->irq_mask
 378  */
 379 static inline void update_edge_detect(struct pxa_gpio_bank *c)
 380 {
 381         uint32_t grer, gfer;
 382
 383         grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
 384         gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
 385         grer |= c->irq_edge_rise & c->irq_mask;
 386         gfer |= c->irq_edge_fall & c->irq_mask;
 387         writel_relaxed(grer, c->regbase + GRER_OFFSET);
 388         writel_relaxed(gfer, c->regbase + GFER_OFFSET);
 389 }
 390
 391 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
 392 {
 393         struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
 394         unsigned int gpio = irqd_to_hwirq(d);
 395         struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
 396         unsigned long gpdr, mask = GPIO_bit(gpio);
 397
 398         if (type == IRQ_TYPE_PROBE) {
 399                 /* Don't mess with enabled GPIOs using preconfigured edges or
 400                  * GPIOs set to alternate function or to output during probe
 401                  */
 402                 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
 403                         return 0;
 404
 405                 if (__gpio_is_occupied(pchip, gpio))
 406                         return 0;
 407
 408                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 409         }
 410
 411         gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
 412
 413         if (__gpio_is_inverted(gpio))
 414                 writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
 415         else
 416                 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
 417
 418         if (type & IRQ_TYPE_EDGE_RISING)
 419                 c->irq_edge_rise |= mask;
 420         else
 421                 c->irq_edge_rise &= ~mask;
 422
 423         if (type & IRQ_TYPE_EDGE_FALLING)
 424                 c->irq_edge_fall |= mask;
 425         else
 426                 c->irq_edge_fall &= ~mask;
 427
 428         update_edge_detect(c);
 429
 430         pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
 431                 ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
 432                 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
 433         return 0;
 434 }
 435
 436 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
 437 {
 438         int loop, gpio, n, handled = 0;
 439         unsigned long gedr;
 440         struct pxa_gpio_chip *pchip = d;
 441         struct pxa_gpio_bank *c;
 442
 443         do {
 444                 loop = 0;
 445                 for_each_gpio_bank(gpio, c, pchip) {
 446                         gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
 447                         gedr = gedr & c->irq_mask;
 448                         writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
 449
 450                         for_each_set_bit(n, &gedr, BITS_PER_LONG) {
 451                                 loop = 1;
 452
 453                                 generic_handle_irq(gpio_to_irq(gpio + n));
 454                         }
 455                 }
 456                 handled += loop;
 457         } while (loop);
 458
 459         return handled ? IRQ_HANDLED : IRQ_NONE;
 460 }
 461
 462 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
 463 {
 464         struct pxa_gpio_chip *pchip = d;
 465
 466         if (in_irq == pchip->irq0) {
 467                 generic_handle_irq(gpio_to_irq(0));
 468         } else if (in_irq == pchip->irq1) {
 469                 generic_handle_irq(gpio_to_irq(1));
 470         } else {
 471                 pr_err("%s() unknown irq %d\n", __func__, in_irq);
 472                 return IRQ_NONE;
 473         }
 474         return IRQ_HANDLED;
 475 }
 476
 477 static void pxa_ack_muxed_gpio(struct irq_data *d)
 478 {
 479         struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
 480         unsigned int gpio = irqd_to_hwirq(d);
 481         void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
 482
 483         writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
 484 }
 485
 486 static void pxa_mask_muxed_gpio(struct irq_data *d)
 487 {
 488         struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
 489         unsigned int gpio = irqd_to_hwirq(d);
 490         struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
 491         void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
 492         uint32_t grer, gfer;
 493
 494         b->irq_mask &= ~GPIO_bit(gpio);
 495
 496         grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
 497         gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
 498         writel_relaxed(grer, base + GRER_OFFSET);
 499         writel_relaxed(gfer, base + GFER_OFFSET);
 500 }
 501
 502 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
 503 {
 504         struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
 505         unsigned int gpio = irqd_to_hwirq(d);
 506
 507         if (pchip->set_wake)
 508                 return pchip->set_wake(gpio, on);
 509         else
 510                 return 0;
 511 }
 512
 513 static void pxa_unmask_muxed_gpio(struct irq_data *d)
 514 {
 515         struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
 516         unsigned int gpio = irqd_to_hwirq(d);
 517         struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
 518
 519         c->irq_mask |= GPIO_bit(gpio);
 520         update_edge_detect(c);
 521 }
 522
 523 static struct irq_chip pxa_muxed_gpio_chip = {
 524         .name           = "GPIO",
 525         .irq_ack        = pxa_ack_muxed_gpio,
 526         .irq_mask       = pxa_mask_muxed_gpio,
 527         .irq_unmask     = pxa_unmask_muxed_gpio,
 528         .irq_set_type   = pxa_gpio_irq_type,
 529         .irq_set_wake   = pxa_gpio_set_wake,
 530 };
 531
 532 static int pxa_gpio_nums(struct platform_device *pdev)
 533 {
 534         const struct platform_device_id *id = platform_get_device_id(pdev);
 535         struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
 536         int count = 0;
 537
 538         switch (pxa_id->type) {
 539         case PXA25X_GPIO:
 540         case PXA26X_GPIO:
 541         case PXA27X_GPIO:
 542         case PXA3XX_GPIO:
 543         case PXA93X_GPIO:
 544         case MMP_GPIO:
 545         case MMP2_GPIO:
 546         case PXA1928_GPIO:
 547                 gpio_type = pxa_id->type;
 548                 count = pxa_id->gpio_nums - 1;
 549                 break;
 550         default:
 551                 count = -EINVAL;
 552                 break;
 553         }
 554         return count;
 555 }
 556
 557 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
 558                               irq_hw_number_t hw)
 559 {
 560         irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
 561                                  handle_edge_irq);
 562         irq_set_chip_data(irq, d->host_data);
 563         irq_set_noprobe(irq);
 564         return 0;
 565 }
 566
 567 const struct irq_domain_ops pxa_irq_domain_ops = {
 568         .map    = pxa_irq_domain_map,
 569         .xlate  = irq_domain_xlate_twocell,
 570 };
 571
 572 #ifdef CONFIG_OF
 573 static const struct of_device_id pxa_gpio_dt_ids[] = {
 574         { .compatible = "intel,pxa25x-gpio",    .data = &pxa25x_id, },
 575         { .compatible = "intel,pxa26x-gpio",    .data = &pxa26x_id, },
 576         { .compatible = "intel,pxa27x-gpio",    .data = &pxa27x_id, },
 577         { .compatible = "intel,pxa3xx-gpio",    .data = &pxa3xx_id, },
 578         { .compatible = "marvell,pxa93x-gpio",  .data = &pxa93x_id, },
 579         { .compatible = "marvell,mmp-gpio",     .data = &mmp_id, },
 580         { .compatible = "marvell,mmp2-gpio",    .data = &mmp2_id, },
 581         { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
 582         {}
 583 };
 584
 585 static int pxa_gpio_probe_dt(struct platform_device *pdev,
 586                              struct pxa_gpio_chip *pchip)
 587 {
 588         int nr_gpios;
 589         const struct of_device_id *of_id =
 590                                 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
 591         const struct pxa_gpio_id *gpio_id;
 592
 593         if (!of_id || !of_id->data) {
 594                 dev_err(&pdev->dev, "Failed to find gpio controller\n");
 595                 return -EFAULT;
 596         }
 597         gpio_id = of_id->data;
 598         gpio_type = gpio_id->type;
 599
 600         nr_gpios = gpio_id->gpio_nums;
 601         pxa_last_gpio = nr_gpios - 1;
 602
 603         irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
 604         if (irq_base < 0) {
 605                 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
 606                 return irq_base;
 607         }
 608         return irq_base;
 609 }
 610 #else
 611 #define pxa_gpio_probe_dt(pdev, pchip)          (-1)
 612 #endif
 613
 614 static int pxa_gpio_probe(struct platform_device *pdev)
 615 {
 616         struct pxa_gpio_chip *pchip;
 617         struct pxa_gpio_bank *c;
 618         struct resource *res;
 619         struct clk *clk;
 620         struct pxa_gpio_platform_data *info;
 621         void __iomem *gpio_reg_base;
 622         int gpio, ret;
 623         int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
 624
 625         pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
 626         if (!pchip)
 627                 return -ENOMEM;
 628         pchip->dev = &pdev->dev;
 629
 630         info = dev_get_platdata(&pdev->dev);
 631         if (info) {
 632                 irq_base = info->irq_base;
 633                 if (irq_base <= 0)
 634                         return -EINVAL;
 635                 pxa_last_gpio = pxa_gpio_nums(pdev);
 636                 pchip->set_wake = info->gpio_set_wake;
 637         } else {
 638                 irq_base = pxa_gpio_probe_dt(pdev, pchip);
 639                 if (irq_base < 0)
 640                         return -EINVAL;
 641         }
 642
 643         if (!pxa_last_gpio)
 644                 return -EINVAL;
 645
 646         pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
 647                                                  pxa_last_gpio + 1, irq_base,
 648                                                  0, &pxa_irq_domain_ops, pchip);
 649         if (IS_ERR(pchip->irqdomain))
 650                 return PTR_ERR(pchip->irqdomain);
 651
 652         irq0 = platform_get_irq_byname(pdev, "gpio0");
 653         irq1 = platform_get_irq_byname(pdev, "gpio1");
 654         irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
 655         if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
 656                 || (irq_mux <= 0))
 657                 return -EINVAL;
 658
 659         pchip->irq0 = irq0;
 660         pchip->irq1 = irq1;
 661         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 662         gpio_reg_base = devm_ioremap(&pdev->dev, res->start,
 663                                      resource_size(res));
 664         if (!gpio_reg_base)
 665                 return -EINVAL;
 666
 667         if (irq0 > 0)
 668                 gpio_offset = 2;
 669
 670         clk = clk_get(&pdev->dev, NULL);
 671         if (IS_ERR(clk)) {
 672                 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
 673                         PTR_ERR(clk));
 674                 return PTR_ERR(clk);
 675         }
 676         ret = clk_prepare_enable(clk);
 677         if (ret) {
 678                 clk_put(clk);
 679                 return ret;
 680         }
 681
 682         /* Initialize GPIO chips */
 683         ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
 684                                  gpio_reg_base);
 685         if (ret) {
 686                 clk_put(clk);
 687                 return ret;
 688         }
 689
 690         /* clear all GPIO edge detects */
 691         for_each_gpio_bank(gpio, c, pchip) {
 692                 writel_relaxed(0, c->regbase + GFER_OFFSET);
 693                 writel_relaxed(0, c->regbase + GRER_OFFSET);
 694                 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
 695                 /* unmask GPIO edge detect for AP side */
 696                 if (gpio_is_mmp_type(gpio_type))
 697                         writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
 698         }
 699
 700         if (irq0 > 0) {
 701                 ret = devm_request_irq(&pdev->dev,
 702                                        irq0, pxa_gpio_direct_handler, 0,
 703                                        "gpio-0", pchip);
 704                 if (ret)
 705                         dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
 706                                 ret);
 707         }
 708         if (irq1 > 0) {
 709                 ret = devm_request_irq(&pdev->dev,
 710                                        irq1, pxa_gpio_direct_handler, 0,
 711                                        "gpio-1", pchip);
 712                 if (ret)
 713                         dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
 714                                 ret);
 715         }
 716         ret = devm_request_irq(&pdev->dev,
 717                                irq_mux, pxa_gpio_demux_handler, 0,
 718                                        "gpio-mux", pchip);
 719         if (ret)
 720                 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
 721                                 ret);
 722
 723         pxa_gpio_chip = pchip;
 724
 725         return 0;
 726 }
 727
 728 static const struct platform_device_id gpio_id_table[] = {
 729         { "pxa25x-gpio",        (unsigned long)&pxa25x_id },
 730         { "pxa26x-gpio",        (unsigned long)&pxa26x_id },
 731         { "pxa27x-gpio",        (unsigned long)&pxa27x_id },
 732         { "pxa3xx-gpio",        (unsigned long)&pxa3xx_id },
 733         { "pxa93x-gpio",        (unsigned long)&pxa93x_id },
 734         { "mmp-gpio",           (unsigned long)&mmp_id },
 735         { "mmp2-gpio",          (unsigned long)&mmp2_id },
 736         { "pxa1928-gpio",       (unsigned long)&pxa1928_id },
 737         { },
 738 };
 739
 740 static struct platform_driver pxa_gpio_driver = {
 741         .probe          = pxa_gpio_probe,
 742         .driver         = {
 743                 .name   = "pxa-gpio",
 744                 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
 745         },
 746         .id_table       = gpio_id_table,
 747 };
 748
 749 static int __init pxa_gpio_legacy_init(void)
 750 {
 751         if (of_have_populated_dt())
 752                 return 0;
 753
 754         return platform_driver_register(&pxa_gpio_driver);
 755 }
 756 postcore_initcall(pxa_gpio_legacy_init);
 757
 758 static int __init pxa_gpio_dt_init(void)
 759 {
 760         if (of_have_populated_dt())
 761                 return platform_driver_register(&pxa_gpio_driver);
 762
 763         return 0;
 764 }
 765 device_initcall(pxa_gpio_dt_init);
 766
 767 #ifdef CONFIG_PM
 768 static int pxa_gpio_suspend(void)
 769 {
 770         struct pxa_gpio_chip *pchip = pxa_gpio_chip;
 771         struct pxa_gpio_bank *c;
 772         int gpio;
 773
 774         for_each_gpio_bank(gpio, c, pchip) {
 775                 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
 776                 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
 777                 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
 778                 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
 779
 780                 /* Clear GPIO transition detect bits */
 781                 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
 782         }
 783         return 0;
 784 }
 785
 786 static void pxa_gpio_resume(void)
 787 {
 788         struct pxa_gpio_chip *pchip = pxa_gpio_chip;
 789         struct pxa_gpio_bank *c;
 790         int gpio;
 791
 792         for_each_gpio_bank(gpio, c, pchip) {
 793                 /* restore level with set/clear */
 794                 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
 795                 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
 796
 797                 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
 798                 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
 799                 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
 800         }
 801 }
 802 #else
 803 #define pxa_gpio_suspend        NULL
 804 #define pxa_gpio_resume         NULL
 805 #endif
 806
 807 struct syscore_ops pxa_gpio_syscore_ops = {
 808         .suspend        = pxa_gpio_suspend,
 809         .resume         = pxa_gpio_resume,
 810 };
 811
 812 static int __init pxa_gpio_sysinit(void)
 813 {
 814         register_syscore_ops(&pxa_gpio_syscore_ops);
 815         return 0;
 816 }
 817 postcore_initcall(pxa_gpio_sysinit);