drivers/gpio/gpio-rcar.c

   1 /*
   2  * Renesas R-Car GPIO Support
   3  *
   4  *  Copyright (C) 2014 Renesas Electronics Corporation
   5  *  Copyright (C) 2013 Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/err.h>
  18 #include <linux/gpio.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/ioport.h>
  23 #include <linux/irq.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/platform_data/gpio-rcar.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/slab.h>
  32
  33 struct gpio_rcar_priv {
  34         void __iomem *base;
  35         spinlock_t lock;
  36         struct gpio_rcar_config config;
  37         struct platform_device *pdev;
  38         struct gpio_chip gpio_chip;
  39         struct irq_chip irq_chip;
  40 };
  41
  42 #define IOINTSEL 0x00
  43 #define INOUTSEL 0x04
  44 #define OUTDT 0x08
  45 #define INDT 0x0c
  46 #define INTDT 0x10
  47 #define INTCLR 0x14
  48 #define INTMSK 0x18
  49 #define MSKCLR 0x1c
  50 #define POSNEG 0x20
  51 #define EDGLEVEL 0x24
  52 #define FILONOFF 0x28
  53 #define BOTHEDGE 0x4c
  54
  55 #define RCAR_MAX_GPIO_PER_BANK          32
  56
  57 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  58 {
  59         return ioread32(p->base + offs);
  60 }
  61
  62 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  63                                    u32 value)
  64 {
  65         iowrite32(value, p->base + offs);
  66 }
  67
  68 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  69                                  int bit, bool value)
  70 {
  71         u32 tmp = gpio_rcar_read(p, offs);
  72
  73         if (value)
  74                 tmp |= BIT(bit);
  75         else
  76                 tmp &= ~BIT(bit);
  77
  78         gpio_rcar_write(p, offs, tmp);
  79 }
  80
  81 static void gpio_rcar_irq_disable(struct irq_data *d)
  82 {
  83         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  84         struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
  85                                                 gpio_chip);
  86
  87         gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
  88 }
  89
  90 static void gpio_rcar_irq_enable(struct irq_data *d)
  91 {
  92         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  93         struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
  94                                                 gpio_chip);
  95
  96         gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
  97 }
  98
  99 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 100                                                   unsigned int hwirq,
 101                                                   bool active_high_rising_edge,
 102                                                   bool level_trigger,
 103                                                   bool both)
 104 {
 105         unsigned long flags;
 106
 107         /* follow steps in the GPIO documentation for
 108          * "Setting Edge-Sensitive Interrupt Input Mode" and
 109          * "Setting Level-Sensitive Interrupt Input Mode"
 110          */
 111
 112         spin_lock_irqsave(&p->lock, flags);
 113
 114         /* Configure postive or negative logic in POSNEG */
 115         gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
 116
 117         /* Configure edge or level trigger in EDGLEVEL */
 118         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 119
 120         /* Select one edge or both edges in BOTHEDGE */
 121         if (p->config.has_both_edge_trigger)
 122                 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
 123
 124         /* Select "Interrupt Input Mode" in IOINTSEL */
 125         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 126
 127         /* Write INTCLR in case of edge trigger */
 128         if (!level_trigger)
 129                 gpio_rcar_write(p, INTCLR, BIT(hwirq));
 130
 131         spin_unlock_irqrestore(&p->lock, flags);
 132 }
 133
 134 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 135 {
 136         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 137         struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
 138                                                 gpio_chip);
 139         unsigned int hwirq = irqd_to_hwirq(d);
 140
 141         dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
 142
 143         switch (type & IRQ_TYPE_SENSE_MASK) {
 144         case IRQ_TYPE_LEVEL_HIGH:
 145                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
 146                                                       false);
 147                 break;
 148         case IRQ_TYPE_LEVEL_LOW:
 149                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
 150                                                       false);
 151                 break;
 152         case IRQ_TYPE_EDGE_RISING:
 153                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 154                                                       false);
 155                 break;
 156         case IRQ_TYPE_EDGE_FALLING:
 157                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
 158                                                       false);
 159                 break;
 160         case IRQ_TYPE_EDGE_BOTH:
 161                 if (!p->config.has_both_edge_trigger)
 162                         return -EINVAL;
 163                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 164                                                       true);
 165                 break;
 166         default:
 167                 return -EINVAL;
 168         }
 169         return 0;
 170 }
 171
 172 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
 173 {
 174         struct gpio_rcar_priv *p = dev_id;
 175         u32 pending;
 176         unsigned int offset, irqs_handled = 0;
 177
 178         while ((pending = gpio_rcar_read(p, INTDT) &
 179                           gpio_rcar_read(p, INTMSK))) {
 180                 offset = __ffs(pending);
 181                 gpio_rcar_write(p, INTCLR, BIT(offset));
 182                 generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
 183                                                     offset));
 184                 irqs_handled++;
 185         }
 186
 187         return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 188 }
 189
 190 static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
 191 {
 192         return container_of(chip, struct gpio_rcar_priv, gpio_chip);
 193 }
 194
 195 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 196                                                        unsigned int gpio,
 197                                                        bool output)
 198 {
 199         struct gpio_rcar_priv *p = gpio_to_priv(chip);
 200         unsigned long flags;
 201
 202         /* follow steps in the GPIO documentation for
 203          * "Setting General Output Mode" and
 204          * "Setting General Input Mode"
 205          */
 206
 207         spin_lock_irqsave(&p->lock, flags);
 208
 209         /* Configure postive logic in POSNEG */
 210         gpio_rcar_modify_bit(p, POSNEG, gpio, false);
 211
 212         /* Select "General Input/Output Mode" in IOINTSEL */
 213         gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
 214
 215         /* Select Input Mode or Output Mode in INOUTSEL */
 216         gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
 217
 218         spin_unlock_irqrestore(&p->lock, flags);
 219 }
 220
 221 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 222 {
 223         return pinctrl_request_gpio(chip->base + offset);
 224 }
 225
 226 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 227 {
 228         pinctrl_free_gpio(chip->base + offset);
 229
 230         /* Set the GPIO as an input to ensure that the next GPIO request won't
 231          * drive the GPIO pin as an output.
 232          */
 233         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 234 }
 235
 236 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 237 {
 238         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 239         return 0;
 240 }
 241
 242 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
 243 {
 244         u32 bit = BIT(offset);
 245
 246         /* testing on r8a7790 shows that INDT does not show correct pin state
 247          * when configured as output, so use OUTDT in case of output pins */
 248         if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
 249                 return !!(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
 250         else
 251                 return !!(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
 252 }
 253
 254 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
 255 {
 256         struct gpio_rcar_priv *p = gpio_to_priv(chip);
 257         unsigned long flags;
 258
 259         spin_lock_irqsave(&p->lock, flags);
 260         gpio_rcar_modify_bit(p, OUTDT, offset, value);
 261         spin_unlock_irqrestore(&p->lock, flags);
 262 }
 263
 264 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 265                                       int value)
 266 {
 267         /* write GPIO value to output before selecting output mode of pin */
 268         gpio_rcar_set(chip, offset, value);
 269         gpio_rcar_config_general_input_output_mode(chip, offset, true);
 270         return 0;
 271 }
 272
 273 struct gpio_rcar_info {
 274         bool has_both_edge_trigger;
 275 };
 276
 277 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
 278         .has_both_edge_trigger = false,
 279 };
 280
 281 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
 282         .has_both_edge_trigger = true,
 283 };
 284
 285 static const struct of_device_id gpio_rcar_of_table[] = {
 286         {
 287                 .compatible = "renesas,gpio-r8a7790",
 288                 .data = &gpio_rcar_info_gen2,
 289         }, {
 290                 .compatible = "renesas,gpio-r8a7791",
 291                 .data = &gpio_rcar_info_gen2,
 292         }, {
 293                 .compatible = "renesas,gpio-r8a7793",
 294                 .data = &gpio_rcar_info_gen2,
 295         }, {
 296                 .compatible = "renesas,gpio-r8a7794",
 297                 .data = &gpio_rcar_info_gen2,
 298         }, {
 299                 .compatible = "renesas,gpio-rcar",
 300                 .data = &gpio_rcar_info_gen1,
 301         }, {
 302                 /* Terminator */
 303         },
 304 };
 305
 306 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
 307
 308 static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
 309 {
 310         struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
 311         struct device_node *np = p->pdev->dev.of_node;
 312         struct of_phandle_args args;
 313         int ret;
 314
 315         if (pdata) {
 316                 p->config = *pdata;
 317         } else if (IS_ENABLED(CONFIG_OF) && np) {
 318                 const struct of_device_id *match;
 319                 const struct gpio_rcar_info *info;
 320
 321                 match = of_match_node(gpio_rcar_of_table, np);
 322                 if (!match)
 323                         return -EINVAL;
 324
 325                 info = match->data;
 326
 327                 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
 328                                                        &args);
 329                 p->config.number_of_pins = ret == 0 ? args.args[2]
 330                                          : RCAR_MAX_GPIO_PER_BANK;
 331                 p->config.gpio_base = -1;
 332                 p->config.has_both_edge_trigger = info->has_both_edge_trigger;
 333         }
 334
 335         if (p->config.number_of_pins == 0 ||
 336             p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
 337                 dev_warn(&p->pdev->dev,
 338                          "Invalid number of gpio lines %u, using %u\n",
 339                          p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
 340                 p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
 341         }
 342
 343         return 0;
 344 }
 345
 346 static int gpio_rcar_probe(struct platform_device *pdev)
 347 {
 348         struct gpio_rcar_priv *p;
 349         struct resource *io, *irq;
 350         struct gpio_chip *gpio_chip;
 351         struct irq_chip *irq_chip;
 352         struct device *dev = &pdev->dev;
 353         const char *name = dev_name(dev);
 354         int ret;
 355
 356         p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
 357         if (!p)
 358                 return -ENOMEM;
 359
 360         p->pdev = pdev;
 361         spin_lock_init(&p->lock);
 362
 363         /* Get device configuration from DT node or platform data. */
 364         ret = gpio_rcar_parse_pdata(p);
 365         if (ret < 0)
 366                 return ret;
 367
 368         platform_set_drvdata(pdev, p);
 369
 370         pm_runtime_enable(dev);
 371         pm_runtime_get_sync(dev);
 372
 373         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 374         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 375
 376         if (!io || !irq) {
 377                 dev_err(dev, "missing IRQ or IOMEM\n");
 378                 ret = -EINVAL;
 379                 goto err0;
 380         }
 381
 382         p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
 383         if (!p->base) {
 384                 dev_err(dev, "failed to remap I/O memory\n");
 385                 ret = -ENXIO;
 386                 goto err0;
 387         }
 388
 389         gpio_chip = &p->gpio_chip;
 390         gpio_chip->request = gpio_rcar_request;
 391         gpio_chip->free = gpio_rcar_free;
 392         gpio_chip->direction_input = gpio_rcar_direction_input;
 393         gpio_chip->get = gpio_rcar_get;
 394         gpio_chip->direction_output = gpio_rcar_direction_output;
 395         gpio_chip->set = gpio_rcar_set;
 396         gpio_chip->label = name;
 397         gpio_chip->dev = dev;
 398         gpio_chip->owner = THIS_MODULE;
 399         gpio_chip->base = p->config.gpio_base;
 400         gpio_chip->ngpio = p->config.number_of_pins;
 401
 402         irq_chip = &p->irq_chip;
 403         irq_chip->name = name;
 404         irq_chip->irq_mask = gpio_rcar_irq_disable;
 405         irq_chip->irq_unmask = gpio_rcar_irq_enable;
 406         irq_chip->irq_set_type = gpio_rcar_irq_set_type;
 407         irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED
 408                          | IRQCHIP_MASK_ON_SUSPEND;
 409
 410         ret = gpiochip_add(gpio_chip);
 411         if (ret) {
 412                 dev_err(dev, "failed to add GPIO controller\n");
 413                 goto err0;
 414         }
 415
 416         ret = gpiochip_irqchip_add(&p->gpio_chip, irq_chip, p->config.irq_base,
 417                                    handle_level_irq, IRQ_TYPE_NONE);
 418         if (ret) {
 419                 dev_err(dev, "cannot add irqchip\n");
 420                 goto err1;
 421         }
 422
 423         if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
 424                              IRQF_SHARED, name, p)) {
 425                 dev_err(dev, "failed to request IRQ\n");
 426                 ret = -ENOENT;
 427                 goto err1;
 428         }
 429
 430         dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);
 431
 432         /* warn in case of mismatch if irq base is specified */
 433         if (p->config.irq_base) {
 434                 ret = irq_find_mapping(p->gpio_chip.irqdomain, 0);
 435                 if (p->config.irq_base != ret)
 436                         dev_warn(dev, "irq base mismatch (%u/%u)\n",
 437                                  p->config.irq_base, ret);
 438         }
 439
 440         if (p->config.pctl_name) {
 441                 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
 442                                              gpio_chip->base, gpio_chip->ngpio);
 443                 if (ret < 0)
 444                         dev_warn(dev, "failed to add pin range\n");
 445         }
 446
 447         return 0;
 448
 449 err1:
 450         gpiochip_remove(&p->gpio_chip);
 451 err0:
 452         pm_runtime_put(dev);
 453         pm_runtime_disable(dev);
 454         return ret;
 455 }
 456
 457 static int gpio_rcar_remove(struct platform_device *pdev)
 458 {
 459         struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
 460
 461         gpiochip_remove(&p->gpio_chip);
 462
 463         pm_runtime_put(&pdev->dev);
 464         pm_runtime_disable(&pdev->dev);
 465         return 0;
 466 }
 467
 468 static struct platform_driver gpio_rcar_device_driver = {
 469         .probe          = gpio_rcar_probe,
 470         .remove         = gpio_rcar_remove,
 471         .driver         = {
 472                 .name   = "gpio_rcar",
 473                 .of_match_table = of_match_ptr(gpio_rcar_of_table),
 474         }
 475 };
 476
 477 module_platform_driver(gpio_rcar_device_driver);
 478
 479 MODULE_AUTHOR("Magnus Damm");
 480 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
 481 MODULE_LICENSE("GPL v2");