drivers/gpio/gpio-rcar.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas R-Car GPIO Support
   4  *
   5  *  Copyright (C) 2014 Renesas Electronics Corporation
   6  *  Copyright (C) 2013 Magnus Damm
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/gpio/driver.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/ioport.h>
  15 #include <linux/irq.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pinctrl/consumer.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/slab.h>
  24
  25 struct gpio_rcar_bank_info {
  26         u32 iointsel;
  27         u32 inoutsel;
  28         u32 outdt;
  29         u32 posneg;
  30         u32 edglevel;
  31         u32 bothedge;
  32         u32 intmsk;
  33 };
  34
  35 struct gpio_rcar_priv {
  36         void __iomem *base;
  37         spinlock_t lock;
  38         struct device *dev;
  39         struct gpio_chip gpio_chip;
  40         struct irq_chip irq_chip;
  41         unsigned int irq_parent;
  42         atomic_t wakeup_path;
  43         bool has_both_edge_trigger;
  44         struct gpio_rcar_bank_info bank_info;
  45 };
  46
  47 #define IOINTSEL 0x00   /* General IO/Interrupt Switching Register */
  48 #define INOUTSEL 0x04   /* General Input/Output Switching Register */
  49 #define OUTDT 0x08      /* General Output Register */
  50 #define INDT 0x0c       /* General Input Register */
  51 #define INTDT 0x10      /* Interrupt Display Register */
  52 #define INTCLR 0x14     /* Interrupt Clear Register */
  53 #define INTMSK 0x18     /* Interrupt Mask Register */
  54 #define MSKCLR 0x1c     /* Interrupt Mask Clear Register */
  55 #define POSNEG 0x20     /* Positive/Negative Logic Select Register */
  56 #define EDGLEVEL 0x24   /* Edge/level Select Register */
  57 #define FILONOFF 0x28   /* Chattering Prevention On/Off Register */
  58 #define BOTHEDGE 0x4c   /* One Edge/Both Edge Select Register */
  59
  60 #define RCAR_MAX_GPIO_PER_BANK          32
  61
  62 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  63 {
  64         return ioread32(p->base + offs);
  65 }
  66
  67 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  68                                    u32 value)
  69 {
  70         iowrite32(value, p->base + offs);
  71 }
  72
  73 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  74                                  int bit, bool value)
  75 {
  76         u32 tmp = gpio_rcar_read(p, offs);
  77
  78         if (value)
  79                 tmp |= BIT(bit);
  80         else
  81                 tmp &= ~BIT(bit);
  82
  83         gpio_rcar_write(p, offs, tmp);
  84 }
  85
  86 static void gpio_rcar_irq_disable(struct irq_data *d)
  87 {
  88         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  89         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
  90
  91         gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
  92 }
  93
  94 static void gpio_rcar_irq_enable(struct irq_data *d)
  95 {
  96         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  97         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
  98
  99         gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
 100 }
 101
 102 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 103                                                   unsigned int hwirq,
 104                                                   bool active_high_rising_edge,
 105                                                   bool level_trigger,
 106                                                   bool both)
 107 {
 108         unsigned long flags;
 109
 110         /* follow steps in the GPIO documentation for
 111          * "Setting Edge-Sensitive Interrupt Input Mode" and
 112          * "Setting Level-Sensitive Interrupt Input Mode"
 113          */
 114
 115         spin_lock_irqsave(&p->lock, flags);
 116
 117         /* Configure postive or negative logic in POSNEG */
 118         gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
 119
 120         /* Configure edge or level trigger in EDGLEVEL */
 121         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 122
 123         /* Select one edge or both edges in BOTHEDGE */
 124         if (p->has_both_edge_trigger)
 125                 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
 126
 127         /* Select "Interrupt Input Mode" in IOINTSEL */
 128         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 129
 130         /* Write INTCLR in case of edge trigger */
 131         if (!level_trigger)
 132                 gpio_rcar_write(p, INTCLR, BIT(hwirq));
 133
 134         spin_unlock_irqrestore(&p->lock, flags);
 135 }
 136
 137 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 138 {
 139         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 140         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 141         unsigned int hwirq = irqd_to_hwirq(d);
 142
 143         dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
 144
 145         switch (type & IRQ_TYPE_SENSE_MASK) {
 146         case IRQ_TYPE_LEVEL_HIGH:
 147                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
 148                                                       false);
 149                 break;
 150         case IRQ_TYPE_LEVEL_LOW:
 151                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
 152                                                       false);
 153                 break;
 154         case IRQ_TYPE_EDGE_RISING:
 155                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 156                                                       false);
 157                 break;
 158         case IRQ_TYPE_EDGE_FALLING:
 159                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
 160                                                       false);
 161                 break;
 162         case IRQ_TYPE_EDGE_BOTH:
 163                 if (!p->has_both_edge_trigger)
 164                         return -EINVAL;
 165                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 166                                                       true);
 167                 break;
 168         default:
 169                 return -EINVAL;
 170         }
 171         return 0;
 172 }
 173
 174 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
 175 {
 176         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 177         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 178         int error;
 179
 180         if (p->irq_parent) {
 181                 error = irq_set_irq_wake(p->irq_parent, on);
 182                 if (error) {
 183                         dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
 184                                 p->irq_parent);
 185                         p->irq_parent = 0;
 186                 }
 187         }
 188
 189         if (on)
 190                 atomic_inc(&p->wakeup_path);
 191         else
 192                 atomic_dec(&p->wakeup_path);
 193
 194         return 0;
 195 }
 196
 197 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
 198 {
 199         struct gpio_rcar_priv *p = dev_id;
 200         u32 pending;
 201         unsigned int offset, irqs_handled = 0;
 202
 203         while ((pending = gpio_rcar_read(p, INTDT) &
 204                           gpio_rcar_read(p, INTMSK))) {
 205                 offset = __ffs(pending);
 206                 gpio_rcar_write(p, INTCLR, BIT(offset));
 207                 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
 208                                                     offset));
 209                 irqs_handled++;
 210         }
 211
 212         return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 213 }
 214
 215 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 216                                                        unsigned int gpio,
 217                                                        bool output)
 218 {
 219         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 220         unsigned long flags;
 221
 222         /* follow steps in the GPIO documentation for
 223          * "Setting General Output Mode" and
 224          * "Setting General Input Mode"
 225          */
 226
 227         spin_lock_irqsave(&p->lock, flags);
 228
 229         /* Configure postive logic in POSNEG */
 230         gpio_rcar_modify_bit(p, POSNEG, gpio, false);
 231
 232         /* Select "General Input/Output Mode" in IOINTSEL */
 233         gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
 234
 235         /* Select Input Mode or Output Mode in INOUTSEL */
 236         gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
 237
 238         spin_unlock_irqrestore(&p->lock, flags);
 239 }
 240
 241 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 242 {
 243         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 244         int error;
 245
 246         error = pm_runtime_get_sync(p->dev);
 247         if (error < 0)
 248                 return error;
 249
 250         error = pinctrl_gpio_request(chip->base + offset);
 251         if (error)
 252                 pm_runtime_put(p->dev);
 253
 254         return error;
 255 }
 256
 257 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 258 {
 259         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 260
 261         pinctrl_gpio_free(chip->base + offset);
 262
 263         /*
 264          * Set the GPIO as an input to ensure that the next GPIO request won't
 265          * drive the GPIO pin as an output.
 266          */
 267         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 268
 269         pm_runtime_put(p->dev);
 270 }
 271
 272 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
 273 {
 274         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 275
 276         return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
 277 }
 278
 279 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 280 {
 281         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 282         return 0;
 283 }
 284
 285 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
 286 {
 287         u32 bit = BIT(offset);
 288
 289         /* testing on r8a7790 shows that INDT does not show correct pin state
 290          * when configured as output, so use OUTDT in case of output pins */
 291         if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
 292                 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
 293         else
 294                 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
 295 }
 296
 297 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
 298 {
 299         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&p->lock, flags);
 303         gpio_rcar_modify_bit(p, OUTDT, offset, value);
 304         spin_unlock_irqrestore(&p->lock, flags);
 305 }
 306
 307 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
 308                                    unsigned long *bits)
 309 {
 310         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 311         unsigned long flags;
 312         u32 val, bankmask;
 313
 314         bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
 315         if (chip->valid_mask)
 316                 bankmask &= chip->valid_mask[0];
 317
 318         if (!bankmask)
 319                 return;
 320
 321         spin_lock_irqsave(&p->lock, flags);
 322         val = gpio_rcar_read(p, OUTDT);
 323         val &= ~bankmask;
 324         val |= (bankmask & bits[0]);
 325         gpio_rcar_write(p, OUTDT, val);
 326         spin_unlock_irqrestore(&p->lock, flags);
 327 }
 328
 329 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 330                                       int value)
 331 {
 332         /* write GPIO value to output before selecting output mode of pin */
 333         gpio_rcar_set(chip, offset, value);
 334         gpio_rcar_config_general_input_output_mode(chip, offset, true);
 335         return 0;
 336 }
 337
 338 struct gpio_rcar_info {
 339         bool has_both_edge_trigger;
 340 };
 341
 342 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
 343         .has_both_edge_trigger = false,
 344 };
 345
 346 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
 347         .has_both_edge_trigger = true,
 348 };
 349
 350 static const struct of_device_id gpio_rcar_of_table[] = {
 351         {
 352                 .compatible = "renesas,gpio-r8a7743",
 353                 /* RZ/G1 GPIO is identical to R-Car Gen2. */
 354                 .data = &gpio_rcar_info_gen2,
 355         }, {
 356                 .compatible = "renesas,gpio-r8a7790",
 357                 .data = &gpio_rcar_info_gen2,
 358         }, {
 359                 .compatible = "renesas,gpio-r8a7791",
 360                 .data = &gpio_rcar_info_gen2,
 361         }, {
 362                 .compatible = "renesas,gpio-r8a7792",
 363                 .data = &gpio_rcar_info_gen2,
 364         }, {
 365                 .compatible = "renesas,gpio-r8a7793",
 366                 .data = &gpio_rcar_info_gen2,
 367         }, {
 368                 .compatible = "renesas,gpio-r8a7794",
 369                 .data = &gpio_rcar_info_gen2,
 370         }, {
 371                 .compatible = "renesas,gpio-r8a7795",
 372                 /* Gen3 GPIO is identical to Gen2. */
 373                 .data = &gpio_rcar_info_gen2,
 374         }, {
 375                 .compatible = "renesas,gpio-r8a7796",
 376                 /* Gen3 GPIO is identical to Gen2. */
 377                 .data = &gpio_rcar_info_gen2,
 378         }, {
 379                 .compatible = "renesas,rcar-gen1-gpio",
 380                 .data = &gpio_rcar_info_gen1,
 381         }, {
 382                 .compatible = "renesas,rcar-gen2-gpio",
 383                 .data = &gpio_rcar_info_gen2,
 384         }, {
 385                 .compatible = "renesas,rcar-gen3-gpio",
 386                 /* Gen3 GPIO is identical to Gen2. */
 387                 .data = &gpio_rcar_info_gen2,
 388         }, {
 389                 .compatible = "renesas,gpio-rcar",
 390                 .data = &gpio_rcar_info_gen1,
 391         }, {
 392                 /* Terminator */
 393         },
 394 };
 395
 396 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
 397
 398 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
 399 {
 400         struct device_node *np = p->dev->of_node;
 401         const struct gpio_rcar_info *info;
 402         struct of_phandle_args args;
 403         int ret;
 404
 405         info = of_device_get_match_data(p->dev);
 406
 407         ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
 408         *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
 409         p->has_both_edge_trigger = info->has_both_edge_trigger;
 410
 411         if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
 412                 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
 413                          *npins, RCAR_MAX_GPIO_PER_BANK);
 414                 *npins = RCAR_MAX_GPIO_PER_BANK;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int gpio_rcar_probe(struct platform_device *pdev)
 421 {
 422         struct gpio_rcar_priv *p;
 423         struct resource *io, *irq;
 424         struct gpio_chip *gpio_chip;
 425         struct irq_chip *irq_chip;
 426         struct device *dev = &pdev->dev;
 427         const char *name = dev_name(dev);
 428         unsigned int npins;
 429         int ret;
 430
 431         p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
 432         if (!p)
 433                 return -ENOMEM;
 434
 435         p->dev = dev;
 436         spin_lock_init(&p->lock);
 437
 438         /* Get device configuration from DT node */
 439         ret = gpio_rcar_parse_dt(p, &npins);
 440         if (ret < 0)
 441                 return ret;
 442
 443         platform_set_drvdata(pdev, p);
 444
 445         pm_runtime_enable(dev);
 446
 447         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 448         if (!irq) {
 449                 dev_err(dev, "missing IRQ\n");
 450                 ret = -EINVAL;
 451                 goto err0;
 452         }
 453
 454         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 455         p->base = devm_ioremap_resource(dev, io);
 456         if (IS_ERR(p->base)) {
 457                 ret = PTR_ERR(p->base);
 458                 goto err0;
 459         }
 460
 461         gpio_chip = &p->gpio_chip;
 462         gpio_chip->request = gpio_rcar_request;
 463         gpio_chip->free = gpio_rcar_free;
 464         gpio_chip->get_direction = gpio_rcar_get_direction;
 465         gpio_chip->direction_input = gpio_rcar_direction_input;
 466         gpio_chip->get = gpio_rcar_get;
 467         gpio_chip->direction_output = gpio_rcar_direction_output;
 468         gpio_chip->set = gpio_rcar_set;
 469         gpio_chip->set_multiple = gpio_rcar_set_multiple;
 470         gpio_chip->label = name;
 471         gpio_chip->parent = dev;
 472         gpio_chip->owner = THIS_MODULE;
 473         gpio_chip->base = -1;
 474         gpio_chip->ngpio = npins;
 475
 476         irq_chip = &p->irq_chip;
 477         irq_chip->name = name;
 478         irq_chip->parent_device = dev;
 479         irq_chip->irq_mask = gpio_rcar_irq_disable;
 480         irq_chip->irq_unmask = gpio_rcar_irq_enable;
 481         irq_chip->irq_set_type = gpio_rcar_irq_set_type;
 482         irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
 483         irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
 484
 485         ret = gpiochip_add_data(gpio_chip, p);
 486         if (ret) {
 487                 dev_err(dev, "failed to add GPIO controller\n");
 488                 goto err0;
 489         }
 490
 491         ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
 492                                    IRQ_TYPE_NONE);
 493         if (ret) {
 494                 dev_err(dev, "cannot add irqchip\n");
 495                 goto err1;
 496         }
 497
 498         p->irq_parent = irq->start;
 499         if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
 500                              IRQF_SHARED, name, p)) {
 501                 dev_err(dev, "failed to request IRQ\n");
 502                 ret = -ENOENT;
 503                 goto err1;
 504         }
 505
 506         dev_info(dev, "driving %d GPIOs\n", npins);
 507
 508         return 0;
 509
 510 err1:
 511         gpiochip_remove(gpio_chip);
 512 err0:
 513         pm_runtime_disable(dev);
 514         return ret;
 515 }
 516
 517 static int gpio_rcar_remove(struct platform_device *pdev)
 518 {
 519         struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
 520
 521         gpiochip_remove(&p->gpio_chip);
 522
 523         pm_runtime_disable(&pdev->dev);
 524         return 0;
 525 }
 526
 527 #ifdef CONFIG_PM_SLEEP
 528 static int gpio_rcar_suspend(struct device *dev)
 529 {
 530         struct gpio_rcar_priv *p = dev_get_drvdata(dev);
 531
 532         p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
 533         p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
 534         p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
 535         p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
 536         p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
 537         p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
 538         if (p->has_both_edge_trigger)
 539                 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
 540
 541         if (atomic_read(&p->wakeup_path))
 542                 device_set_wakeup_path(dev);
 543
 544         return 0;
 545 }
 546
 547 static int gpio_rcar_resume(struct device *dev)
 548 {
 549         struct gpio_rcar_priv *p = dev_get_drvdata(dev);
 550         unsigned int offset;
 551         u32 mask;
 552
 553         for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
 554                 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
 555                         continue;
 556
 557                 mask = BIT(offset);
 558                 /* I/O pin */
 559                 if (!(p->bank_info.iointsel & mask)) {
 560                         if (p->bank_info.inoutsel & mask)
 561                                 gpio_rcar_direction_output(
 562                                         &p->gpio_chip, offset,
 563                                         !!(p->bank_info.outdt & mask));
 564                         else
 565                                 gpio_rcar_direction_input(&p->gpio_chip,
 566                                                           offset);
 567                 } else {
 568                         /* Interrupt pin */
 569                         gpio_rcar_config_interrupt_input_mode(
 570                                 p,
 571                                 offset,
 572                                 !(p->bank_info.posneg & mask),
 573                                 !(p->bank_info.edglevel & mask),
 574                                 !!(p->bank_info.bothedge & mask));
 575
 576                         if (p->bank_info.intmsk & mask)
 577                                 gpio_rcar_write(p, MSKCLR, mask);
 578                 }
 579         }
 580
 581         return 0;
 582 }
 583 #endif /* CONFIG_PM_SLEEP*/
 584
 585 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
 586
 587 static struct platform_driver gpio_rcar_device_driver = {
 588         .probe          = gpio_rcar_probe,
 589         .remove         = gpio_rcar_remove,
 590         .driver         = {
 591                 .name   = "gpio_rcar",
 592                 .pm     = &gpio_rcar_pm_ops,
 593                 .of_match_table = of_match_ptr(gpio_rcar_of_table),
 594         }
 595 };
 596
 597 module_platform_driver(gpio_rcar_device_driver);
 598
 599 MODULE_AUTHOR("Magnus Damm");
 600 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
 601 MODULE_LICENSE("GPL v2");