]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpio/gpio-rcar.c
Merge branch 'linux-4.15' of git://github.com/skeggsb/linux into drm-fixes
[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-rcar.c
1 /*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/gpio.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/ioport.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/spinlock.h>
32 #include <linux/slab.h>
33
34 struct gpio_rcar_priv {
35 void __iomem *base;
36 spinlock_t lock;
37 struct platform_device *pdev;
38 struct gpio_chip gpio_chip;
39 struct irq_chip irq_chip;
40 struct clk *clk;
41 unsigned int irq_parent;
42 bool has_both_edge_trigger;
43 bool needs_clk;
44 };
45
46 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
47 #define INOUTSEL 0x04 /* General Input/Output Switching Register */
48 #define OUTDT 0x08 /* General Output Register */
49 #define INDT 0x0c /* General Input Register */
50 #define INTDT 0x10 /* Interrupt Display Register */
51 #define INTCLR 0x14 /* Interrupt Clear Register */
52 #define INTMSK 0x18 /* Interrupt Mask Register */
53 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
54 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
55 #define EDGLEVEL 0x24 /* Edge/level Select Register */
56 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
57 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
58
59 #define RCAR_MAX_GPIO_PER_BANK 32
60
61 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
62 {
63 return ioread32(p->base + offs);
64 }
65
66 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
67 u32 value)
68 {
69 iowrite32(value, p->base + offs);
70 }
71
72 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
73 int bit, bool value)
74 {
75 u32 tmp = gpio_rcar_read(p, offs);
76
77 if (value)
78 tmp |= BIT(bit);
79 else
80 tmp &= ~BIT(bit);
81
82 gpio_rcar_write(p, offs, tmp);
83 }
84
85 static void gpio_rcar_irq_disable(struct irq_data *d)
86 {
87 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
88 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
89
90 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
91 }
92
93 static void gpio_rcar_irq_enable(struct irq_data *d)
94 {
95 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
96 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
97
98 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
99 }
100
101 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
102 unsigned int hwirq,
103 bool active_high_rising_edge,
104 bool level_trigger,
105 bool both)
106 {
107 unsigned long flags;
108
109 /* follow steps in the GPIO documentation for
110 * "Setting Edge-Sensitive Interrupt Input Mode" and
111 * "Setting Level-Sensitive Interrupt Input Mode"
112 */
113
114 spin_lock_irqsave(&p->lock, flags);
115
116 /* Configure postive or negative logic in POSNEG */
117 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
118
119 /* Configure edge or level trigger in EDGLEVEL */
120 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
121
122 /* Select one edge or both edges in BOTHEDGE */
123 if (p->has_both_edge_trigger)
124 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
125
126 /* Select "Interrupt Input Mode" in IOINTSEL */
127 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
128
129 /* Write INTCLR in case of edge trigger */
130 if (!level_trigger)
131 gpio_rcar_write(p, INTCLR, BIT(hwirq));
132
133 spin_unlock_irqrestore(&p->lock, flags);
134 }
135
136 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
137 {
138 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
139 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
140 unsigned int hwirq = irqd_to_hwirq(d);
141
142 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
143
144 switch (type & IRQ_TYPE_SENSE_MASK) {
145 case IRQ_TYPE_LEVEL_HIGH:
146 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
147 false);
148 break;
149 case IRQ_TYPE_LEVEL_LOW:
150 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
151 false);
152 break;
153 case IRQ_TYPE_EDGE_RISING:
154 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
155 false);
156 break;
157 case IRQ_TYPE_EDGE_FALLING:
158 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
159 false);
160 break;
161 case IRQ_TYPE_EDGE_BOTH:
162 if (!p->has_both_edge_trigger)
163 return -EINVAL;
164 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
165 true);
166 break;
167 default:
168 return -EINVAL;
169 }
170 return 0;
171 }
172
173 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
174 {
175 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
176 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
177 int error;
178
179 if (p->irq_parent) {
180 error = irq_set_irq_wake(p->irq_parent, on);
181 if (error) {
182 dev_dbg(&p->pdev->dev,
183 "irq %u doesn't support irq_set_wake\n",
184 p->irq_parent);
185 p->irq_parent = 0;
186 }
187 }
188
189 if (!p->clk)
190 return 0;
191
192 if (on)
193 clk_enable(p->clk);
194 else
195 clk_disable(p->clk);
196
197 return 0;
198 }
199
200 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
201 {
202 struct gpio_rcar_priv *p = dev_id;
203 u32 pending;
204 unsigned int offset, irqs_handled = 0;
205
206 while ((pending = gpio_rcar_read(p, INTDT) &
207 gpio_rcar_read(p, INTMSK))) {
208 offset = __ffs(pending);
209 gpio_rcar_write(p, INTCLR, BIT(offset));
210 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
211 offset));
212 irqs_handled++;
213 }
214
215 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
216 }
217
218 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
219 unsigned int gpio,
220 bool output)
221 {
222 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
223 unsigned long flags;
224
225 /* follow steps in the GPIO documentation for
226 * "Setting General Output Mode" and
227 * "Setting General Input Mode"
228 */
229
230 spin_lock_irqsave(&p->lock, flags);
231
232 /* Configure postive logic in POSNEG */
233 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
234
235 /* Select "General Input/Output Mode" in IOINTSEL */
236 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
237
238 /* Select Input Mode or Output Mode in INOUTSEL */
239 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
240
241 spin_unlock_irqrestore(&p->lock, flags);
242 }
243
244 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
245 {
246 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
247 int error;
248
249 error = pm_runtime_get_sync(&p->pdev->dev);
250 if (error < 0)
251 return error;
252
253 error = pinctrl_gpio_request(chip->base + offset);
254 if (error)
255 pm_runtime_put(&p->pdev->dev);
256
257 return error;
258 }
259
260 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
261 {
262 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
263
264 pinctrl_gpio_free(chip->base + offset);
265
266 /*
267 * Set the GPIO as an input to ensure that the next GPIO request won't
268 * drive the GPIO pin as an output.
269 */
270 gpio_rcar_config_general_input_output_mode(chip, offset, false);
271
272 pm_runtime_put(&p->pdev->dev);
273 }
274
275 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
276 {
277 gpio_rcar_config_general_input_output_mode(chip, offset, false);
278 return 0;
279 }
280
281 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
282 {
283 u32 bit = BIT(offset);
284
285 /* testing on r8a7790 shows that INDT does not show correct pin state
286 * when configured as output, so use OUTDT in case of output pins */
287 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
288 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
289 else
290 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
291 }
292
293 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
294 {
295 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
296 unsigned long flags;
297
298 spin_lock_irqsave(&p->lock, flags);
299 gpio_rcar_modify_bit(p, OUTDT, offset, value);
300 spin_unlock_irqrestore(&p->lock, flags);
301 }
302
303 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
304 unsigned long *bits)
305 {
306 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
307 unsigned long flags;
308 u32 val, bankmask;
309
310 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
311 if (!bankmask)
312 return;
313
314 spin_lock_irqsave(&p->lock, flags);
315 val = gpio_rcar_read(p, OUTDT);
316 val &= ~bankmask;
317 val |= (bankmask & bits[0]);
318 gpio_rcar_write(p, OUTDT, val);
319 spin_unlock_irqrestore(&p->lock, flags);
320 }
321
322 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
323 int value)
324 {
325 /* write GPIO value to output before selecting output mode of pin */
326 gpio_rcar_set(chip, offset, value);
327 gpio_rcar_config_general_input_output_mode(chip, offset, true);
328 return 0;
329 }
330
331 struct gpio_rcar_info {
332 bool has_both_edge_trigger;
333 bool needs_clk;
334 };
335
336 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
337 .has_both_edge_trigger = false,
338 .needs_clk = false,
339 };
340
341 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
342 .has_both_edge_trigger = true,
343 .needs_clk = true,
344 };
345
346 static const struct of_device_id gpio_rcar_of_table[] = {
347 {
348 .compatible = "renesas,gpio-r8a7743",
349 /* RZ/G1 GPIO is identical to R-Car Gen2. */
350 .data = &gpio_rcar_info_gen2,
351 }, {
352 .compatible = "renesas,gpio-r8a7790",
353 .data = &gpio_rcar_info_gen2,
354 }, {
355 .compatible = "renesas,gpio-r8a7791",
356 .data = &gpio_rcar_info_gen2,
357 }, {
358 .compatible = "renesas,gpio-r8a7792",
359 .data = &gpio_rcar_info_gen2,
360 }, {
361 .compatible = "renesas,gpio-r8a7793",
362 .data = &gpio_rcar_info_gen2,
363 }, {
364 .compatible = "renesas,gpio-r8a7794",
365 .data = &gpio_rcar_info_gen2,
366 }, {
367 .compatible = "renesas,gpio-r8a7795",
368 /* Gen3 GPIO is identical to Gen2. */
369 .data = &gpio_rcar_info_gen2,
370 }, {
371 .compatible = "renesas,gpio-r8a7796",
372 /* Gen3 GPIO is identical to Gen2. */
373 .data = &gpio_rcar_info_gen2,
374 }, {
375 .compatible = "renesas,rcar-gen1-gpio",
376 .data = &gpio_rcar_info_gen1,
377 }, {
378 .compatible = "renesas,rcar-gen2-gpio",
379 .data = &gpio_rcar_info_gen2,
380 }, {
381 .compatible = "renesas,rcar-gen3-gpio",
382 /* Gen3 GPIO is identical to Gen2. */
383 .data = &gpio_rcar_info_gen2,
384 }, {
385 .compatible = "renesas,gpio-rcar",
386 .data = &gpio_rcar_info_gen1,
387 }, {
388 /* Terminator */
389 },
390 };
391
392 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
393
394 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
395 {
396 struct device_node *np = p->pdev->dev.of_node;
397 const struct gpio_rcar_info *info;
398 struct of_phandle_args args;
399 int ret;
400
401 info = of_device_get_match_data(&p->pdev->dev);
402
403 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
404 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
405 p->has_both_edge_trigger = info->has_both_edge_trigger;
406 p->needs_clk = info->needs_clk;
407
408 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
409 dev_warn(&p->pdev->dev,
410 "Invalid number of gpio lines %u, using %u\n", *npins,
411 RCAR_MAX_GPIO_PER_BANK);
412 *npins = RCAR_MAX_GPIO_PER_BANK;
413 }
414
415 return 0;
416 }
417
418 static int gpio_rcar_probe(struct platform_device *pdev)
419 {
420 struct gpio_rcar_priv *p;
421 struct resource *io, *irq;
422 struct gpio_chip *gpio_chip;
423 struct irq_chip *irq_chip;
424 struct device *dev = &pdev->dev;
425 const char *name = dev_name(dev);
426 unsigned int npins;
427 int ret;
428
429 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
430 if (!p)
431 return -ENOMEM;
432
433 p->pdev = pdev;
434 spin_lock_init(&p->lock);
435
436 /* Get device configuration from DT node */
437 ret = gpio_rcar_parse_dt(p, &npins);
438 if (ret < 0)
439 return ret;
440
441 platform_set_drvdata(pdev, p);
442
443 p->clk = devm_clk_get(dev, NULL);
444 if (IS_ERR(p->clk)) {
445 if (p->needs_clk) {
446 dev_err(dev, "unable to get clock\n");
447 ret = PTR_ERR(p->clk);
448 goto err0;
449 }
450 p->clk = NULL;
451 }
452
453 pm_runtime_enable(dev);
454
455 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
456 if (!irq) {
457 dev_err(dev, "missing IRQ\n");
458 ret = -EINVAL;
459 goto err0;
460 }
461
462 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
463 p->base = devm_ioremap_resource(dev, io);
464 if (IS_ERR(p->base)) {
465 ret = PTR_ERR(p->base);
466 goto err0;
467 }
468
469 gpio_chip = &p->gpio_chip;
470 gpio_chip->request = gpio_rcar_request;
471 gpio_chip->free = gpio_rcar_free;
472 gpio_chip->direction_input = gpio_rcar_direction_input;
473 gpio_chip->get = gpio_rcar_get;
474 gpio_chip->direction_output = gpio_rcar_direction_output;
475 gpio_chip->set = gpio_rcar_set;
476 gpio_chip->set_multiple = gpio_rcar_set_multiple;
477 gpio_chip->label = name;
478 gpio_chip->parent = dev;
479 gpio_chip->owner = THIS_MODULE;
480 gpio_chip->base = -1;
481 gpio_chip->ngpio = npins;
482
483 irq_chip = &p->irq_chip;
484 irq_chip->name = name;
485 irq_chip->parent_device = dev;
486 irq_chip->irq_mask = gpio_rcar_irq_disable;
487 irq_chip->irq_unmask = gpio_rcar_irq_enable;
488 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
489 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
490 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
491
492 ret = gpiochip_add_data(gpio_chip, p);
493 if (ret) {
494 dev_err(dev, "failed to add GPIO controller\n");
495 goto err0;
496 }
497
498 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
499 IRQ_TYPE_NONE);
500 if (ret) {
501 dev_err(dev, "cannot add irqchip\n");
502 goto err1;
503 }
504
505 p->irq_parent = irq->start;
506 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
507 IRQF_SHARED, name, p)) {
508 dev_err(dev, "failed to request IRQ\n");
509 ret = -ENOENT;
510 goto err1;
511 }
512
513 dev_info(dev, "driving %d GPIOs\n", npins);
514
515 return 0;
516
517 err1:
518 gpiochip_remove(gpio_chip);
519 err0:
520 pm_runtime_disable(dev);
521 return ret;
522 }
523
524 static int gpio_rcar_remove(struct platform_device *pdev)
525 {
526 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
527
528 gpiochip_remove(&p->gpio_chip);
529
530 pm_runtime_disable(&pdev->dev);
531 return 0;
532 }
533
534 static struct platform_driver gpio_rcar_device_driver = {
535 .probe = gpio_rcar_probe,
536 .remove = gpio_rcar_remove,
537 .driver = {
538 .name = "gpio_rcar",
539 .of_match_table = of_match_ptr(gpio_rcar_of_table),
540 }
541 };
542
543 module_platform_driver(gpio_rcar_device_driver);
544
545 MODULE_AUTHOR("Magnus Damm");
546 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
547 MODULE_LICENSE("GPL v2");