drivers/gpio/gpio-rcar.c

   1 /*
   2  * Renesas R-Car GPIO Support
   3  *
   4  *  Copyright (C) 2014 Renesas Electronics Corporation
   5  *  Copyright (C) 2013 Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/err.h>
  18 #include <linux/gpio/driver.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/ioport.h>
  23 #include <linux/irq.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/slab.h>
  32
  33 struct gpio_rcar_bank_info {
  34         u32 iointsel;
  35         u32 inoutsel;
  36         u32 outdt;
  37         u32 posneg;
  38         u32 edglevel;
  39         u32 bothedge;
  40         u32 intmsk;
  41 };
  42
  43 struct gpio_rcar_priv {
  44         void __iomem *base;
  45         spinlock_t lock;
  46         struct platform_device *pdev;
  47         struct gpio_chip gpio_chip;
  48         struct irq_chip irq_chip;
  49         unsigned int irq_parent;
  50         atomic_t wakeup_path;
  51         bool has_both_edge_trigger;
  52         struct gpio_rcar_bank_info bank_info;
  53 };
  54
  55 #define IOINTSEL 0x00   /* General IO/Interrupt Switching Register */
  56 #define INOUTSEL 0x04   /* General Input/Output Switching Register */
  57 #define OUTDT 0x08      /* General Output Register */
  58 #define INDT 0x0c       /* General Input Register */
  59 #define INTDT 0x10      /* Interrupt Display Register */
  60 #define INTCLR 0x14     /* Interrupt Clear Register */
  61 #define INTMSK 0x18     /* Interrupt Mask Register */
  62 #define MSKCLR 0x1c     /* Interrupt Mask Clear Register */
  63 #define POSNEG 0x20     /* Positive/Negative Logic Select Register */
  64 #define EDGLEVEL 0x24   /* Edge/level Select Register */
  65 #define FILONOFF 0x28   /* Chattering Prevention On/Off Register */
  66 #define BOTHEDGE 0x4c   /* One Edge/Both Edge Select Register */
  67
  68 #define RCAR_MAX_GPIO_PER_BANK          32
  69
  70 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  71 {
  72         return ioread32(p->base + offs);
  73 }
  74
  75 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  76                                    u32 value)
  77 {
  78         iowrite32(value, p->base + offs);
  79 }
  80
  81 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  82                                  int bit, bool value)
  83 {
  84         u32 tmp = gpio_rcar_read(p, offs);
  85
  86         if (value)
  87                 tmp |= BIT(bit);
  88         else
  89                 tmp &= ~BIT(bit);
  90
  91         gpio_rcar_write(p, offs, tmp);
  92 }
  93
  94 static void gpio_rcar_irq_disable(struct irq_data *d)
  95 {
  96         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  97         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
  98
  99         gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
 100 }
 101
 102 static void gpio_rcar_irq_enable(struct irq_data *d)
 103 {
 104         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 105         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 106
 107         gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
 108 }
 109
 110 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 111                                                   unsigned int hwirq,
 112                                                   bool active_high_rising_edge,
 113                                                   bool level_trigger,
 114                                                   bool both)
 115 {
 116         unsigned long flags;
 117
 118         /* follow steps in the GPIO documentation for
 119          * "Setting Edge-Sensitive Interrupt Input Mode" and
 120          * "Setting Level-Sensitive Interrupt Input Mode"
 121          */
 122
 123         spin_lock_irqsave(&p->lock, flags);
 124
 125         /* Configure postive or negative logic in POSNEG */
 126         gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
 127
 128         /* Configure edge or level trigger in EDGLEVEL */
 129         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 130
 131         /* Select one edge or both edges in BOTHEDGE */
 132         if (p->has_both_edge_trigger)
 133                 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
 134
 135         /* Select "Interrupt Input Mode" in IOINTSEL */
 136         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 137
 138         /* Write INTCLR in case of edge trigger */
 139         if (!level_trigger)
 140                 gpio_rcar_write(p, INTCLR, BIT(hwirq));
 141
 142         spin_unlock_irqrestore(&p->lock, flags);
 143 }
 144
 145 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 146 {
 147         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 148         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 149         unsigned int hwirq = irqd_to_hwirq(d);
 150
 151         dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
 152
 153         switch (type & IRQ_TYPE_SENSE_MASK) {
 154         case IRQ_TYPE_LEVEL_HIGH:
 155                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
 156                                                       false);
 157                 break;
 158         case IRQ_TYPE_LEVEL_LOW:
 159                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
 160                                                       false);
 161                 break;
 162         case IRQ_TYPE_EDGE_RISING:
 163                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 164                                                       false);
 165                 break;
 166         case IRQ_TYPE_EDGE_FALLING:
 167                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
 168                                                       false);
 169                 break;
 170         case IRQ_TYPE_EDGE_BOTH:
 171                 if (!p->has_both_edge_trigger)
 172                         return -EINVAL;
 173                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 174                                                       true);
 175                 break;
 176         default:
 177                 return -EINVAL;
 178         }
 179         return 0;
 180 }
 181
 182 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
 183 {
 184         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 185         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 186         int error;
 187
 188         if (p->irq_parent) {
 189                 error = irq_set_irq_wake(p->irq_parent, on);
 190                 if (error) {
 191                         dev_dbg(&p->pdev->dev,
 192                                 "irq %u doesn't support irq_set_wake\n",
 193                                 p->irq_parent);
 194                         p->irq_parent = 0;
 195                 }
 196         }
 197
 198         if (on)
 199                 atomic_inc(&p->wakeup_path);
 200         else
 201                 atomic_dec(&p->wakeup_path);
 202
 203         return 0;
 204 }
 205
 206 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
 207 {
 208         struct gpio_rcar_priv *p = dev_id;
 209         u32 pending;
 210         unsigned int offset, irqs_handled = 0;
 211
 212         while ((pending = gpio_rcar_read(p, INTDT) &
 213                           gpio_rcar_read(p, INTMSK))) {
 214                 offset = __ffs(pending);
 215                 gpio_rcar_write(p, INTCLR, BIT(offset));
 216                 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
 217                                                     offset));
 218                 irqs_handled++;
 219         }
 220
 221         return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 222 }
 223
 224 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 225                                                        unsigned int gpio,
 226                                                        bool output)
 227 {
 228         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 229         unsigned long flags;
 230
 231         /* follow steps in the GPIO documentation for
 232          * "Setting General Output Mode" and
 233          * "Setting General Input Mode"
 234          */
 235
 236         spin_lock_irqsave(&p->lock, flags);
 237
 238         /* Configure postive logic in POSNEG */
 239         gpio_rcar_modify_bit(p, POSNEG, gpio, false);
 240
 241         /* Select "General Input/Output Mode" in IOINTSEL */
 242         gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
 243
 244         /* Select Input Mode or Output Mode in INOUTSEL */
 245         gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
 246
 247         spin_unlock_irqrestore(&p->lock, flags);
 248 }
 249
 250 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 251 {
 252         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 253         int error;
 254
 255         error = pm_runtime_get_sync(&p->pdev->dev);
 256         if (error < 0)
 257                 return error;
 258
 259         error = pinctrl_gpio_request(chip->base + offset);
 260         if (error)
 261                 pm_runtime_put(&p->pdev->dev);
 262
 263         return error;
 264 }
 265
 266 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 267 {
 268         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 269
 270         pinctrl_gpio_free(chip->base + offset);
 271
 272         /*
 273          * Set the GPIO as an input to ensure that the next GPIO request won't
 274          * drive the GPIO pin as an output.
 275          */
 276         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 277
 278         pm_runtime_put(&p->pdev->dev);
 279 }
 280
 281 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
 282 {
 283         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 284
 285         return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
 286 }
 287
 288 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 289 {
 290         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 291         return 0;
 292 }
 293
 294 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
 295 {
 296         u32 bit = BIT(offset);
 297
 298         /* testing on r8a7790 shows that INDT does not show correct pin state
 299          * when configured as output, so use OUTDT in case of output pins */
 300         if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
 301                 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
 302         else
 303                 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
 304 }
 305
 306 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
 307 {
 308         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 309         unsigned long flags;
 310
 311         spin_lock_irqsave(&p->lock, flags);
 312         gpio_rcar_modify_bit(p, OUTDT, offset, value);
 313         spin_unlock_irqrestore(&p->lock, flags);
 314 }
 315
 316 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
 317                                    unsigned long *bits)
 318 {
 319         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 320         unsigned long flags;
 321         u32 val, bankmask;
 322
 323         bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
 324         if (chip->valid_mask)
 325                 bankmask &= chip->valid_mask[0];
 326
 327         if (!bankmask)
 328                 return;
 329
 330         spin_lock_irqsave(&p->lock, flags);
 331         val = gpio_rcar_read(p, OUTDT);
 332         val &= ~bankmask;
 333         val |= (bankmask & bits[0]);
 334         gpio_rcar_write(p, OUTDT, val);
 335         spin_unlock_irqrestore(&p->lock, flags);
 336 }
 337
 338 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 339                                       int value)
 340 {
 341         /* write GPIO value to output before selecting output mode of pin */
 342         gpio_rcar_set(chip, offset, value);
 343         gpio_rcar_config_general_input_output_mode(chip, offset, true);
 344         return 0;
 345 }
 346
 347 struct gpio_rcar_info {
 348         bool has_both_edge_trigger;
 349 };
 350
 351 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
 352         .has_both_edge_trigger = false,
 353 };
 354
 355 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
 356         .has_both_edge_trigger = true,
 357 };
 358
 359 static const struct of_device_id gpio_rcar_of_table[] = {
 360         {
 361                 .compatible = "renesas,gpio-r8a7743",
 362                 /* RZ/G1 GPIO is identical to R-Car Gen2. */
 363                 .data = &gpio_rcar_info_gen2,
 364         }, {
 365                 .compatible = "renesas,gpio-r8a7790",
 366                 .data = &gpio_rcar_info_gen2,
 367         }, {
 368                 .compatible = "renesas,gpio-r8a7791",
 369                 .data = &gpio_rcar_info_gen2,
 370         }, {
 371                 .compatible = "renesas,gpio-r8a7792",
 372                 .data = &gpio_rcar_info_gen2,
 373         }, {
 374                 .compatible = "renesas,gpio-r8a7793",
 375                 .data = &gpio_rcar_info_gen2,
 376         }, {
 377                 .compatible = "renesas,gpio-r8a7794",
 378                 .data = &gpio_rcar_info_gen2,
 379         }, {
 380                 .compatible = "renesas,gpio-r8a7795",
 381                 /* Gen3 GPIO is identical to Gen2. */
 382                 .data = &gpio_rcar_info_gen2,
 383         }, {
 384                 .compatible = "renesas,gpio-r8a7796",
 385                 /* Gen3 GPIO is identical to Gen2. */
 386                 .data = &gpio_rcar_info_gen2,
 387         }, {
 388                 .compatible = "renesas,rcar-gen1-gpio",
 389                 .data = &gpio_rcar_info_gen1,
 390         }, {
 391                 .compatible = "renesas,rcar-gen2-gpio",
 392                 .data = &gpio_rcar_info_gen2,
 393         }, {
 394                 .compatible = "renesas,rcar-gen3-gpio",
 395                 /* Gen3 GPIO is identical to Gen2. */
 396                 .data = &gpio_rcar_info_gen2,
 397         }, {
 398                 .compatible = "renesas,gpio-rcar",
 399                 .data = &gpio_rcar_info_gen1,
 400         }, {
 401                 /* Terminator */
 402         },
 403 };
 404
 405 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
 406
 407 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
 408 {
 409         struct device_node *np = p->pdev->dev.of_node;
 410         const struct gpio_rcar_info *info;
 411         struct of_phandle_args args;
 412         int ret;
 413
 414         info = of_device_get_match_data(&p->pdev->dev);
 415
 416         ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
 417         *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
 418         p->has_both_edge_trigger = info->has_both_edge_trigger;
 419
 420         if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
 421                 dev_warn(&p->pdev->dev,
 422                          "Invalid number of gpio lines %u, using %u\n", *npins,
 423                          RCAR_MAX_GPIO_PER_BANK);
 424                 *npins = RCAR_MAX_GPIO_PER_BANK;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int gpio_rcar_probe(struct platform_device *pdev)
 431 {
 432         struct gpio_rcar_priv *p;
 433         struct resource *io, *irq;
 434         struct gpio_chip *gpio_chip;
 435         struct irq_chip *irq_chip;
 436         struct device *dev = &pdev->dev;
 437         const char *name = dev_name(dev);
 438         unsigned int npins;
 439         int ret;
 440
 441         p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
 442         if (!p)
 443                 return -ENOMEM;
 444
 445         p->pdev = pdev;
 446         spin_lock_init(&p->lock);
 447
 448         /* Get device configuration from DT node */
 449         ret = gpio_rcar_parse_dt(p, &npins);
 450         if (ret < 0)
 451                 return ret;
 452
 453         platform_set_drvdata(pdev, p);
 454
 455         pm_runtime_enable(dev);
 456
 457         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 458         if (!irq) {
 459                 dev_err(dev, "missing IRQ\n");
 460                 ret = -EINVAL;
 461                 goto err0;
 462         }
 463
 464         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 465         p->base = devm_ioremap_resource(dev, io);
 466         if (IS_ERR(p->base)) {
 467                 ret = PTR_ERR(p->base);
 468                 goto err0;
 469         }
 470
 471         gpio_chip = &p->gpio_chip;
 472         gpio_chip->request = gpio_rcar_request;
 473         gpio_chip->free = gpio_rcar_free;
 474         gpio_chip->get_direction = gpio_rcar_get_direction;
 475         gpio_chip->direction_input = gpio_rcar_direction_input;
 476         gpio_chip->get = gpio_rcar_get;
 477         gpio_chip->direction_output = gpio_rcar_direction_output;
 478         gpio_chip->set = gpio_rcar_set;
 479         gpio_chip->set_multiple = gpio_rcar_set_multiple;
 480         gpio_chip->label = name;
 481         gpio_chip->parent = dev;
 482         gpio_chip->owner = THIS_MODULE;
 483         gpio_chip->base = -1;
 484         gpio_chip->ngpio = npins;
 485
 486         irq_chip = &p->irq_chip;
 487         irq_chip->name = name;
 488         irq_chip->parent_device = dev;
 489         irq_chip->irq_mask = gpio_rcar_irq_disable;
 490         irq_chip->irq_unmask = gpio_rcar_irq_enable;
 491         irq_chip->irq_set_type = gpio_rcar_irq_set_type;
 492         irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
 493         irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
 494
 495         ret = gpiochip_add_data(gpio_chip, p);
 496         if (ret) {
 497                 dev_err(dev, "failed to add GPIO controller\n");
 498                 goto err0;
 499         }
 500
 501         ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
 502                                    IRQ_TYPE_NONE);
 503         if (ret) {
 504                 dev_err(dev, "cannot add irqchip\n");
 505                 goto err1;
 506         }
 507
 508         p->irq_parent = irq->start;
 509         if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
 510                              IRQF_SHARED, name, p)) {
 511                 dev_err(dev, "failed to request IRQ\n");
 512                 ret = -ENOENT;
 513                 goto err1;
 514         }
 515
 516         dev_info(dev, "driving %d GPIOs\n", npins);
 517
 518         return 0;
 519
 520 err1:
 521         gpiochip_remove(gpio_chip);
 522 err0:
 523         pm_runtime_disable(dev);
 524         return ret;
 525 }
 526
 527 static int gpio_rcar_remove(struct platform_device *pdev)
 528 {
 529         struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
 530
 531         gpiochip_remove(&p->gpio_chip);
 532
 533         pm_runtime_disable(&pdev->dev);
 534         return 0;
 535 }
 536
 537 #ifdef CONFIG_PM_SLEEP
 538 static int gpio_rcar_suspend(struct device *dev)
 539 {
 540         struct gpio_rcar_priv *p = dev_get_drvdata(dev);
 541
 542         p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
 543         p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
 544         p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
 545         p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
 546         p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
 547         p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
 548         if (p->has_both_edge_trigger)
 549                 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
 550
 551         if (atomic_read(&p->wakeup_path))
 552                 device_set_wakeup_path(dev);
 553
 554         return 0;
 555 }
 556
 557 static int gpio_rcar_resume(struct device *dev)
 558 {
 559         struct gpio_rcar_priv *p = dev_get_drvdata(dev);
 560         unsigned int offset;
 561         u32 mask;
 562
 563         for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
 564                 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
 565                         continue;
 566
 567                 mask = BIT(offset);
 568                 /* I/O pin */
 569                 if (!(p->bank_info.iointsel & mask)) {
 570                         if (p->bank_info.inoutsel & mask)
 571                                 gpio_rcar_direction_output(
 572                                         &p->gpio_chip, offset,
 573                                         !!(p->bank_info.outdt & mask));
 574                         else
 575                                 gpio_rcar_direction_input(&p->gpio_chip,
 576                                                           offset);
 577                 } else {
 578                         /* Interrupt pin */
 579                         gpio_rcar_config_interrupt_input_mode(
 580                                 p,
 581                                 offset,
 582                                 !(p->bank_info.posneg & mask),
 583                                 !(p->bank_info.edglevel & mask),
 584                                 !!(p->bank_info.bothedge & mask));
 585
 586                         if (p->bank_info.intmsk & mask)
 587                                 gpio_rcar_write(p, MSKCLR, mask);
 588                 }
 589         }
 590
 591         return 0;
 592 }
 593 #endif /* CONFIG_PM_SLEEP*/
 594
 595 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
 596
 597 static struct platform_driver gpio_rcar_device_driver = {
 598         .probe          = gpio_rcar_probe,
 599         .remove         = gpio_rcar_remove,
 600         .driver         = {
 601                 .name   = "gpio_rcar",
 602                 .pm     = &gpio_rcar_pm_ops,
 603                 .of_match_table = of_match_ptr(gpio_rcar_of_table),
 604         }
 605 };
 606
 607 module_platform_driver(gpio_rcar_device_driver);
 608
 609 MODULE_AUTHOR("Magnus Damm");
 610 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
 611 MODULE_LICENSE("GPL v2");