2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
30 #include <mach/hardware.h>
32 #include <mach/regs-clock.h>
33 #include <mach/regs-gpio.h>
36 #include <plat/gpio-core.h>
37 #include <plat/gpio-cfg.h>
38 #include <plat/gpio-cfg-helpers.h>
39 #include <plat/gpio-fns.h>
43 #define gpio_dbg(x...) do { } while (0)
45 #define gpio_dbg(x...) printk(KERN_DEBUG x)
48 int samsung_gpio_setpull_updown(struct samsung_gpio_chip
*chip
,
49 unsigned int off
, samsung_gpio_pull_t pull
)
51 void __iomem
*reg
= chip
->base
+ 0x08;
55 pup
= __raw_readl(reg
);
58 __raw_writel(pup
, reg
);
63 samsung_gpio_pull_t
samsung_gpio_getpull_updown(struct samsung_gpio_chip
*chip
,
66 void __iomem
*reg
= chip
->base
+ 0x08;
68 u32 pup
= __raw_readl(reg
);
73 return (__force samsung_gpio_pull_t
)pup
;
76 int s3c2443_gpio_setpull(struct samsung_gpio_chip
*chip
,
77 unsigned int off
, samsung_gpio_pull_t pull
)
80 case S3C_GPIO_PULL_NONE
:
83 case S3C_GPIO_PULL_UP
:
86 case S3C_GPIO_PULL_DOWN
:
90 return samsung_gpio_setpull_updown(chip
, off
, pull
);
93 samsung_gpio_pull_t
s3c2443_gpio_getpull(struct samsung_gpio_chip
*chip
,
96 samsung_gpio_pull_t pull
;
98 pull
= samsung_gpio_getpull_updown(chip
, off
);
102 pull
= S3C_GPIO_PULL_UP
;
106 pull
= S3C_GPIO_PULL_NONE
;
109 pull
= S3C_GPIO_PULL_DOWN
;
116 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip
*chip
,
117 unsigned int off
, samsung_gpio_pull_t pull
,
118 samsung_gpio_pull_t updown
)
120 void __iomem
*reg
= chip
->base
+ 0x08;
121 u32 pup
= __raw_readl(reg
);
125 else if (pull
== S3C_GPIO_PULL_NONE
)
130 __raw_writel(pup
, reg
);
134 static samsung_gpio_pull_t
s3c24xx_gpio_getpull_1(struct samsung_gpio_chip
*chip
,
136 samsung_gpio_pull_t updown
)
138 void __iomem
*reg
= chip
->base
+ 0x08;
139 u32 pup
= __raw_readl(reg
);
142 return pup
? S3C_GPIO_PULL_NONE
: updown
;
145 samsung_gpio_pull_t
s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip
*chip
,
148 return s3c24xx_gpio_getpull_1(chip
, off
, S3C_GPIO_PULL_UP
);
151 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip
*chip
,
152 unsigned int off
, samsung_gpio_pull_t pull
)
154 return s3c24xx_gpio_setpull_1(chip
, off
, pull
, S3C_GPIO_PULL_UP
);
157 samsung_gpio_pull_t
s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip
*chip
,
160 return s3c24xx_gpio_getpull_1(chip
, off
, S3C_GPIO_PULL_DOWN
);
163 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip
*chip
,
164 unsigned int off
, samsung_gpio_pull_t pull
)
166 return s3c24xx_gpio_setpull_1(chip
, off
, pull
, S3C_GPIO_PULL_DOWN
);
169 static int exynos4_gpio_setpull(struct samsung_gpio_chip
*chip
,
170 unsigned int off
, samsung_gpio_pull_t pull
)
172 if (pull
== S3C_GPIO_PULL_UP
)
175 return samsung_gpio_setpull_updown(chip
, off
, pull
);
178 static samsung_gpio_pull_t
exynos4_gpio_getpull(struct samsung_gpio_chip
*chip
,
181 samsung_gpio_pull_t pull
;
183 pull
= samsung_gpio_getpull_updown(chip
, off
);
186 pull
= S3C_GPIO_PULL_UP
;
192 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
193 * @chip: The gpio chip that is being configured.
194 * @off: The offset for the GPIO being configured.
195 * @cfg: The configuration value to set.
197 * This helper deal with the GPIO cases where the control register
198 * has two bits of configuration per gpio, which have the following
202 * 1x = special function
205 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip
*chip
,
206 unsigned int off
, unsigned int cfg
)
208 void __iomem
*reg
= chip
->base
;
209 unsigned int shift
= off
* 2;
212 if (samsung_gpio_is_cfg_special(cfg
)) {
220 con
= __raw_readl(reg
);
221 con
&= ~(0x3 << shift
);
223 __raw_writel(con
, reg
);
229 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
230 * @chip: The gpio chip that is being configured.
231 * @off: The offset for the GPIO being configured.
233 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value whicg
234 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
235 * S3C_GPIO_SPECIAL() macro.
238 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip
*chip
,
243 con
= __raw_readl(chip
->base
);
247 /* this conversion works for IN and OUT as well as special mode */
248 return S3C_GPIO_SPECIAL(con
);
252 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
253 * @chip: The gpio chip that is being configured.
254 * @off: The offset for the GPIO being configured.
255 * @cfg: The configuration value to set.
257 * This helper deal with the GPIO cases where the control register has 4 bits
258 * of control per GPIO, generally in the form of:
261 * others = Special functions (dependent on bank)
263 * Note, since the code to deal with the case where there are two control
264 * registers instead of one, we do not have a separate set of functions for
268 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip
*chip
,
269 unsigned int off
, unsigned int cfg
)
271 void __iomem
*reg
= chip
->base
;
272 unsigned int shift
= (off
& 7) * 4;
275 if (off
< 8 && chip
->chip
.ngpio
> 8)
278 if (samsung_gpio_is_cfg_special(cfg
)) {
283 con
= __raw_readl(reg
);
284 con
&= ~(0xf << shift
);
286 __raw_writel(con
, reg
);
292 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
293 * @chip: The gpio chip that is being configured.
294 * @off: The offset for the GPIO being configured.
296 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
297 * register setting into a value the software can use, such as could be passed
298 * to samsung_gpio_setcfg_4bit().
300 * @sa samsung_gpio_getcfg_2bit
303 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip
*chip
,
306 void __iomem
*reg
= chip
->base
;
307 unsigned int shift
= (off
& 7) * 4;
310 if (off
< 8 && chip
->chip
.ngpio
> 8)
313 con
= __raw_readl(reg
);
317 /* this conversion works for IN and OUT as well as special mode */
318 return S3C_GPIO_SPECIAL(con
);
322 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
323 * @chip: The gpio chip that is being configured.
324 * @off: The offset for the GPIO being configured.
325 * @cfg: The configuration value to set.
327 * This helper deal with the GPIO cases where the control register
328 * has one bit of configuration for the gpio, where setting the bit
329 * means the pin is in special function mode and unset means output.
332 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip
*chip
,
333 unsigned int off
, unsigned int cfg
)
335 void __iomem
*reg
= chip
->base
;
336 unsigned int shift
= off
;
339 if (samsung_gpio_is_cfg_special(cfg
)) {
342 /* Map output to 0, and SFN2 to 1 */
350 con
= __raw_readl(reg
);
351 con
&= ~(0x1 << shift
);
353 __raw_writel(con
, reg
);
359 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
360 * @chip: The gpio chip that is being configured.
361 * @off: The offset for the GPIO being configured.
363 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
364 * GPIO configuration value.
366 * @sa samsung_gpio_getcfg_2bit
367 * @sa samsung_gpio_getcfg_4bit
370 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip
*chip
,
375 con
= __raw_readl(chip
->base
);
380 return S3C_GPIO_SFN(con
);
383 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip
*chip
,
384 unsigned int off
, unsigned int cfg
)
386 void __iomem
*reg
= chip
->base
;
397 shift
= (off
& 7) * 4;
401 shift
= ((off
+ 1) & 7) * 4;
404 shift
= ((off
+ 1) & 7) * 4;
408 if (samsung_gpio_is_cfg_special(cfg
)) {
413 con
= __raw_readl(reg
);
414 con
&= ~(0xf << shift
);
416 __raw_writel(con
, reg
);
421 static void __init
samsung_gpiolib_set_cfg(struct samsung_gpio_cfg
*chipcfg
,
424 for (; nr_chips
> 0; nr_chips
--, chipcfg
++) {
425 if (!chipcfg
->set_config
)
426 chipcfg
->set_config
= samsung_gpio_setcfg_4bit
;
427 if (!chipcfg
->get_config
)
428 chipcfg
->get_config
= samsung_gpio_getcfg_4bit
;
429 if (!chipcfg
->set_pull
)
430 chipcfg
->set_pull
= samsung_gpio_setpull_updown
;
431 if (!chipcfg
->get_pull
)
432 chipcfg
->get_pull
= samsung_gpio_getpull_updown
;
436 struct samsung_gpio_cfg s3c24xx_gpiocfg_default
= {
437 .set_config
= samsung_gpio_setcfg_2bit
,
438 .get_config
= samsung_gpio_getcfg_2bit
,
441 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka
= {
442 .set_config
= s3c24xx_gpio_setcfg_abank
,
443 .get_config
= s3c24xx_gpio_getcfg_abank
,
446 static struct samsung_gpio_cfg exynos4_gpio_cfg
= {
447 .set_pull
= exynos4_gpio_setpull
,
448 .get_pull
= exynos4_gpio_getpull
,
449 .set_config
= samsung_gpio_setcfg_4bit
,
450 .get_config
= samsung_gpio_getcfg_4bit
,
453 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank
= {
455 .set_config
= s5p64x0_gpio_setcfg_rbank
,
456 .get_config
= samsung_gpio_getcfg_4bit
,
457 .set_pull
= samsung_gpio_setpull_updown
,
458 .get_pull
= samsung_gpio_getpull_updown
,
461 static struct samsung_gpio_cfg samsung_gpio_cfgs
[] = {
472 .set_config
= samsung_gpio_setcfg_2bit
,
473 .get_config
= samsung_gpio_getcfg_2bit
,
476 .set_config
= samsung_gpio_setcfg_2bit
,
477 .get_config
= samsung_gpio_getcfg_2bit
,
480 .set_config
= samsung_gpio_setcfg_2bit
,
481 .get_config
= samsung_gpio_getcfg_2bit
,
483 .set_config
= samsung_gpio_setcfg_2bit
,
484 .get_config
= samsung_gpio_getcfg_2bit
,
486 .set_pull
= exynos4_gpio_setpull
,
487 .get_pull
= exynos4_gpio_getpull
,
490 .set_pull
= exynos4_gpio_setpull
,
491 .get_pull
= exynos4_gpio_getpull
,
496 * Default routines for controlling GPIO, based on the original S3C24XX
497 * GPIO functions which deal with the case where each gpio bank of the
498 * chip is as following:
500 * base + 0x00: Control register, 2 bits per gpio
501 * gpio n: 2 bits starting at (2*n)
502 * 00 = input, 01 = output, others mean special-function
503 * base + 0x04: Data register, 1 bit per gpio
507 static int samsung_gpiolib_2bit_input(struct gpio_chip
*chip
, unsigned offset
)
509 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
510 void __iomem
*base
= ourchip
->base
;
514 samsung_gpio_lock(ourchip
, flags
);
516 con
= __raw_readl(base
+ 0x00);
517 con
&= ~(3 << (offset
* 2));
519 __raw_writel(con
, base
+ 0x00);
521 samsung_gpio_unlock(ourchip
, flags
);
525 static int samsung_gpiolib_2bit_output(struct gpio_chip
*chip
,
526 unsigned offset
, int value
)
528 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
529 void __iomem
*base
= ourchip
->base
;
534 samsung_gpio_lock(ourchip
, flags
);
536 dat
= __raw_readl(base
+ 0x04);
537 dat
&= ~(1 << offset
);
540 __raw_writel(dat
, base
+ 0x04);
542 con
= __raw_readl(base
+ 0x00);
543 con
&= ~(3 << (offset
* 2));
544 con
|= 1 << (offset
* 2);
546 __raw_writel(con
, base
+ 0x00);
547 __raw_writel(dat
, base
+ 0x04);
549 samsung_gpio_unlock(ourchip
, flags
);
554 * The samsung_gpiolib_4bit routines are to control the gpio banks where
555 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
558 * base + 0x00: Control register, 4 bits per gpio
559 * gpio n: 4 bits starting at (4*n)
560 * 0000 = input, 0001 = output, others mean special-function
561 * base + 0x04: Data register, 1 bit per gpio
564 * Note, since the data register is one bit per gpio and is at base + 0x4
565 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
566 * state of the output.
569 static int samsung_gpiolib_4bit_input(struct gpio_chip
*chip
,
572 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
573 void __iomem
*base
= ourchip
->base
;
576 con
= __raw_readl(base
+ GPIOCON_OFF
);
577 con
&= ~(0xf << con_4bit_shift(offset
));
578 __raw_writel(con
, base
+ GPIOCON_OFF
);
580 gpio_dbg("%s: %p: CON now %08lx\n", __func__
, base
, con
);
585 static int samsung_gpiolib_4bit_output(struct gpio_chip
*chip
,
586 unsigned int offset
, int value
)
588 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
589 void __iomem
*base
= ourchip
->base
;
593 con
= __raw_readl(base
+ GPIOCON_OFF
);
594 con
&= ~(0xf << con_4bit_shift(offset
));
595 con
|= 0x1 << con_4bit_shift(offset
);
597 dat
= __raw_readl(base
+ GPIODAT_OFF
);
602 dat
&= ~(1 << offset
);
604 __raw_writel(dat
, base
+ GPIODAT_OFF
);
605 __raw_writel(con
, base
+ GPIOCON_OFF
);
606 __raw_writel(dat
, base
+ GPIODAT_OFF
);
608 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__
, base
, con
, dat
);
614 * The next set of routines are for the case where the GPIO configuration
615 * registers are 4 bits per GPIO but there is more than one register (the
616 * bank has more than 8 GPIOs.
618 * This case is the similar to the 4 bit case, but the registers are as
621 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
622 * gpio n: 4 bits starting at (4*n)
623 * 0000 = input, 0001 = output, others mean special-function
624 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
625 * gpio n: 4 bits starting at (4*n)
626 * 0000 = input, 0001 = output, others mean special-function
627 * base + 0x08: Data register, 1 bit per gpio
630 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
631 * routines we store the 'base + 0x4' address so that these routines see
632 * the data register at ourchip->base + 0x04.
635 static int samsung_gpiolib_4bit2_input(struct gpio_chip
*chip
,
638 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
639 void __iomem
*base
= ourchip
->base
;
640 void __iomem
*regcon
= base
;
648 con
= __raw_readl(regcon
);
649 con
&= ~(0xf << con_4bit_shift(offset
));
650 __raw_writel(con
, regcon
);
652 gpio_dbg("%s: %p: CON %08lx\n", __func__
, base
, con
);
657 static int samsung_gpiolib_4bit2_output(struct gpio_chip
*chip
,
658 unsigned int offset
, int value
)
660 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
661 void __iomem
*base
= ourchip
->base
;
662 void __iomem
*regcon
= base
;
665 unsigned con_offset
= offset
;
672 con
= __raw_readl(regcon
);
673 con
&= ~(0xf << con_4bit_shift(con_offset
));
674 con
|= 0x1 << con_4bit_shift(con_offset
);
676 dat
= __raw_readl(base
+ GPIODAT_OFF
);
681 dat
&= ~(1 << offset
);
683 __raw_writel(dat
, base
+ GPIODAT_OFF
);
684 __raw_writel(con
, regcon
);
685 __raw_writel(dat
, base
+ GPIODAT_OFF
);
687 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__
, base
, con
, dat
);
692 /* The next set of routines are for the case of s3c24xx bank a */
694 static int s3c24xx_gpiolib_banka_input(struct gpio_chip
*chip
, unsigned offset
)
699 static int s3c24xx_gpiolib_banka_output(struct gpio_chip
*chip
,
700 unsigned offset
, int value
)
702 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
703 void __iomem
*base
= ourchip
->base
;
708 local_irq_save(flags
);
710 con
= __raw_readl(base
+ 0x00);
711 dat
= __raw_readl(base
+ 0x04);
713 dat
&= ~(1 << offset
);
717 __raw_writel(dat
, base
+ 0x04);
719 con
&= ~(1 << offset
);
721 __raw_writel(con
, base
+ 0x00);
722 __raw_writel(dat
, base
+ 0x04);
724 local_irq_restore(flags
);
728 /* The next set of routines are for the case of s5p64x0 bank r */
730 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip
*chip
,
733 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
734 void __iomem
*base
= ourchip
->base
;
735 void __iomem
*regcon
= base
;
755 samsung_gpio_lock(ourchip
, flags
);
757 con
= __raw_readl(regcon
);
758 con
&= ~(0xf << con_4bit_shift(offset
));
759 __raw_writel(con
, regcon
);
761 samsung_gpio_unlock(ourchip
, flags
);
766 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip
*chip
,
767 unsigned int offset
, int value
)
769 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
770 void __iomem
*base
= ourchip
->base
;
771 void __iomem
*regcon
= base
;
775 unsigned con_offset
= offset
;
777 switch (con_offset
) {
793 samsung_gpio_lock(ourchip
, flags
);
795 con
= __raw_readl(regcon
);
796 con
&= ~(0xf << con_4bit_shift(con_offset
));
797 con
|= 0x1 << con_4bit_shift(con_offset
);
799 dat
= __raw_readl(base
+ GPIODAT_OFF
);
803 dat
&= ~(1 << offset
);
805 __raw_writel(con
, regcon
);
806 __raw_writel(dat
, base
+ GPIODAT_OFF
);
808 samsung_gpio_unlock(ourchip
, flags
);
813 static void samsung_gpiolib_set(struct gpio_chip
*chip
,
814 unsigned offset
, int value
)
816 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
817 void __iomem
*base
= ourchip
->base
;
821 samsung_gpio_lock(ourchip
, flags
);
823 dat
= __raw_readl(base
+ 0x04);
824 dat
&= ~(1 << offset
);
827 __raw_writel(dat
, base
+ 0x04);
829 samsung_gpio_unlock(ourchip
, flags
);
832 static int samsung_gpiolib_get(struct gpio_chip
*chip
, unsigned offset
)
834 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
837 val
= __raw_readl(ourchip
->base
+ 0x04);
845 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
846 * for use with the configuration calls, and other parts of the s3c gpiolib
849 * Not all s3c support code will need this, as some configurations of cpu
850 * may only support one or two different configuration options and have an
851 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
852 * the machine support file should provide its own samsung_gpiolib_getchip()
853 * and any other necessary functions.
856 #ifdef CONFIG_S3C_GPIO_TRACK
857 struct samsung_gpio_chip
*s3c_gpios
[S3C_GPIO_END
];
859 static __init
void s3c_gpiolib_track(struct samsung_gpio_chip
*chip
)
864 gpn
= chip
->chip
.base
;
865 for (i
= 0; i
< chip
->chip
.ngpio
; i
++, gpn
++) {
866 BUG_ON(gpn
>= ARRAY_SIZE(s3c_gpios
));
867 s3c_gpios
[gpn
] = chip
;
870 #endif /* CONFIG_S3C_GPIO_TRACK */
873 * samsung_gpiolib_add() - add the Samsung gpio_chip.
874 * @chip: The chip to register
876 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
877 * information and makes the necessary alterations for the platform and
878 * notes the information for use with the configuration systems and any
879 * other parts of the system.
882 static void __init
samsung_gpiolib_add(struct samsung_gpio_chip
*chip
)
884 struct gpio_chip
*gc
= &chip
->chip
;
891 spin_lock_init(&chip
->lock
);
893 if (!gc
->direction_input
)
894 gc
->direction_input
= samsung_gpiolib_2bit_input
;
895 if (!gc
->direction_output
)
896 gc
->direction_output
= samsung_gpiolib_2bit_output
;
898 gc
->set
= samsung_gpiolib_set
;
900 gc
->get
= samsung_gpiolib_get
;
903 if (chip
->pm
!= NULL
) {
904 if (!chip
->pm
->save
|| !chip
->pm
->resume
)
905 printk(KERN_ERR
"gpio: %s has missing PM functions\n",
908 printk(KERN_ERR
"gpio: %s has no PM function\n", gc
->label
);
911 /* gpiochip_add() prints own failure message on error. */
912 ret
= gpiochip_add(gc
);
914 s3c_gpiolib_track(chip
);
917 static void __init
s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip
*chip
,
918 int nr_chips
, void __iomem
*base
)
921 struct gpio_chip
*gc
= &chip
->chip
;
923 for (i
= 0 ; i
< nr_chips
; i
++, chip
++) {
924 /* skip banks not present on SoC */
925 if (chip
->chip
.base
>= S3C_GPIO_END
)
929 chip
->config
= &s3c24xx_gpiocfg_default
;
931 chip
->pm
= __gpio_pm(&samsung_gpio_pm_2bit
);
932 if ((base
!= NULL
) && (chip
->base
== NULL
))
933 chip
->base
= base
+ ((i
) * 0x10);
935 if (!gc
->direction_input
)
936 gc
->direction_input
= samsung_gpiolib_2bit_input
;
937 if (!gc
->direction_output
)
938 gc
->direction_output
= samsung_gpiolib_2bit_output
;
940 samsung_gpiolib_add(chip
);
944 static void __init
samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip
*chip
,
945 int nr_chips
, void __iomem
*base
,
950 for (i
= 0 ; i
< nr_chips
; i
++, chip
++) {
951 chip
->chip
.direction_input
= samsung_gpiolib_2bit_input
;
952 chip
->chip
.direction_output
= samsung_gpiolib_2bit_output
;
955 chip
->config
= &samsung_gpio_cfgs
[7];
957 chip
->pm
= __gpio_pm(&samsung_gpio_pm_2bit
);
958 if ((base
!= NULL
) && (chip
->base
== NULL
))
959 chip
->base
= base
+ ((i
) * offset
);
961 samsung_gpiolib_add(chip
);
966 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
967 * @chip: The gpio chip that is being configured.
968 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
970 * This helper deal with the GPIO cases where the control register has 4 bits
971 * of control per GPIO, generally in the form of:
974 * others = Special functions (dependent on bank)
976 * Note, since the code to deal with the case where there are two control
977 * registers instead of one, we do not have a separate set of function
978 * (samsung_gpiolib_add_4bit2_chips)for each case.
981 static void __init
samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip
*chip
,
982 int nr_chips
, void __iomem
*base
)
986 for (i
= 0 ; i
< nr_chips
; i
++, chip
++) {
987 chip
->chip
.direction_input
= samsung_gpiolib_4bit_input
;
988 chip
->chip
.direction_output
= samsung_gpiolib_4bit_output
;
991 chip
->config
= &samsung_gpio_cfgs
[2];
993 chip
->pm
= __gpio_pm(&samsung_gpio_pm_4bit
);
994 if ((base
!= NULL
) && (chip
->base
== NULL
))
995 chip
->base
= base
+ ((i
) * 0x20);
997 samsung_gpiolib_add(chip
);
1001 static void __init
samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip
*chip
,
1004 for (; nr_chips
> 0; nr_chips
--, chip
++) {
1005 chip
->chip
.direction_input
= samsung_gpiolib_4bit2_input
;
1006 chip
->chip
.direction_output
= samsung_gpiolib_4bit2_output
;
1009 chip
->config
= &samsung_gpio_cfgs
[2];
1011 chip
->pm
= __gpio_pm(&samsung_gpio_pm_4bit
);
1013 samsung_gpiolib_add(chip
);
1017 static void __init
s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip
*chip
,
1020 for (; nr_chips
> 0; nr_chips
--, chip
++) {
1021 chip
->chip
.direction_input
= s5p64x0_gpiolib_rbank_input
;
1022 chip
->chip
.direction_output
= s5p64x0_gpiolib_rbank_output
;
1025 chip
->pm
= __gpio_pm(&samsung_gpio_pm_4bit
);
1027 samsung_gpiolib_add(chip
);
1031 int samsung_gpiolib_to_irq(struct gpio_chip
*chip
, unsigned int offset
)
1033 struct samsung_gpio_chip
*samsung_chip
= container_of(chip
, struct samsung_gpio_chip
, chip
);
1035 return samsung_chip
->irq_base
+ offset
;
1038 #ifdef CONFIG_PLAT_S3C24XX
1039 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip
*chip
, unsigned offset
)
1042 return IRQ_EINT0
+ offset
;
1045 return IRQ_EINT4
+ offset
- 4;
1051 #ifdef CONFIG_PLAT_S3C64XX
1052 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip
*chip
, unsigned pin
)
1054 return pin
< 5 ? IRQ_EINT(23) + pin
: -ENXIO
;
1057 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip
*chip
, unsigned pin
)
1059 return pin
>= 8 ? IRQ_EINT(16) + pin
- 8 : -ENXIO
;
1063 struct samsung_gpio_chip s3c24xx_gpios
[] = {
1064 #ifdef CONFIG_PLAT_S3C24XX
1066 .config
= &s3c24xx_gpiocfg_banka
,
1068 .base
= S3C2410_GPA(0),
1069 .owner
= THIS_MODULE
,
1072 .direction_input
= s3c24xx_gpiolib_banka_input
,
1073 .direction_output
= s3c24xx_gpiolib_banka_output
,
1077 .base
= S3C2410_GPB(0),
1078 .owner
= THIS_MODULE
,
1084 .base
= S3C2410_GPC(0),
1085 .owner
= THIS_MODULE
,
1091 .base
= S3C2410_GPD(0),
1092 .owner
= THIS_MODULE
,
1098 .base
= S3C2410_GPE(0),
1100 .owner
= THIS_MODULE
,
1105 .base
= S3C2410_GPF(0),
1106 .owner
= THIS_MODULE
,
1109 .to_irq
= s3c24xx_gpiolib_fbank_to_irq
,
1112 .irq_base
= IRQ_EINT8
,
1114 .base
= S3C2410_GPG(0),
1115 .owner
= THIS_MODULE
,
1118 .to_irq
= samsung_gpiolib_to_irq
,
1122 .base
= S3C2410_GPH(0),
1123 .owner
= THIS_MODULE
,
1128 /* GPIOS for the S3C2443 and later devices. */
1130 .base
= S3C2440_GPJCON
,
1132 .base
= S3C2410_GPJ(0),
1133 .owner
= THIS_MODULE
,
1138 .base
= S3C2443_GPKCON
,
1140 .base
= S3C2410_GPK(0),
1141 .owner
= THIS_MODULE
,
1146 .base
= S3C2443_GPLCON
,
1148 .base
= S3C2410_GPL(0),
1149 .owner
= THIS_MODULE
,
1154 .base
= S3C2443_GPMCON
,
1156 .base
= S3C2410_GPM(0),
1157 .owner
= THIS_MODULE
,
1166 * GPIO bank summary:
1168 * Bank GPIOs Style SlpCon ExtInt Group
1174 * F 16 2Bit Yes 4 [1]
1176 * H 10 4Bit[2] Yes 6
1177 * I 16 2Bit Yes None
1178 * J 12 2Bit Yes None
1179 * K 16 4Bit[2] No None
1180 * L 15 4Bit[2] No None
1181 * M 6 4Bit No IRQ_EINT
1182 * N 16 2Bit No IRQ_EINT
1187 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1188 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1191 static struct samsung_gpio_chip s3c64xx_gpios_4bit
[] = {
1192 #ifdef CONFIG_PLAT_S3C64XX
1195 .base
= S3C64XX_GPA(0),
1196 .ngpio
= S3C64XX_GPIO_A_NR
,
1201 .base
= S3C64XX_GPB(0),
1202 .ngpio
= S3C64XX_GPIO_B_NR
,
1207 .base
= S3C64XX_GPC(0),
1208 .ngpio
= S3C64XX_GPIO_C_NR
,
1213 .base
= S3C64XX_GPD(0),
1214 .ngpio
= S3C64XX_GPIO_D_NR
,
1218 .config
= &samsung_gpio_cfgs
[0],
1220 .base
= S3C64XX_GPE(0),
1221 .ngpio
= S3C64XX_GPIO_E_NR
,
1225 .base
= S3C64XX_GPG_BASE
,
1227 .base
= S3C64XX_GPG(0),
1228 .ngpio
= S3C64XX_GPIO_G_NR
,
1232 .base
= S3C64XX_GPM_BASE
,
1233 .config
= &samsung_gpio_cfgs
[1],
1235 .base
= S3C64XX_GPM(0),
1236 .ngpio
= S3C64XX_GPIO_M_NR
,
1238 .to_irq
= s3c64xx_gpiolib_mbank_to_irq
,
1244 static struct samsung_gpio_chip s3c64xx_gpios_4bit2
[] = {
1245 #ifdef CONFIG_PLAT_S3C64XX
1247 .base
= S3C64XX_GPH_BASE
+ 0x4,
1249 .base
= S3C64XX_GPH(0),
1250 .ngpio
= S3C64XX_GPIO_H_NR
,
1254 .base
= S3C64XX_GPK_BASE
+ 0x4,
1255 .config
= &samsung_gpio_cfgs
[0],
1257 .base
= S3C64XX_GPK(0),
1258 .ngpio
= S3C64XX_GPIO_K_NR
,
1262 .base
= S3C64XX_GPL_BASE
+ 0x4,
1263 .config
= &samsung_gpio_cfgs
[1],
1265 .base
= S3C64XX_GPL(0),
1266 .ngpio
= S3C64XX_GPIO_L_NR
,
1268 .to_irq
= s3c64xx_gpiolib_lbank_to_irq
,
1274 static struct samsung_gpio_chip s3c64xx_gpios_2bit
[] = {
1275 #ifdef CONFIG_PLAT_S3C64XX
1277 .base
= S3C64XX_GPF_BASE
,
1278 .config
= &samsung_gpio_cfgs
[6],
1280 .base
= S3C64XX_GPF(0),
1281 .ngpio
= S3C64XX_GPIO_F_NR
,
1285 .config
= &samsung_gpio_cfgs
[7],
1287 .base
= S3C64XX_GPI(0),
1288 .ngpio
= S3C64XX_GPIO_I_NR
,
1292 .config
= &samsung_gpio_cfgs
[7],
1294 .base
= S3C64XX_GPJ(0),
1295 .ngpio
= S3C64XX_GPIO_J_NR
,
1299 .config
= &samsung_gpio_cfgs
[6],
1301 .base
= S3C64XX_GPO(0),
1302 .ngpio
= S3C64XX_GPIO_O_NR
,
1306 .config
= &samsung_gpio_cfgs
[6],
1308 .base
= S3C64XX_GPP(0),
1309 .ngpio
= S3C64XX_GPIO_P_NR
,
1313 .config
= &samsung_gpio_cfgs
[6],
1315 .base
= S3C64XX_GPQ(0),
1316 .ngpio
= S3C64XX_GPIO_Q_NR
,
1320 .base
= S3C64XX_GPN_BASE
,
1321 .irq_base
= IRQ_EINT(0),
1322 .config
= &samsung_gpio_cfgs
[5],
1324 .base
= S3C64XX_GPN(0),
1325 .ngpio
= S3C64XX_GPIO_N_NR
,
1327 .to_irq
= samsung_gpiolib_to_irq
,
1334 * S5P6440 GPIO bank summary:
1336 * Bank GPIOs Style SlpCon ExtInt Group
1340 * F 2 2Bit Yes 4 [1]
1342 * H 10 4Bit[2] Yes 6
1343 * I 16 2Bit Yes None
1344 * J 12 2Bit Yes None
1345 * N 16 2Bit No IRQ_EINT
1347 * R 15 4Bit[2] Yes 8
1350 static struct samsung_gpio_chip s5p6440_gpios_4bit
[] = {
1351 #ifdef CONFIG_CPU_S5P6440
1354 .base
= S5P6440_GPA(0),
1355 .ngpio
= S5P6440_GPIO_A_NR
,
1360 .base
= S5P6440_GPB(0),
1361 .ngpio
= S5P6440_GPIO_B_NR
,
1366 .base
= S5P6440_GPC(0),
1367 .ngpio
= S5P6440_GPIO_C_NR
,
1371 .base
= S5P64X0_GPG_BASE
,
1373 .base
= S5P6440_GPG(0),
1374 .ngpio
= S5P6440_GPIO_G_NR
,
1381 static struct samsung_gpio_chip s5p6440_gpios_4bit2
[] = {
1382 #ifdef CONFIG_CPU_S5P6440
1384 .base
= S5P64X0_GPH_BASE
+ 0x4,
1386 .base
= S5P6440_GPH(0),
1387 .ngpio
= S5P6440_GPIO_H_NR
,
1394 static struct samsung_gpio_chip s5p6440_gpios_rbank
[] = {
1395 #ifdef CONFIG_CPU_S5P6440
1397 .base
= S5P64X0_GPR_BASE
+ 0x4,
1398 .config
= &s5p64x0_gpio_cfg_rbank
,
1400 .base
= S5P6440_GPR(0),
1401 .ngpio
= S5P6440_GPIO_R_NR
,
1408 static struct samsung_gpio_chip s5p6440_gpios_2bit
[] = {
1409 #ifdef CONFIG_CPU_S5P6440
1411 .base
= S5P64X0_GPF_BASE
,
1412 .config
= &samsung_gpio_cfgs
[6],
1414 .base
= S5P6440_GPF(0),
1415 .ngpio
= S5P6440_GPIO_F_NR
,
1419 .base
= S5P64X0_GPI_BASE
,
1420 .config
= &samsung_gpio_cfgs
[4],
1422 .base
= S5P6440_GPI(0),
1423 .ngpio
= S5P6440_GPIO_I_NR
,
1427 .base
= S5P64X0_GPJ_BASE
,
1428 .config
= &samsung_gpio_cfgs
[4],
1430 .base
= S5P6440_GPJ(0),
1431 .ngpio
= S5P6440_GPIO_J_NR
,
1435 .base
= S5P64X0_GPN_BASE
,
1436 .config
= &samsung_gpio_cfgs
[5],
1438 .base
= S5P6440_GPN(0),
1439 .ngpio
= S5P6440_GPIO_N_NR
,
1443 .base
= S5P64X0_GPP_BASE
,
1444 .config
= &samsung_gpio_cfgs
[6],
1446 .base
= S5P6440_GPP(0),
1447 .ngpio
= S5P6440_GPIO_P_NR
,
1455 * S5P6450 GPIO bank summary:
1457 * Bank GPIOs Style SlpCon ExtInt Group
1463 * G 14 4Bit[2] Yes 5
1464 * H 10 4Bit[2] Yes 6
1465 * I 16 2Bit Yes None
1466 * J 12 2Bit Yes None
1468 * N 16 2Bit No IRQ_EINT
1470 * Q 14 2Bit Yes None
1471 * R 15 4Bit[2] Yes None
1474 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1475 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1478 static struct samsung_gpio_chip s5p6450_gpios_4bit
[] = {
1479 #ifdef CONFIG_CPU_S5P6450
1482 .base
= S5P6450_GPA(0),
1483 .ngpio
= S5P6450_GPIO_A_NR
,
1488 .base
= S5P6450_GPB(0),
1489 .ngpio
= S5P6450_GPIO_B_NR
,
1494 .base
= S5P6450_GPC(0),
1495 .ngpio
= S5P6450_GPIO_C_NR
,
1500 .base
= S5P6450_GPD(0),
1501 .ngpio
= S5P6450_GPIO_D_NR
,
1505 .base
= S5P6450_GPK_BASE
,
1507 .base
= S5P6450_GPK(0),
1508 .ngpio
= S5P6450_GPIO_K_NR
,
1515 static struct samsung_gpio_chip s5p6450_gpios_4bit2
[] = {
1516 #ifdef CONFIG_CPU_S5P6450
1518 .base
= S5P64X0_GPG_BASE
+ 0x4,
1520 .base
= S5P6450_GPG(0),
1521 .ngpio
= S5P6450_GPIO_G_NR
,
1525 .base
= S5P64X0_GPH_BASE
+ 0x4,
1527 .base
= S5P6450_GPH(0),
1528 .ngpio
= S5P6450_GPIO_H_NR
,
1535 static struct samsung_gpio_chip s5p6450_gpios_rbank
[] = {
1536 #ifdef CONFIG_CPU_S5P6450
1538 .base
= S5P64X0_GPR_BASE
+ 0x4,
1539 .config
= &s5p64x0_gpio_cfg_rbank
,
1541 .base
= S5P6450_GPR(0),
1542 .ngpio
= S5P6450_GPIO_R_NR
,
1549 static struct samsung_gpio_chip s5p6450_gpios_2bit
[] = {
1550 #ifdef CONFIG_CPU_S5P6450
1552 .base
= S5P64X0_GPF_BASE
,
1553 .config
= &samsung_gpio_cfgs
[6],
1555 .base
= S5P6450_GPF(0),
1556 .ngpio
= S5P6450_GPIO_F_NR
,
1560 .base
= S5P64X0_GPI_BASE
,
1561 .config
= &samsung_gpio_cfgs
[4],
1563 .base
= S5P6450_GPI(0),
1564 .ngpio
= S5P6450_GPIO_I_NR
,
1568 .base
= S5P64X0_GPJ_BASE
,
1569 .config
= &samsung_gpio_cfgs
[4],
1571 .base
= S5P6450_GPJ(0),
1572 .ngpio
= S5P6450_GPIO_J_NR
,
1576 .base
= S5P64X0_GPN_BASE
,
1577 .config
= &samsung_gpio_cfgs
[5],
1579 .base
= S5P6450_GPN(0),
1580 .ngpio
= S5P6450_GPIO_N_NR
,
1584 .base
= S5P64X0_GPP_BASE
,
1585 .config
= &samsung_gpio_cfgs
[6],
1587 .base
= S5P6450_GPP(0),
1588 .ngpio
= S5P6450_GPIO_P_NR
,
1592 .base
= S5P6450_GPQ_BASE
,
1593 .config
= &samsung_gpio_cfgs
[5],
1595 .base
= S5P6450_GPQ(0),
1596 .ngpio
= S5P6450_GPIO_Q_NR
,
1600 .base
= S5P6450_GPS_BASE
,
1601 .config
= &samsung_gpio_cfgs
[6],
1603 .base
= S5P6450_GPS(0),
1604 .ngpio
= S5P6450_GPIO_S_NR
,
1612 * S5PC100 GPIO bank summary:
1614 * Bank GPIOs Style INT Type
1615 * A0 8 4Bit GPIO_INT0
1616 * A1 5 4Bit GPIO_INT1
1617 * B 8 4Bit GPIO_INT2
1618 * C 5 4Bit GPIO_INT3
1619 * D 7 4Bit GPIO_INT4
1620 * E0 8 4Bit GPIO_INT5
1621 * E1 6 4Bit GPIO_INT6
1622 * F0 8 4Bit GPIO_INT7
1623 * F1 8 4Bit GPIO_INT8
1624 * F2 8 4Bit GPIO_INT9
1625 * F3 4 4Bit GPIO_INT10
1626 * G0 8 4Bit GPIO_INT11
1627 * G1 3 4Bit GPIO_INT12
1628 * G2 7 4Bit GPIO_INT13
1629 * G3 7 4Bit GPIO_INT14
1630 * H0 8 4Bit WKUP_INT
1631 * H1 8 4Bit WKUP_INT
1632 * H2 8 4Bit WKUP_INT
1633 * H3 8 4Bit WKUP_INT
1634 * I 8 4Bit GPIO_INT15
1635 * J0 8 4Bit GPIO_INT16
1636 * J1 5 4Bit GPIO_INT17
1637 * J2 8 4Bit GPIO_INT18
1638 * J3 8 4Bit GPIO_INT19
1639 * J4 4 4Bit GPIO_INT20
1650 static struct samsung_gpio_chip s5pc100_gpios_4bit
[] = {
1651 #ifdef CONFIG_CPU_S5PC100
1654 .base
= S5PC100_GPA0(0),
1655 .ngpio
= S5PC100_GPIO_A0_NR
,
1660 .base
= S5PC100_GPA1(0),
1661 .ngpio
= S5PC100_GPIO_A1_NR
,
1666 .base
= S5PC100_GPB(0),
1667 .ngpio
= S5PC100_GPIO_B_NR
,
1672 .base
= S5PC100_GPC(0),
1673 .ngpio
= S5PC100_GPIO_C_NR
,
1678 .base
= S5PC100_GPD(0),
1679 .ngpio
= S5PC100_GPIO_D_NR
,
1684 .base
= S5PC100_GPE0(0),
1685 .ngpio
= S5PC100_GPIO_E0_NR
,
1690 .base
= S5PC100_GPE1(0),
1691 .ngpio
= S5PC100_GPIO_E1_NR
,
1696 .base
= S5PC100_GPF0(0),
1697 .ngpio
= S5PC100_GPIO_F0_NR
,
1702 .base
= S5PC100_GPF1(0),
1703 .ngpio
= S5PC100_GPIO_F1_NR
,
1708 .base
= S5PC100_GPF2(0),
1709 .ngpio
= S5PC100_GPIO_F2_NR
,
1714 .base
= S5PC100_GPF3(0),
1715 .ngpio
= S5PC100_GPIO_F3_NR
,
1720 .base
= S5PC100_GPG0(0),
1721 .ngpio
= S5PC100_GPIO_G0_NR
,
1726 .base
= S5PC100_GPG1(0),
1727 .ngpio
= S5PC100_GPIO_G1_NR
,
1732 .base
= S5PC100_GPG2(0),
1733 .ngpio
= S5PC100_GPIO_G2_NR
,
1738 .base
= S5PC100_GPG3(0),
1739 .ngpio
= S5PC100_GPIO_G3_NR
,
1744 .base
= S5PC100_GPI(0),
1745 .ngpio
= S5PC100_GPIO_I_NR
,
1750 .base
= S5PC100_GPJ0(0),
1751 .ngpio
= S5PC100_GPIO_J0_NR
,
1756 .base
= S5PC100_GPJ1(0),
1757 .ngpio
= S5PC100_GPIO_J1_NR
,
1762 .base
= S5PC100_GPJ2(0),
1763 .ngpio
= S5PC100_GPIO_J2_NR
,
1768 .base
= S5PC100_GPJ3(0),
1769 .ngpio
= S5PC100_GPIO_J3_NR
,
1774 .base
= S5PC100_GPJ4(0),
1775 .ngpio
= S5PC100_GPIO_J4_NR
,
1780 .base
= S5PC100_GPK0(0),
1781 .ngpio
= S5PC100_GPIO_K0_NR
,
1786 .base
= S5PC100_GPK1(0),
1787 .ngpio
= S5PC100_GPIO_K1_NR
,
1792 .base
= S5PC100_GPK2(0),
1793 .ngpio
= S5PC100_GPIO_K2_NR
,
1798 .base
= S5PC100_GPK3(0),
1799 .ngpio
= S5PC100_GPIO_K3_NR
,
1804 .base
= S5PC100_GPL0(0),
1805 .ngpio
= S5PC100_GPIO_L0_NR
,
1810 .base
= S5PC100_GPL1(0),
1811 .ngpio
= S5PC100_GPIO_L1_NR
,
1816 .base
= S5PC100_GPL2(0),
1817 .ngpio
= S5PC100_GPIO_L2_NR
,
1822 .base
= S5PC100_GPL3(0),
1823 .ngpio
= S5PC100_GPIO_L3_NR
,
1828 .base
= S5PC100_GPL4(0),
1829 .ngpio
= S5PC100_GPIO_L4_NR
,
1833 .base
= (S5P_VA_GPIO
+ 0xC00),
1834 .irq_base
= IRQ_EINT(0),
1836 .base
= S5PC100_GPH0(0),
1837 .ngpio
= S5PC100_GPIO_H0_NR
,
1839 .to_irq
= samsung_gpiolib_to_irq
,
1842 .base
= (S5P_VA_GPIO
+ 0xC20),
1843 .irq_base
= IRQ_EINT(8),
1845 .base
= S5PC100_GPH1(0),
1846 .ngpio
= S5PC100_GPIO_H1_NR
,
1848 .to_irq
= samsung_gpiolib_to_irq
,
1851 .base
= (S5P_VA_GPIO
+ 0xC40),
1852 .irq_base
= IRQ_EINT(16),
1854 .base
= S5PC100_GPH2(0),
1855 .ngpio
= S5PC100_GPIO_H2_NR
,
1857 .to_irq
= samsung_gpiolib_to_irq
,
1860 .base
= (S5P_VA_GPIO
+ 0xC60),
1861 .irq_base
= IRQ_EINT(24),
1863 .base
= S5PC100_GPH3(0),
1864 .ngpio
= S5PC100_GPIO_H3_NR
,
1866 .to_irq
= samsung_gpiolib_to_irq
,
1873 * Followings are the gpio banks in S5PV210/S5PC110
1875 * The 'config' member when left to NULL, is initialized to the default
1876 * structure samsung_gpio_cfgs[3] in the init function below.
1878 * The 'base' member is also initialized in the init function below.
1879 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1880 * uses the above macro and depends on the banks being listed in order here.
1883 static struct samsung_gpio_chip s5pv210_gpios_4bit
[] = {
1884 #ifdef CONFIG_CPU_S5PV210
1887 .base
= S5PV210_GPA0(0),
1888 .ngpio
= S5PV210_GPIO_A0_NR
,
1893 .base
= S5PV210_GPA1(0),
1894 .ngpio
= S5PV210_GPIO_A1_NR
,
1899 .base
= S5PV210_GPB(0),
1900 .ngpio
= S5PV210_GPIO_B_NR
,
1905 .base
= S5PV210_GPC0(0),
1906 .ngpio
= S5PV210_GPIO_C0_NR
,
1911 .base
= S5PV210_GPC1(0),
1912 .ngpio
= S5PV210_GPIO_C1_NR
,
1917 .base
= S5PV210_GPD0(0),
1918 .ngpio
= S5PV210_GPIO_D0_NR
,
1923 .base
= S5PV210_GPD1(0),
1924 .ngpio
= S5PV210_GPIO_D1_NR
,
1929 .base
= S5PV210_GPE0(0),
1930 .ngpio
= S5PV210_GPIO_E0_NR
,
1935 .base
= S5PV210_GPE1(0),
1936 .ngpio
= S5PV210_GPIO_E1_NR
,
1941 .base
= S5PV210_GPF0(0),
1942 .ngpio
= S5PV210_GPIO_F0_NR
,
1947 .base
= S5PV210_GPF1(0),
1948 .ngpio
= S5PV210_GPIO_F1_NR
,
1953 .base
= S5PV210_GPF2(0),
1954 .ngpio
= S5PV210_GPIO_F2_NR
,
1959 .base
= S5PV210_GPF3(0),
1960 .ngpio
= S5PV210_GPIO_F3_NR
,
1965 .base
= S5PV210_GPG0(0),
1966 .ngpio
= S5PV210_GPIO_G0_NR
,
1971 .base
= S5PV210_GPG1(0),
1972 .ngpio
= S5PV210_GPIO_G1_NR
,
1977 .base
= S5PV210_GPG2(0),
1978 .ngpio
= S5PV210_GPIO_G2_NR
,
1983 .base
= S5PV210_GPG3(0),
1984 .ngpio
= S5PV210_GPIO_G3_NR
,
1989 .base
= S5PV210_GPI(0),
1990 .ngpio
= S5PV210_GPIO_I_NR
,
1995 .base
= S5PV210_GPJ0(0),
1996 .ngpio
= S5PV210_GPIO_J0_NR
,
2001 .base
= S5PV210_GPJ1(0),
2002 .ngpio
= S5PV210_GPIO_J1_NR
,
2007 .base
= S5PV210_GPJ2(0),
2008 .ngpio
= S5PV210_GPIO_J2_NR
,
2013 .base
= S5PV210_GPJ3(0),
2014 .ngpio
= S5PV210_GPIO_J3_NR
,
2019 .base
= S5PV210_GPJ4(0),
2020 .ngpio
= S5PV210_GPIO_J4_NR
,
2025 .base
= S5PV210_MP01(0),
2026 .ngpio
= S5PV210_GPIO_MP01_NR
,
2031 .base
= S5PV210_MP02(0),
2032 .ngpio
= S5PV210_GPIO_MP02_NR
,
2037 .base
= S5PV210_MP03(0),
2038 .ngpio
= S5PV210_GPIO_MP03_NR
,
2043 .base
= S5PV210_MP04(0),
2044 .ngpio
= S5PV210_GPIO_MP04_NR
,
2049 .base
= S5PV210_MP05(0),
2050 .ngpio
= S5PV210_GPIO_MP05_NR
,
2054 .base
= (S5P_VA_GPIO
+ 0xC00),
2055 .irq_base
= IRQ_EINT(0),
2057 .base
= S5PV210_GPH0(0),
2058 .ngpio
= S5PV210_GPIO_H0_NR
,
2060 .to_irq
= samsung_gpiolib_to_irq
,
2063 .base
= (S5P_VA_GPIO
+ 0xC20),
2064 .irq_base
= IRQ_EINT(8),
2066 .base
= S5PV210_GPH1(0),
2067 .ngpio
= S5PV210_GPIO_H1_NR
,
2069 .to_irq
= samsung_gpiolib_to_irq
,
2072 .base
= (S5P_VA_GPIO
+ 0xC40),
2073 .irq_base
= IRQ_EINT(16),
2075 .base
= S5PV210_GPH2(0),
2076 .ngpio
= S5PV210_GPIO_H2_NR
,
2078 .to_irq
= samsung_gpiolib_to_irq
,
2081 .base
= (S5P_VA_GPIO
+ 0xC60),
2082 .irq_base
= IRQ_EINT(24),
2084 .base
= S5PV210_GPH3(0),
2085 .ngpio
= S5PV210_GPIO_H3_NR
,
2087 .to_irq
= samsung_gpiolib_to_irq
,
2094 * Followings are the gpio banks in EXYNOS4210
2096 * The 'config' member when left to NULL, is initialized to the default
2097 * structure samsung_gpio_cfgs[3] in the init function below.
2099 * The 'base' member is also initialized in the init function below.
2100 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2101 * uses the above macro and depends on the banks being listed in order here.
2104 static struct samsung_gpio_chip exynos4_gpios_1
[] = {
2105 #ifdef CONFIG_ARCH_EXYNOS4
2108 .base
= EXYNOS4_GPA0(0),
2109 .ngpio
= EXYNOS4_GPIO_A0_NR
,
2114 .base
= EXYNOS4_GPA1(0),
2115 .ngpio
= EXYNOS4_GPIO_A1_NR
,
2120 .base
= EXYNOS4_GPB(0),
2121 .ngpio
= EXYNOS4_GPIO_B_NR
,
2126 .base
= EXYNOS4_GPC0(0),
2127 .ngpio
= EXYNOS4_GPIO_C0_NR
,
2132 .base
= EXYNOS4_GPC1(0),
2133 .ngpio
= EXYNOS4_GPIO_C1_NR
,
2138 .base
= EXYNOS4_GPD0(0),
2139 .ngpio
= EXYNOS4_GPIO_D0_NR
,
2144 .base
= EXYNOS4_GPD1(0),
2145 .ngpio
= EXYNOS4_GPIO_D1_NR
,
2150 .base
= EXYNOS4_GPE0(0),
2151 .ngpio
= EXYNOS4_GPIO_E0_NR
,
2156 .base
= EXYNOS4_GPE1(0),
2157 .ngpio
= EXYNOS4_GPIO_E1_NR
,
2162 .base
= EXYNOS4_GPE2(0),
2163 .ngpio
= EXYNOS4_GPIO_E2_NR
,
2168 .base
= EXYNOS4_GPE3(0),
2169 .ngpio
= EXYNOS4_GPIO_E3_NR
,
2174 .base
= EXYNOS4_GPE4(0),
2175 .ngpio
= EXYNOS4_GPIO_E4_NR
,
2180 .base
= EXYNOS4_GPF0(0),
2181 .ngpio
= EXYNOS4_GPIO_F0_NR
,
2186 .base
= EXYNOS4_GPF1(0),
2187 .ngpio
= EXYNOS4_GPIO_F1_NR
,
2192 .base
= EXYNOS4_GPF2(0),
2193 .ngpio
= EXYNOS4_GPIO_F2_NR
,
2198 .base
= EXYNOS4_GPF3(0),
2199 .ngpio
= EXYNOS4_GPIO_F3_NR
,
2206 static struct samsung_gpio_chip exynos4_gpios_2
[] = {
2207 #ifdef CONFIG_ARCH_EXYNOS4
2210 .base
= EXYNOS4_GPJ0(0),
2211 .ngpio
= EXYNOS4_GPIO_J0_NR
,
2216 .base
= EXYNOS4_GPJ1(0),
2217 .ngpio
= EXYNOS4_GPIO_J1_NR
,
2222 .base
= EXYNOS4_GPK0(0),
2223 .ngpio
= EXYNOS4_GPIO_K0_NR
,
2228 .base
= EXYNOS4_GPK1(0),
2229 .ngpio
= EXYNOS4_GPIO_K1_NR
,
2234 .base
= EXYNOS4_GPK2(0),
2235 .ngpio
= EXYNOS4_GPIO_K2_NR
,
2240 .base
= EXYNOS4_GPK3(0),
2241 .ngpio
= EXYNOS4_GPIO_K3_NR
,
2246 .base
= EXYNOS4_GPL0(0),
2247 .ngpio
= EXYNOS4_GPIO_L0_NR
,
2252 .base
= EXYNOS4_GPL1(0),
2253 .ngpio
= EXYNOS4_GPIO_L1_NR
,
2258 .base
= EXYNOS4_GPL2(0),
2259 .ngpio
= EXYNOS4_GPIO_L2_NR
,
2263 .config
= &samsung_gpio_cfgs
[8],
2265 .base
= EXYNOS4_GPY0(0),
2266 .ngpio
= EXYNOS4_GPIO_Y0_NR
,
2270 .config
= &samsung_gpio_cfgs
[8],
2272 .base
= EXYNOS4_GPY1(0),
2273 .ngpio
= EXYNOS4_GPIO_Y1_NR
,
2277 .config
= &samsung_gpio_cfgs
[8],
2279 .base
= EXYNOS4_GPY2(0),
2280 .ngpio
= EXYNOS4_GPIO_Y2_NR
,
2284 .config
= &samsung_gpio_cfgs
[8],
2286 .base
= EXYNOS4_GPY3(0),
2287 .ngpio
= EXYNOS4_GPIO_Y3_NR
,
2291 .config
= &samsung_gpio_cfgs
[8],
2293 .base
= EXYNOS4_GPY4(0),
2294 .ngpio
= EXYNOS4_GPIO_Y4_NR
,
2298 .config
= &samsung_gpio_cfgs
[8],
2300 .base
= EXYNOS4_GPY5(0),
2301 .ngpio
= EXYNOS4_GPIO_Y5_NR
,
2305 .config
= &samsung_gpio_cfgs
[8],
2307 .base
= EXYNOS4_GPY6(0),
2308 .ngpio
= EXYNOS4_GPIO_Y6_NR
,
2312 .base
= (S5P_VA_GPIO2
+ 0xC00),
2313 .config
= &samsung_gpio_cfgs
[9],
2314 .irq_base
= IRQ_EINT(0),
2316 .base
= EXYNOS4_GPX0(0),
2317 .ngpio
= EXYNOS4_GPIO_X0_NR
,
2319 .to_irq
= samsung_gpiolib_to_irq
,
2322 .base
= (S5P_VA_GPIO2
+ 0xC20),
2323 .config
= &samsung_gpio_cfgs
[9],
2324 .irq_base
= IRQ_EINT(8),
2326 .base
= EXYNOS4_GPX1(0),
2327 .ngpio
= EXYNOS4_GPIO_X1_NR
,
2329 .to_irq
= samsung_gpiolib_to_irq
,
2332 .base
= (S5P_VA_GPIO2
+ 0xC40),
2333 .config
= &samsung_gpio_cfgs
[9],
2334 .irq_base
= IRQ_EINT(16),
2336 .base
= EXYNOS4_GPX2(0),
2337 .ngpio
= EXYNOS4_GPIO_X2_NR
,
2339 .to_irq
= samsung_gpiolib_to_irq
,
2342 .base
= (S5P_VA_GPIO2
+ 0xC60),
2343 .config
= &samsung_gpio_cfgs
[9],
2344 .irq_base
= IRQ_EINT(24),
2346 .base
= EXYNOS4_GPX3(0),
2347 .ngpio
= EXYNOS4_GPIO_X3_NR
,
2349 .to_irq
= samsung_gpiolib_to_irq
,
2355 static struct samsung_gpio_chip exynos4_gpios_3
[] = {
2356 #ifdef CONFIG_ARCH_EXYNOS4
2359 .base
= EXYNOS4_GPZ(0),
2360 .ngpio
= EXYNOS4_GPIO_Z_NR
,
2367 /* TODO: cleanup soc_is_* */
2368 static __init
int samsung_gpiolib_init(void)
2370 struct samsung_gpio_chip
*chip
;
2374 samsung_gpiolib_set_cfg(samsung_gpio_cfgs
, ARRAY_SIZE(samsung_gpio_cfgs
));
2376 if (soc_is_s3c24xx()) {
2377 s3c24xx_gpiolib_add_chips(s3c24xx_gpios
,
2378 ARRAY_SIZE(s3c24xx_gpios
), S3C24XX_VA_GPIO
);
2379 } else if (soc_is_s3c64xx()) {
2380 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit
,
2381 ARRAY_SIZE(s3c64xx_gpios_2bit
),
2382 S3C64XX_VA_GPIO
+ 0xE0, 0x20);
2383 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit
,
2384 ARRAY_SIZE(s3c64xx_gpios_4bit
),
2386 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2
,
2387 ARRAY_SIZE(s3c64xx_gpios_4bit2
));
2388 } else if (soc_is_s5p6440()) {
2389 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit
,
2390 ARRAY_SIZE(s5p6440_gpios_2bit
), NULL
, 0x0);
2391 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit
,
2392 ARRAY_SIZE(s5p6440_gpios_4bit
), S5P_VA_GPIO
);
2393 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2
,
2394 ARRAY_SIZE(s5p6440_gpios_4bit2
));
2395 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank
,
2396 ARRAY_SIZE(s5p6440_gpios_rbank
));
2397 } else if (soc_is_s5p6450()) {
2398 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit
,
2399 ARRAY_SIZE(s5p6450_gpios_2bit
), NULL
, 0x0);
2400 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit
,
2401 ARRAY_SIZE(s5p6450_gpios_4bit
), S5P_VA_GPIO
);
2402 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2
,
2403 ARRAY_SIZE(s5p6450_gpios_4bit2
));
2404 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank
,
2405 ARRAY_SIZE(s5p6450_gpios_rbank
));
2406 } else if (soc_is_s5pc100()) {
2408 chip
= s5pc100_gpios_4bit
;
2409 nr_chips
= ARRAY_SIZE(s5pc100_gpios_4bit
);
2411 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2412 if (!chip
->config
) {
2413 chip
->config
= &samsung_gpio_cfgs
[3];
2414 chip
->group
= group
++;
2417 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit
, nr_chips
, S5P_VA_GPIO
);
2418 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2419 s5p_register_gpioint_bank(IRQ_GPIOINT
, 0, S5P_GPIOINT_GROUP_MAXNR
);
2421 } else if (soc_is_s5pv210()) {
2423 chip
= s5pv210_gpios_4bit
;
2424 nr_chips
= ARRAY_SIZE(s5pv210_gpios_4bit
);
2426 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2427 if (!chip
->config
) {
2428 chip
->config
= &samsung_gpio_cfgs
[3];
2429 chip
->group
= group
++;
2432 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit
, nr_chips
, S5P_VA_GPIO
);
2433 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2434 s5p_register_gpioint_bank(IRQ_GPIOINT
, 0, S5P_GPIOINT_GROUP_MAXNR
);
2436 } else if (soc_is_exynos4210()) {
2440 chip
= exynos4_gpios_1
;
2441 nr_chips
= ARRAY_SIZE(exynos4_gpios_1
);
2443 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2444 if (!chip
->config
) {
2445 chip
->config
= &exynos4_gpio_cfg
;
2446 chip
->group
= group
++;
2449 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1
, nr_chips
, S5P_VA_GPIO1
);
2452 chip
= exynos4_gpios_2
;
2453 nr_chips
= ARRAY_SIZE(exynos4_gpios_2
);
2455 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2456 if (!chip
->config
) {
2457 chip
->config
= &exynos4_gpio_cfg
;
2458 chip
->group
= group
++;
2461 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2
, nr_chips
, S5P_VA_GPIO2
);
2464 chip
= exynos4_gpios_3
;
2465 nr_chips
= ARRAY_SIZE(exynos4_gpios_3
);
2467 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2468 if (!chip
->config
) {
2469 chip
->config
= &exynos4_gpio_cfg
;
2470 chip
->group
= group
++;
2473 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3
, nr_chips
, S5P_VA_GPIO3
);
2475 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2476 s5p_register_gpioint_bank(IRQ_GPIO_XA
, 0, IRQ_GPIO1_NR_GROUPS
);
2477 s5p_register_gpioint_bank(IRQ_GPIO_XB
, IRQ_GPIO1_NR_GROUPS
, IRQ_GPIO2_NR_GROUPS
);
2483 core_initcall(samsung_gpiolib_init
);
2485 int s3c_gpio_cfgpin(unsigned int pin
, unsigned int config
)
2487 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2488 unsigned long flags
;
2495 offset
= pin
- chip
->chip
.base
;
2497 samsung_gpio_lock(chip
, flags
);
2498 ret
= samsung_gpio_do_setcfg(chip
, offset
, config
);
2499 samsung_gpio_unlock(chip
, flags
);
2503 EXPORT_SYMBOL(s3c_gpio_cfgpin
);
2505 int s3c_gpio_cfgpin_range(unsigned int start
, unsigned int nr
,
2510 for (; nr
> 0; nr
--, start
++) {
2511 ret
= s3c_gpio_cfgpin(start
, cfg
);
2518 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range
);
2520 int s3c_gpio_cfgall_range(unsigned int start
, unsigned int nr
,
2521 unsigned int cfg
, samsung_gpio_pull_t pull
)
2525 for (; nr
> 0; nr
--, start
++) {
2526 s3c_gpio_setpull(start
, pull
);
2527 ret
= s3c_gpio_cfgpin(start
, cfg
);
2534 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range
);
2536 unsigned s3c_gpio_getcfg(unsigned int pin
)
2538 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2539 unsigned long flags
;
2544 offset
= pin
- chip
->chip
.base
;
2546 samsung_gpio_lock(chip
, flags
);
2547 ret
= samsung_gpio_do_getcfg(chip
, offset
);
2548 samsung_gpio_unlock(chip
, flags
);
2553 EXPORT_SYMBOL(s3c_gpio_getcfg
);
2555 int s3c_gpio_setpull(unsigned int pin
, samsung_gpio_pull_t pull
)
2557 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2558 unsigned long flags
;
2564 offset
= pin
- chip
->chip
.base
;
2566 samsung_gpio_lock(chip
, flags
);
2567 ret
= samsung_gpio_do_setpull(chip
, offset
, pull
);
2568 samsung_gpio_unlock(chip
, flags
);
2572 EXPORT_SYMBOL(s3c_gpio_setpull
);
2574 samsung_gpio_pull_t
s3c_gpio_getpull(unsigned int pin
)
2576 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2577 unsigned long flags
;
2582 offset
= pin
- chip
->chip
.base
;
2584 samsung_gpio_lock(chip
, flags
);
2585 pup
= samsung_gpio_do_getpull(chip
, offset
);
2586 samsung_gpio_unlock(chip
, flags
);
2589 return (__force samsung_gpio_pull_t
)pup
;
2591 EXPORT_SYMBOL(s3c_gpio_getpull
);
2593 /* gpiolib wrappers until these are totally eliminated */
2595 void s3c2410_gpio_pullup(unsigned int pin
, unsigned int to
)
2599 WARN_ON(to
); /* should be none of these left */
2602 /* if pull is enabled, try first with up, and if that
2603 * fails, try using down */
2605 ret
= s3c_gpio_setpull(pin
, S3C_GPIO_PULL_UP
);
2607 s3c_gpio_setpull(pin
, S3C_GPIO_PULL_DOWN
);
2609 s3c_gpio_setpull(pin
, S3C_GPIO_PULL_NONE
);
2612 EXPORT_SYMBOL(s3c2410_gpio_pullup
);
2614 void s3c2410_gpio_setpin(unsigned int pin
, unsigned int to
)
2616 /* do this via gpiolib until all users removed */
2618 gpio_request(pin
, "temporary");
2619 gpio_set_value(pin
, to
);
2622 EXPORT_SYMBOL(s3c2410_gpio_setpin
);
2624 unsigned int s3c2410_gpio_getpin(unsigned int pin
)
2626 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2627 unsigned long offs
= pin
- chip
->chip
.base
;
2629 return __raw_readl(chip
->base
+ 0x04) & (1 << offs
);
2631 EXPORT_SYMBOL(s3c2410_gpio_getpin
);
2633 #ifdef CONFIG_S5P_GPIO_DRVSTR
2634 s5p_gpio_drvstr_t
s5p_gpio_get_drvstr(unsigned int pin
)
2636 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2645 off
= pin
- chip
->chip
.base
;
2647 reg
= chip
->base
+ 0x0C;
2649 drvstr
= __raw_readl(reg
);
2650 drvstr
= drvstr
>> shift
;
2653 return (__force s5p_gpio_drvstr_t
)drvstr
;
2655 EXPORT_SYMBOL(s5p_gpio_get_drvstr
);
2657 int s5p_gpio_set_drvstr(unsigned int pin
, s5p_gpio_drvstr_t drvstr
)
2659 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2668 off
= pin
- chip
->chip
.base
;
2670 reg
= chip
->base
+ 0x0C;
2672 tmp
= __raw_readl(reg
);
2673 tmp
&= ~(0x3 << shift
);
2674 tmp
|= drvstr
<< shift
;
2676 __raw_writel(tmp
, reg
);
2680 EXPORT_SYMBOL(s5p_gpio_set_drvstr
);
2681 #endif /* CONFIG_S5P_GPIO_DRVSTR */
2683 #ifdef CONFIG_PLAT_S3C24XX
2684 unsigned int s3c2410_modify_misccr(unsigned int clear
, unsigned int change
)
2686 unsigned long flags
;
2687 unsigned long misccr
;
2689 local_irq_save(flags
);
2690 misccr
= __raw_readl(S3C24XX_MISCCR
);
2693 __raw_writel(misccr
, S3C24XX_MISCCR
);
2694 local_irq_restore(flags
);
2698 EXPORT_SYMBOL(s3c2410_modify_misccr
);