1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012 John Crispin <john@phrozen.org>
7 #include <linux/slab.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/types.h>
11 #include <linux/of_platform.h>
12 #include <linux/mutex.h>
13 #include <linux/gpio/driver.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
19 * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
20 * peripheral controller used to drive external shift register cascades. At most
21 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
22 * to drive the 2 LSBs of the cascade automatically.
25 /* control register 0 */
26 #define XWAY_STP_CON0 0x00
27 /* control register 1 */
28 #define XWAY_STP_CON1 0x04
30 #define XWAY_STP_CPU0 0x08
32 #define XWAY_STP_CPU1 0x0C
34 #define XWAY_STP_AR 0x10
36 /* software or hardware update select bit */
37 #define XWAY_STP_CON_SWU BIT(31)
39 /* automatic update rates */
40 #define XWAY_STP_2HZ 0
41 #define XWAY_STP_4HZ BIT(23)
42 #define XWAY_STP_8HZ BIT(24)
43 #define XWAY_STP_10HZ (BIT(24) | BIT(23))
44 #define XWAY_STP_SPEED_MASK (BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
46 #define XWAY_STP_FPIS_VALUE BIT(21)
47 #define XWAY_STP_FPIS_MASK (BIT(20) | BIT(21))
49 /* clock source for automatic update */
50 #define XWAY_STP_UPD_FPI BIT(31)
51 #define XWAY_STP_UPD_MASK (BIT(31) | BIT(30))
53 /* let the adsl core drive the 2 LSBs */
54 #define XWAY_STP_ADSL_SHIFT 24
55 #define XWAY_STP_ADSL_MASK 0x3
57 /* 2 groups of 3 bits can be driven by the phys */
58 #define XWAY_STP_PHY_MASK 0x7
59 #define XWAY_STP_PHY1_SHIFT 27
60 #define XWAY_STP_PHY2_SHIFT 3
61 #define XWAY_STP_PHY3_SHIFT 6
62 #define XWAY_STP_PHY4_SHIFT 15
64 /* STP has 3 groups of 8 bits */
65 #define XWAY_STP_GROUP0 BIT(0)
66 #define XWAY_STP_GROUP1 BIT(1)
67 #define XWAY_STP_GROUP2 BIT(2)
68 #define XWAY_STP_GROUP_MASK (0x7)
70 /* Edge configuration bits */
71 #define XWAY_STP_FALLING BIT(26)
72 #define XWAY_STP_EDGE_MASK BIT(26)
74 #define xway_stp_r32(m, reg) __raw_readl(m + reg)
75 #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
76 #define xway_stp_w32_mask(m, clear, set, reg) \
77 xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
82 u32 edge
; /* rising or falling edge triggered shift register */
83 u32 shadow
; /* shadow the shift registers state */
84 u8 groups
; /* we can drive 1-3 groups of 8bit each */
85 u8 dsl
; /* the 2 LSBs can be driven by the dsl core */
86 u8 phy1
; /* 3 bits can be driven by phy1 */
87 u8 phy2
; /* 3 bits can be driven by phy2 */
88 u8 phy3
; /* 3 bits can be driven by phy3 */
89 u8 phy4
; /* 3 bits can be driven by phy4 */
90 u8 reserved
; /* mask out the hw driven bits in gpio_request */
94 * xway_stp_get() - gpio_chip->get - get gpios.
95 * @gc: Pointer to gpio_chip device structure.
96 * @gpio: GPIO signal number.
98 * Gets the shadow value.
100 static int xway_stp_get(struct gpio_chip
*gc
, unsigned int gpio
)
102 struct xway_stp
*chip
= gpiochip_get_data(gc
);
104 return (xway_stp_r32(chip
->virt
, XWAY_STP_CPU0
) & BIT(gpio
));
108 * xway_stp_set() - gpio_chip->set - set gpios.
109 * @gc: Pointer to gpio_chip device structure.
110 * @gpio: GPIO signal number.
111 * @val: Value to be written to specified signal.
113 * Set the shadow value and call ltq_ebu_apply.
115 static void xway_stp_set(struct gpio_chip
*gc
, unsigned gpio
, int val
)
117 struct xway_stp
*chip
= gpiochip_get_data(gc
);
120 chip
->shadow
|= BIT(gpio
);
122 chip
->shadow
&= ~BIT(gpio
);
123 xway_stp_w32(chip
->virt
, chip
->shadow
, XWAY_STP_CPU0
);
125 xway_stp_w32_mask(chip
->virt
, 0, XWAY_STP_CON_SWU
, XWAY_STP_CON0
);
129 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
130 * @gc: Pointer to gpio_chip device structure.
131 * @gpio: GPIO signal number.
132 * @val: Value to be written to specified signal.
134 * Same as xway_stp_set, always returns 0.
136 static int xway_stp_dir_out(struct gpio_chip
*gc
, unsigned gpio
, int val
)
138 xway_stp_set(gc
, gpio
, val
);
144 * xway_stp_request() - gpio_chip->request
145 * @gc: Pointer to gpio_chip device structure.
146 * @gpio: GPIO signal number.
148 * We mask out the HW driven pins
150 static int xway_stp_request(struct gpio_chip
*gc
, unsigned gpio
)
152 struct xway_stp
*chip
= gpiochip_get_data(gc
);
154 if ((gpio
< 8) && (chip
->reserved
& BIT(gpio
))) {
155 dev_err(gc
->parent
, "GPIO %d is driven by hardware\n", gpio
);
163 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
164 * @chip: Pointer to the xway_stp chip structure
166 static void xway_stp_hw_init(struct xway_stp
*chip
)
169 xway_stp_w32(chip
->virt
, 0, XWAY_STP_AR
);
170 xway_stp_w32(chip
->virt
, 0, XWAY_STP_CPU0
);
171 xway_stp_w32(chip
->virt
, 0, XWAY_STP_CPU1
);
172 xway_stp_w32(chip
->virt
, XWAY_STP_CON_SWU
, XWAY_STP_CON0
);
173 xway_stp_w32(chip
->virt
, 0, XWAY_STP_CON1
);
175 /* apply edge trigger settings for the shift register */
176 xway_stp_w32_mask(chip
->virt
, XWAY_STP_EDGE_MASK
,
177 chip
->edge
, XWAY_STP_CON0
);
179 /* apply led group settings */
180 xway_stp_w32_mask(chip
->virt
, XWAY_STP_GROUP_MASK
,
181 chip
->groups
, XWAY_STP_CON1
);
183 /* tell the hardware which pins are controlled by the dsl modem */
184 xway_stp_w32_mask(chip
->virt
,
185 XWAY_STP_ADSL_MASK
<< XWAY_STP_ADSL_SHIFT
,
186 chip
->dsl
<< XWAY_STP_ADSL_SHIFT
,
189 /* tell the hardware which pins are controlled by the phys */
190 xway_stp_w32_mask(chip
->virt
,
191 XWAY_STP_PHY_MASK
<< XWAY_STP_PHY1_SHIFT
,
192 chip
->phy1
<< XWAY_STP_PHY1_SHIFT
,
194 xway_stp_w32_mask(chip
->virt
,
195 XWAY_STP_PHY_MASK
<< XWAY_STP_PHY2_SHIFT
,
196 chip
->phy2
<< XWAY_STP_PHY2_SHIFT
,
199 if (of_machine_is_compatible("lantiq,grx390")
200 || of_machine_is_compatible("lantiq,ar10")) {
201 xway_stp_w32_mask(chip
->virt
,
202 XWAY_STP_PHY_MASK
<< XWAY_STP_PHY3_SHIFT
,
203 chip
->phy3
<< XWAY_STP_PHY3_SHIFT
,
207 if (of_machine_is_compatible("lantiq,grx390")) {
208 xway_stp_w32_mask(chip
->virt
,
209 XWAY_STP_PHY_MASK
<< XWAY_STP_PHY4_SHIFT
,
210 chip
->phy4
<< XWAY_STP_PHY4_SHIFT
,
214 /* mask out the hw driven bits in gpio_request */
215 chip
->reserved
= (chip
->phy4
<< 11) | (chip
->phy3
<< 8) | (chip
->phy2
<< 5)
216 | (chip
->phy1
<< 2) | chip
->dsl
;
219 * if we have pins that are driven by hw, we need to tell the stp what
220 * clock to use as a timer.
222 if (chip
->reserved
) {
223 xway_stp_w32_mask(chip
->virt
, XWAY_STP_UPD_MASK
,
224 XWAY_STP_UPD_FPI
, XWAY_STP_CON1
);
225 xway_stp_w32_mask(chip
->virt
, XWAY_STP_SPEED_MASK
,
226 XWAY_STP_10HZ
, XWAY_STP_CON1
);
227 xway_stp_w32_mask(chip
->virt
, XWAY_STP_FPIS_MASK
,
228 XWAY_STP_FPIS_VALUE
, XWAY_STP_CON1
);
232 static int xway_stp_probe(struct platform_device
*pdev
)
234 u32 shadow
, groups
, dsl
, phy
;
235 struct xway_stp
*chip
;
239 chip
= devm_kzalloc(&pdev
->dev
, sizeof(*chip
), GFP_KERNEL
);
243 chip
->virt
= devm_platform_ioremap_resource(pdev
, 0);
244 if (IS_ERR(chip
->virt
))
245 return PTR_ERR(chip
->virt
);
247 chip
->gc
.parent
= &pdev
->dev
;
248 chip
->gc
.label
= "stp-xway";
249 chip
->gc
.direction_output
= xway_stp_dir_out
;
250 chip
->gc
.get
= xway_stp_get
;
251 chip
->gc
.set
= xway_stp_set
;
252 chip
->gc
.request
= xway_stp_request
;
254 chip
->gc
.owner
= THIS_MODULE
;
256 /* store the shadow value if one was passed by the devicetree */
257 if (!of_property_read_u32(pdev
->dev
.of_node
, "lantiq,shadow", &shadow
))
258 chip
->shadow
= shadow
;
260 /* find out which gpio groups should be enabled */
261 if (!of_property_read_u32(pdev
->dev
.of_node
, "lantiq,groups", &groups
))
262 chip
->groups
= groups
& XWAY_STP_GROUP_MASK
;
264 chip
->groups
= XWAY_STP_GROUP0
;
265 chip
->gc
.ngpio
= fls(chip
->groups
) * 8;
267 /* find out which gpios are controlled by the dsl core */
268 if (!of_property_read_u32(pdev
->dev
.of_node
, "lantiq,dsl", &dsl
))
269 chip
->dsl
= dsl
& XWAY_STP_ADSL_MASK
;
271 /* find out which gpios are controlled by the phys */
272 if (of_machine_is_compatible("lantiq,ar9") ||
273 of_machine_is_compatible("lantiq,gr9") ||
274 of_machine_is_compatible("lantiq,vr9") ||
275 of_machine_is_compatible("lantiq,ar10") ||
276 of_machine_is_compatible("lantiq,grx390")) {
277 if (!of_property_read_u32(pdev
->dev
.of_node
, "lantiq,phy1", &phy
))
278 chip
->phy1
= phy
& XWAY_STP_PHY_MASK
;
279 if (!of_property_read_u32(pdev
->dev
.of_node
, "lantiq,phy2", &phy
))
280 chip
->phy2
= phy
& XWAY_STP_PHY_MASK
;
283 if (of_machine_is_compatible("lantiq,ar10") ||
284 of_machine_is_compatible("lantiq,grx390")) {
285 if (!of_property_read_u32(pdev
->dev
.of_node
, "lantiq,phy3", &phy
))
286 chip
->phy3
= phy
& XWAY_STP_PHY_MASK
;
289 if (of_machine_is_compatible("lantiq,grx390")) {
290 if (!of_property_read_u32(pdev
->dev
.of_node
, "lantiq,phy4", &phy
))
291 chip
->phy4
= phy
& XWAY_STP_PHY_MASK
;
294 /* check which edge trigger we should use, default to a falling edge */
295 if (!of_find_property(pdev
->dev
.of_node
, "lantiq,rising", NULL
))
296 chip
->edge
= XWAY_STP_FALLING
;
298 clk
= devm_clk_get(&pdev
->dev
, NULL
);
300 dev_err(&pdev
->dev
, "Failed to get clock\n");
304 ret
= clk_prepare_enable(clk
);
308 xway_stp_hw_init(chip
);
310 ret
= devm_gpiochip_add_data(&pdev
->dev
, &chip
->gc
, chip
);
312 clk_disable_unprepare(clk
);
316 dev_info(&pdev
->dev
, "Init done\n");
321 static const struct of_device_id xway_stp_match
[] = {
322 { .compatible
= "lantiq,gpio-stp-xway" },
325 MODULE_DEVICE_TABLE(of
, xway_stp_match
);
327 static struct platform_driver xway_stp_driver
= {
328 .probe
= xway_stp_probe
,
330 .name
= "gpio-stp-xway",
331 .of_match_table
= xway_stp_match
,
335 static int __init
xway_stp_init(void)
337 return platform_driver_register(&xway_stp_driver
);
340 subsys_initcall(xway_stp_init
);