drivers/gpio/gpio-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * arch/arm/mach-tegra/gpio.c
   4  *
   5  * Copyright (c) 2010 Google, Inc
   6  * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
   7  *
   8  * Author:
   9  *      Erik Gilling <konkers@google.com>
  10  */
  11
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/gpio/driver.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/module.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/irqchip/chained_irq.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pm.h>
  25
  26 #define GPIO_BANK(x)            ((x) >> 5)
  27 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  28 #define GPIO_BIT(x)             ((x) & 0x7)
  29
  30 #define GPIO_REG(tgi, x)        (GPIO_BANK(x) * tgi->soc->bank_stride + \
  31                                         GPIO_PORT(x) * 4)
  32
  33 #define GPIO_CNF(t, x)          (GPIO_REG(t, x) + 0x00)
  34 #define GPIO_OE(t, x)           (GPIO_REG(t, x) + 0x10)
  35 #define GPIO_OUT(t, x)          (GPIO_REG(t, x) + 0X20)
  36 #define GPIO_IN(t, x)           (GPIO_REG(t, x) + 0x30)
  37 #define GPIO_INT_STA(t, x)      (GPIO_REG(t, x) + 0x40)
  38 #define GPIO_INT_ENB(t, x)      (GPIO_REG(t, x) + 0x50)
  39 #define GPIO_INT_LVL(t, x)      (GPIO_REG(t, x) + 0x60)
  40 #define GPIO_INT_CLR(t, x)      (GPIO_REG(t, x) + 0x70)
  41 #define GPIO_DBC_CNT(t, x)      (GPIO_REG(t, x) + 0xF0)
  42
  43
  44 #define GPIO_MSK_CNF(t, x)      (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
  45 #define GPIO_MSK_OE(t, x)       (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
  46 #define GPIO_MSK_OUT(t, x)      (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
  47 #define GPIO_MSK_DBC_EN(t, x)   (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
  48 #define GPIO_MSK_INT_STA(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
  49 #define GPIO_MSK_INT_ENB(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
  50 #define GPIO_MSK_INT_LVL(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
  51
  52 #define GPIO_INT_LVL_MASK               0x010101
  53 #define GPIO_INT_LVL_EDGE_RISING        0x000101
  54 #define GPIO_INT_LVL_EDGE_FALLING       0x000100
  55 #define GPIO_INT_LVL_EDGE_BOTH          0x010100
  56 #define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  57 #define GPIO_INT_LVL_LEVEL_LOW          0x000000
  58
  59 struct tegra_gpio_info;
  60
  61 struct tegra_gpio_bank {
  62         unsigned int bank;
  63
  64         /*
  65          * IRQ-core code uses raw locking, and thus, nested locking also
  66          * should be raw in order not to trip spinlock debug warnings.
  67          */
  68         raw_spinlock_t lvl_lock[4];
  69
  70         /* Lock for updating debounce count register */
  71         spinlock_t dbc_lock[4];
  72
  73 #ifdef CONFIG_PM_SLEEP
  74         u32 cnf[4];
  75         u32 out[4];
  76         u32 oe[4];
  77         u32 int_enb[4];
  78         u32 int_lvl[4];
  79         u32 wake_enb[4];
  80         u32 dbc_enb[4];
  81 #endif
  82         u32 dbc_cnt[4];
  83 };
  84
  85 struct tegra_gpio_soc_config {
  86         bool debounce_supported;
  87         u32 bank_stride;
  88         u32 upper_offset;
  89 };
  90
  91 struct tegra_gpio_info {
  92         struct device                           *dev;
  93         void __iomem                            *regs;
  94         struct tegra_gpio_bank                  *bank_info;
  95         const struct tegra_gpio_soc_config      *soc;
  96         struct gpio_chip                        gc;
  97         struct irq_chip                         ic;
  98         u32                                     bank_count;
  99         unsigned int                            *irqs;
 100 };
 101
 102 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
 103                                      u32 val, u32 reg)
 104 {
 105         writel_relaxed(val, tgi->regs + reg);
 106 }
 107
 108 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
 109 {
 110         return readl_relaxed(tgi->regs + reg);
 111 }
 112
 113 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
 114                                        unsigned int bit)
 115 {
 116         return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
 117 }
 118
 119 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
 120                                   unsigned int gpio, u32 value)
 121 {
 122         u32 val;
 123
 124         val = 0x100 << GPIO_BIT(gpio);
 125         if (value)
 126                 val |= 1 << GPIO_BIT(gpio);
 127         tegra_gpio_writel(tgi, val, reg);
 128 }
 129
 130 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
 131 {
 132         tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
 133 }
 134
 135 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
 136 {
 137         tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
 138 }
 139
 140 static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
 141 {
 142         return pinctrl_gpio_request(chip->base + offset);
 143 }
 144
 145 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
 146 {
 147         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 148
 149         pinctrl_gpio_free(chip->base + offset);
 150         tegra_gpio_disable(tgi, offset);
 151 }
 152
 153 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
 154                            int value)
 155 {
 156         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 157
 158         tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
 159 }
 160
 161 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
 162 {
 163         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 164         unsigned int bval = BIT(GPIO_BIT(offset));
 165
 166         /* If gpio is in output mode then read from the out value */
 167         if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
 168                 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
 169
 170         return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
 171 }
 172
 173 static int tegra_gpio_direction_input(struct gpio_chip *chip,
 174                                       unsigned int offset)
 175 {
 176         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 177         int ret;
 178
 179         tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
 180         tegra_gpio_enable(tgi, offset);
 181
 182         ret = pinctrl_gpio_direction_input(chip->base + offset);
 183         if (ret < 0)
 184                 dev_err(tgi->dev,
 185                         "Failed to set pinctrl input direction of GPIO %d: %d",
 186                          chip->base + offset, ret);
 187
 188         return ret;
 189 }
 190
 191 static int tegra_gpio_direction_output(struct gpio_chip *chip,
 192                                        unsigned int offset,
 193                                        int value)
 194 {
 195         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 196         int ret;
 197
 198         tegra_gpio_set(chip, offset, value);
 199         tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
 200         tegra_gpio_enable(tgi, offset);
 201
 202         ret = pinctrl_gpio_direction_output(chip->base + offset);
 203         if (ret < 0)
 204                 dev_err(tgi->dev,
 205                         "Failed to set pinctrl output direction of GPIO %d: %d",
 206                          chip->base + offset, ret);
 207
 208         return ret;
 209 }
 210
 211 static int tegra_gpio_get_direction(struct gpio_chip *chip,
 212                                     unsigned int offset)
 213 {
 214         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 215         u32 pin_mask = BIT(GPIO_BIT(offset));
 216         u32 cnf, oe;
 217
 218         cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
 219         if (!(cnf & pin_mask))
 220                 return -EINVAL;
 221
 222         oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
 223
 224         if (oe & pin_mask)
 225                 return GPIO_LINE_DIRECTION_OUT;
 226
 227         return GPIO_LINE_DIRECTION_IN;
 228 }
 229
 230 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
 231                                    unsigned int debounce)
 232 {
 233         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 234         struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
 235         unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
 236         unsigned long flags;
 237         unsigned int port;
 238
 239         if (!debounce_ms) {
 240                 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
 241                                       offset, 0);
 242                 return 0;
 243         }
 244
 245         debounce_ms = min(debounce_ms, 255U);
 246         port = GPIO_PORT(offset);
 247
 248         /* There is only one debounce count register per port and hence
 249          * set the maximum of current and requested debounce time.
 250          */
 251         spin_lock_irqsave(&bank->dbc_lock[port], flags);
 252         if (bank->dbc_cnt[port] < debounce_ms) {
 253                 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
 254                 bank->dbc_cnt[port] = debounce_ms;
 255         }
 256         spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
 257
 258         tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
 259
 260         return 0;
 261 }
 262
 263 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
 264                                  unsigned long config)
 265 {
 266         u32 debounce;
 267
 268         if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
 269                 return -ENOTSUPP;
 270
 271         debounce = pinconf_to_config_argument(config);
 272         return tegra_gpio_set_debounce(chip, offset, debounce);
 273 }
 274
 275 static void tegra_gpio_irq_ack(struct irq_data *d)
 276 {
 277         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 278         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 279         unsigned int gpio = d->hwirq;
 280
 281         tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
 282 }
 283
 284 static void tegra_gpio_irq_mask(struct irq_data *d)
 285 {
 286         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 287         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 288         unsigned int gpio = d->hwirq;
 289
 290         tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
 291 }
 292
 293 static void tegra_gpio_irq_unmask(struct irq_data *d)
 294 {
 295         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 296         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 297         unsigned int gpio = d->hwirq;
 298
 299         tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
 300 }
 301
 302 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 303 {
 304         unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
 305         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 306         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 307         struct tegra_gpio_bank *bank;
 308         unsigned long flags;
 309         int ret;
 310         u32 val;
 311
 312         bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
 313
 314         switch (type & IRQ_TYPE_SENSE_MASK) {
 315         case IRQ_TYPE_EDGE_RISING:
 316                 lvl_type = GPIO_INT_LVL_EDGE_RISING;
 317                 break;
 318
 319         case IRQ_TYPE_EDGE_FALLING:
 320                 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 321                 break;
 322
 323         case IRQ_TYPE_EDGE_BOTH:
 324                 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 325                 break;
 326
 327         case IRQ_TYPE_LEVEL_HIGH:
 328                 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 329                 break;
 330
 331         case IRQ_TYPE_LEVEL_LOW:
 332                 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 333                 break;
 334
 335         default:
 336                 return -EINVAL;
 337         }
 338
 339         raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
 340
 341         val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
 342         val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 343         val |= lvl_type << GPIO_BIT(gpio);
 344         tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
 345
 346         raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 347
 348         tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
 349         tegra_gpio_enable(tgi, gpio);
 350
 351         ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
 352         if (ret) {
 353                 dev_err(tgi->dev,
 354                         "unable to lock Tegra GPIO %u as IRQ\n", gpio);
 355                 tegra_gpio_disable(tgi, gpio);
 356                 return ret;
 357         }
 358
 359         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 360                 irq_set_handler_locked(d, handle_level_irq);
 361         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 362                 irq_set_handler_locked(d, handle_edge_irq);
 363
 364         if (d->parent_data)
 365                 ret = irq_chip_set_type_parent(d, type);
 366
 367         return ret;
 368 }
 369
 370 static void tegra_gpio_irq_shutdown(struct irq_data *d)
 371 {
 372         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 373         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 374         unsigned int gpio = d->hwirq;
 375
 376         tegra_gpio_irq_mask(d);
 377         gpiochip_unlock_as_irq(&tgi->gc, gpio);
 378 }
 379
 380 static void tegra_gpio_irq_handler(struct irq_desc *desc)
 381 {
 382         struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc);
 383         struct irq_chip *chip = irq_desc_get_chip(desc);
 384         struct irq_domain *domain = tgi->gc.irq.domain;
 385         unsigned int irq = irq_desc_get_irq(desc);
 386         struct tegra_gpio_bank *bank = NULL;
 387         unsigned int port, pin, gpio, i;
 388         bool unmasked = false;
 389         unsigned long sta;
 390         u32 lvl;
 391
 392         for (i = 0; i < tgi->bank_count; i++) {
 393                 if (tgi->irqs[i] == irq) {
 394                         bank = &tgi->bank_info[i];
 395                         break;
 396                 }
 397         }
 398
 399         if (WARN_ON(bank == NULL))
 400                 return;
 401
 402         chained_irq_enter(chip, desc);
 403
 404         for (port = 0; port < 4; port++) {
 405                 gpio = tegra_gpio_compose(bank->bank, port, 0);
 406                 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
 407                         tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
 408                 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
 409
 410                 for_each_set_bit(pin, &sta, 8) {
 411                         int ret;
 412
 413                         tegra_gpio_writel(tgi, 1 << pin,
 414                                           GPIO_INT_CLR(tgi, gpio));
 415
 416                         /* if gpio is edge triggered, clear condition
 417                          * before executing the handler so that we don't
 418                          * miss edges
 419                          */
 420                         if (!unmasked && lvl & (0x100 << pin)) {
 421                                 unmasked = true;
 422                                 chained_irq_exit(chip, desc);
 423                         }
 424
 425                         ret = generic_handle_domain_irq(domain, gpio + pin);
 426                         WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
 427                 }
 428         }
 429
 430         if (!unmasked)
 431                 chained_irq_exit(chip, desc);
 432 }
 433
 434 static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
 435                                             unsigned int hwirq,
 436                                             unsigned int type,
 437                                             unsigned int *parent_hwirq,
 438                                             unsigned int *parent_type)
 439 {
 440         *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
 441         *parent_type = type;
 442
 443         return 0;
 444 }
 445
 446 static void *tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,
 447                                                unsigned int parent_hwirq,
 448                                                unsigned int parent_type)
 449 {
 450         struct irq_fwspec *fwspec;
 451
 452         fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
 453         if (!fwspec)
 454                 return NULL;
 455
 456         fwspec->fwnode = chip->irq.parent_domain->fwnode;
 457         fwspec->param_count = 3;
 458         fwspec->param[0] = 0;
 459         fwspec->param[1] = parent_hwirq;
 460         fwspec->param[2] = parent_type;
 461
 462         return fwspec;
 463 }
 464
 465 #ifdef CONFIG_PM_SLEEP
 466 static int tegra_gpio_resume(struct device *dev)
 467 {
 468         struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
 469         unsigned int b, p;
 470
 471         for (b = 0; b < tgi->bank_count; b++) {
 472                 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
 473
 474                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 475                         unsigned int gpio = (b << 5) | (p << 3);
 476
 477                         tegra_gpio_writel(tgi, bank->cnf[p],
 478                                           GPIO_CNF(tgi, gpio));
 479
 480                         if (tgi->soc->debounce_supported) {
 481                                 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
 482                                                   GPIO_DBC_CNT(tgi, gpio));
 483                                 tegra_gpio_writel(tgi, bank->dbc_enb[p],
 484                                                   GPIO_MSK_DBC_EN(tgi, gpio));
 485                         }
 486
 487                         tegra_gpio_writel(tgi, bank->out[p],
 488                                           GPIO_OUT(tgi, gpio));
 489                         tegra_gpio_writel(tgi, bank->oe[p],
 490                                           GPIO_OE(tgi, gpio));
 491                         tegra_gpio_writel(tgi, bank->int_lvl[p],
 492                                           GPIO_INT_LVL(tgi, gpio));
 493                         tegra_gpio_writel(tgi, bank->int_enb[p],
 494                                           GPIO_INT_ENB(tgi, gpio));
 495                 }
 496         }
 497
 498         return 0;
 499 }
 500
 501 static int tegra_gpio_suspend(struct device *dev)
 502 {
 503         struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
 504         unsigned int b, p;
 505
 506         for (b = 0; b < tgi->bank_count; b++) {
 507                 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
 508
 509                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 510                         unsigned int gpio = (b << 5) | (p << 3);
 511
 512                         bank->cnf[p] = tegra_gpio_readl(tgi,
 513                                                         GPIO_CNF(tgi, gpio));
 514                         bank->out[p] = tegra_gpio_readl(tgi,
 515                                                         GPIO_OUT(tgi, gpio));
 516                         bank->oe[p] = tegra_gpio_readl(tgi,
 517                                                        GPIO_OE(tgi, gpio));
 518                         if (tgi->soc->debounce_supported) {
 519                                 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
 520                                                 GPIO_MSK_DBC_EN(tgi, gpio));
 521                                 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
 522                                                         bank->dbc_enb[p];
 523                         }
 524
 525                         bank->int_enb[p] = tegra_gpio_readl(tgi,
 526                                                 GPIO_INT_ENB(tgi, gpio));
 527                         bank->int_lvl[p] = tegra_gpio_readl(tgi,
 528                                                 GPIO_INT_LVL(tgi, gpio));
 529
 530                         /* Enable gpio irq for wake up source */
 531                         tegra_gpio_writel(tgi, bank->wake_enb[p],
 532                                           GPIO_INT_ENB(tgi, gpio));
 533                 }
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 540 {
 541         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 542         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 543         struct tegra_gpio_bank *bank;
 544         unsigned int gpio = d->hwirq;
 545         u32 port, bit, mask;
 546         int err;
 547
 548         bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
 549
 550         port = GPIO_PORT(gpio);
 551         bit = GPIO_BIT(gpio);
 552         mask = BIT(bit);
 553
 554         err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);
 555         if (err)
 556                 return err;
 557
 558         if (d->parent_data) {
 559                 err = irq_chip_set_wake_parent(d, enable);
 560                 if (err) {
 561                         irq_set_irq_wake(tgi->irqs[bank->bank], !enable);
 562                         return err;
 563                 }
 564         }
 565
 566         if (enable)
 567                 bank->wake_enb[port] |= mask;
 568         else
 569                 bank->wake_enb[port] &= ~mask;
 570
 571         return 0;
 572 }
 573 #endif
 574
 575 static int tegra_gpio_irq_set_affinity(struct irq_data *data,
 576                                        const struct cpumask *dest,
 577                                        bool force)
 578 {
 579         if (data->parent_data)
 580                 return irq_chip_set_affinity_parent(data, dest, force);
 581
 582         return -EINVAL;
 583 }
 584
 585 static int tegra_gpio_irq_request_resources(struct irq_data *d)
 586 {
 587         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 588         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 589
 590         tegra_gpio_enable(tgi, d->hwirq);
 591
 592         return gpiochip_reqres_irq(chip, d->hwirq);
 593 }
 594
 595 static void tegra_gpio_irq_release_resources(struct irq_data *d)
 596 {
 597         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 598         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 599
 600         gpiochip_relres_irq(chip, d->hwirq);
 601         tegra_gpio_enable(tgi, d->hwirq);
 602 }
 603
 604 #ifdef  CONFIG_DEBUG_FS
 605
 606 #include <linux/debugfs.h>
 607 #include <linux/seq_file.h>
 608
 609 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
 610 {
 611         struct tegra_gpio_info *tgi = dev_get_drvdata(s->private);
 612         unsigned int i, j;
 613
 614         for (i = 0; i < tgi->bank_count; i++) {
 615                 for (j = 0; j < 4; j++) {
 616                         unsigned int gpio = tegra_gpio_compose(i, j, 0);
 617
 618                         seq_printf(s,
 619                                 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
 620                                 i, j,
 621                                 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
 622                                 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
 623                                 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
 624                                 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
 625                                 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
 626                                 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
 627                                 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
 628                 }
 629         }
 630         return 0;
 631 }
 632
 633 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
 634 {
 635         debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL,
 636                                     tegra_dbg_gpio_show);
 637 }
 638
 639 #else
 640
 641 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
 642 {
 643 }
 644
 645 #endif
 646
 647 static const struct dev_pm_ops tegra_gpio_pm_ops = {
 648         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
 649 };
 650
 651 static const struct of_device_id tegra_pmc_of_match[] = {
 652         { .compatible = "nvidia,tegra210-pmc", },
 653         { /* sentinel */ },
 654 };
 655
 656 static int tegra_gpio_probe(struct platform_device *pdev)
 657 {
 658         struct tegra_gpio_bank *bank;
 659         struct tegra_gpio_info *tgi;
 660         struct gpio_irq_chip *irq;
 661         struct device_node *np;
 662         unsigned int i, j;
 663         int ret;
 664
 665         tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
 666         if (!tgi)
 667                 return -ENODEV;
 668
 669         tgi->soc = of_device_get_match_data(&pdev->dev);
 670         tgi->dev = &pdev->dev;
 671
 672         ret = platform_irq_count(pdev);
 673         if (ret < 0)
 674                 return ret;
 675
 676         tgi->bank_count = ret;
 677
 678         if (!tgi->bank_count) {
 679                 dev_err(&pdev->dev, "Missing IRQ resource\n");
 680                 return -ENODEV;
 681         }
 682
 683         tgi->gc.label                   = "tegra-gpio";
 684         tgi->gc.request                 = tegra_gpio_request;
 685         tgi->gc.free                    = tegra_gpio_free;
 686         tgi->gc.direction_input         = tegra_gpio_direction_input;
 687         tgi->gc.get                     = tegra_gpio_get;
 688         tgi->gc.direction_output        = tegra_gpio_direction_output;
 689         tgi->gc.set                     = tegra_gpio_set;
 690         tgi->gc.get_direction           = tegra_gpio_get_direction;
 691         tgi->gc.base                    = 0;
 692         tgi->gc.ngpio                   = tgi->bank_count * 32;
 693         tgi->gc.parent                  = &pdev->dev;
 694         tgi->gc.of_node                 = pdev->dev.of_node;
 695
 696         tgi->ic.name                    = "GPIO";
 697         tgi->ic.irq_ack                 = tegra_gpio_irq_ack;
 698         tgi->ic.irq_mask                = tegra_gpio_irq_mask;
 699         tgi->ic.irq_unmask              = tegra_gpio_irq_unmask;
 700         tgi->ic.irq_set_type            = tegra_gpio_irq_set_type;
 701         tgi->ic.irq_shutdown            = tegra_gpio_irq_shutdown;
 702 #ifdef CONFIG_PM_SLEEP
 703         tgi->ic.irq_set_wake            = tegra_gpio_irq_set_wake;
 704 #endif
 705         tgi->ic.irq_request_resources   = tegra_gpio_irq_request_resources;
 706         tgi->ic.irq_release_resources   = tegra_gpio_irq_release_resources;
 707
 708         platform_set_drvdata(pdev, tgi);
 709
 710         if (tgi->soc->debounce_supported)
 711                 tgi->gc.set_config = tegra_gpio_set_config;
 712
 713         tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
 714                                       sizeof(*tgi->bank_info), GFP_KERNEL);
 715         if (!tgi->bank_info)
 716                 return -ENOMEM;
 717
 718         tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count,
 719                                  sizeof(*tgi->irqs), GFP_KERNEL);
 720         if (!tgi->irqs)
 721                 return -ENOMEM;
 722
 723         for (i = 0; i < tgi->bank_count; i++) {
 724                 ret = platform_get_irq(pdev, i);
 725                 if (ret < 0)
 726                         return ret;
 727
 728                 bank = &tgi->bank_info[i];
 729                 bank->bank = i;
 730
 731                 tgi->irqs[i] = ret;
 732
 733                 for (j = 0; j < 4; j++) {
 734                         raw_spin_lock_init(&bank->lvl_lock[j]);
 735                         spin_lock_init(&bank->dbc_lock[j]);
 736                 }
 737         }
 738
 739         irq = &tgi->gc.irq;
 740         irq->chip = &tgi->ic;
 741         irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
 742         irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq;
 743         irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec;
 744         irq->handler = handle_simple_irq;
 745         irq->default_type = IRQ_TYPE_NONE;
 746         irq->parent_handler = tegra_gpio_irq_handler;
 747         irq->parent_handler_data = tgi;
 748         irq->num_parents = tgi->bank_count;
 749         irq->parents = tgi->irqs;
 750
 751         np = of_find_matching_node(NULL, tegra_pmc_of_match);
 752         if (np) {
 753                 irq->parent_domain = irq_find_host(np);
 754                 of_node_put(np);
 755
 756                 if (!irq->parent_domain)
 757                         return -EPROBE_DEFER;
 758
 759                 tgi->ic.irq_set_affinity = tegra_gpio_irq_set_affinity;
 760         }
 761
 762         tgi->regs = devm_platform_ioremap_resource(pdev, 0);
 763         if (IS_ERR(tgi->regs))
 764                 return PTR_ERR(tgi->regs);
 765
 766         for (i = 0; i < tgi->bank_count; i++) {
 767                 for (j = 0; j < 4; j++) {
 768                         int gpio = tegra_gpio_compose(i, j, 0);
 769
 770                         tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
 771                 }
 772         }
 773
 774         ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
 775         if (ret < 0)
 776                 return ret;
 777
 778         tegra_gpio_debuginit(tgi);
 779
 780         return 0;
 781 }
 782
 783 static const struct tegra_gpio_soc_config tegra20_gpio_config = {
 784         .bank_stride = 0x80,
 785         .upper_offset = 0x800,
 786 };
 787
 788 static const struct tegra_gpio_soc_config tegra30_gpio_config = {
 789         .bank_stride = 0x100,
 790         .upper_offset = 0x80,
 791 };
 792
 793 static const struct tegra_gpio_soc_config tegra210_gpio_config = {
 794         .debounce_supported = true,
 795         .bank_stride = 0x100,
 796         .upper_offset = 0x80,
 797 };
 798
 799 static const struct of_device_id tegra_gpio_of_match[] = {
 800         { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
 801         { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
 802         { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
 803         { },
 804 };
 805 MODULE_DEVICE_TABLE(of, tegra_gpio_of_match);
 806
 807 static struct platform_driver tegra_gpio_driver = {
 808         .driver = {
 809                 .name = "tegra-gpio",
 810                 .pm = &tegra_gpio_pm_ops,
 811                 .of_match_table = tegra_gpio_of_match,
 812         },
 813         .probe = tegra_gpio_probe,
 814 };
 815 module_platform_driver(tegra_gpio_driver);
 816
 817 MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver");
 818 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
 819 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 820 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
 821 MODULE_AUTHOR("Erik Gilling <konkers@google.com>");
 822 MODULE_LICENSE("GPL v2");