2 * arch/arm/mach-tegra/gpio.c
4 * Copyright (c) 2010 Google, Inc
7 * Erik Gilling <konkers@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
25 #include <linux/gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/module.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/pinctrl/consumer.h>
34 #define GPIO_BANK(x) ((x) >> 5)
35 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
36 #define GPIO_BIT(x) ((x) & 0x7)
38 #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
41 #define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
42 #define GPIO_OE(x) (GPIO_REG(x) + 0x10)
43 #define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
44 #define GPIO_IN(x) (GPIO_REG(x) + 0x30)
45 #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
46 #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
47 #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
48 #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
50 #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
51 #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
52 #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
53 #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
54 #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
55 #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
57 #define GPIO_INT_LVL_MASK 0x010101
58 #define GPIO_INT_LVL_EDGE_RISING 0x000101
59 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
60 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
61 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
62 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
64 struct tegra_gpio_bank
{
67 spinlock_t lvl_lock
[4];
68 #ifdef CONFIG_PM_SLEEP
78 static struct device
*dev
;
79 static struct irq_domain
*irq_domain
;
80 static void __iomem
*regs
;
81 static u32 tegra_gpio_bank_count
;
82 static u32 tegra_gpio_bank_stride
;
83 static u32 tegra_gpio_upper_offset
;
84 static struct tegra_gpio_bank
*tegra_gpio_banks
;
86 static inline void tegra_gpio_writel(u32 val
, u32 reg
)
88 __raw_writel(val
, regs
+ reg
);
91 static inline u32
tegra_gpio_readl(u32 reg
)
93 return __raw_readl(regs
+ reg
);
96 static int tegra_gpio_compose(int bank
, int port
, int bit
)
98 return (bank
<< 5) | ((port
& 0x3) << 3) | (bit
& 0x7);
101 static void tegra_gpio_mask_write(u32 reg
, int gpio
, int value
)
105 val
= 0x100 << GPIO_BIT(gpio
);
107 val
|= 1 << GPIO_BIT(gpio
);
108 tegra_gpio_writel(val
, reg
);
111 static void tegra_gpio_enable(int gpio
)
113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio
), gpio
, 1);
116 static void tegra_gpio_disable(int gpio
)
118 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio
), gpio
, 0);
121 static int tegra_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
123 return pinctrl_request_gpio(offset
);
126 static void tegra_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
128 pinctrl_free_gpio(offset
);
129 tegra_gpio_disable(offset
);
132 static void tegra_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
134 tegra_gpio_mask_write(GPIO_MSK_OUT(offset
), offset
, value
);
137 static int tegra_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
139 /* If gpio is in output mode then read from the out value */
140 if ((tegra_gpio_readl(GPIO_OE(offset
)) >> GPIO_BIT(offset
)) & 1)
141 return (tegra_gpio_readl(GPIO_OUT(offset
)) >>
142 GPIO_BIT(offset
)) & 0x1;
144 return (tegra_gpio_readl(GPIO_IN(offset
)) >> GPIO_BIT(offset
)) & 0x1;
147 static int tegra_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
149 tegra_gpio_mask_write(GPIO_MSK_OE(offset
), offset
, 0);
150 tegra_gpio_enable(offset
);
154 static int tegra_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
157 tegra_gpio_set(chip
, offset
, value
);
158 tegra_gpio_mask_write(GPIO_MSK_OE(offset
), offset
, 1);
159 tegra_gpio_enable(offset
);
163 static int tegra_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
165 return irq_find_mapping(irq_domain
, offset
);
168 static struct gpio_chip tegra_gpio_chip
= {
169 .label
= "tegra-gpio",
170 .request
= tegra_gpio_request
,
171 .free
= tegra_gpio_free
,
172 .direction_input
= tegra_gpio_direction_input
,
173 .get
= tegra_gpio_get
,
174 .direction_output
= tegra_gpio_direction_output
,
175 .set
= tegra_gpio_set
,
176 .to_irq
= tegra_gpio_to_irq
,
180 static void tegra_gpio_irq_ack(struct irq_data
*d
)
184 tegra_gpio_writel(1 << GPIO_BIT(gpio
), GPIO_INT_CLR(gpio
));
187 static void tegra_gpio_irq_mask(struct irq_data
*d
)
191 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio
), gpio
, 0);
194 static void tegra_gpio_irq_unmask(struct irq_data
*d
)
198 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio
), gpio
, 1);
201 static int tegra_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
204 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
205 int port
= GPIO_PORT(gpio
);
211 switch (type
& IRQ_TYPE_SENSE_MASK
) {
212 case IRQ_TYPE_EDGE_RISING
:
213 lvl_type
= GPIO_INT_LVL_EDGE_RISING
;
216 case IRQ_TYPE_EDGE_FALLING
:
217 lvl_type
= GPIO_INT_LVL_EDGE_FALLING
;
220 case IRQ_TYPE_EDGE_BOTH
:
221 lvl_type
= GPIO_INT_LVL_EDGE_BOTH
;
224 case IRQ_TYPE_LEVEL_HIGH
:
225 lvl_type
= GPIO_INT_LVL_LEVEL_HIGH
;
228 case IRQ_TYPE_LEVEL_LOW
:
229 lvl_type
= GPIO_INT_LVL_LEVEL_LOW
;
236 ret
= gpiochip_lock_as_irq(&tegra_gpio_chip
, gpio
);
238 dev_err(dev
, "unable to lock Tegra GPIO %d as IRQ\n", gpio
);
242 spin_lock_irqsave(&bank
->lvl_lock
[port
], flags
);
244 val
= tegra_gpio_readl(GPIO_INT_LVL(gpio
));
245 val
&= ~(GPIO_INT_LVL_MASK
<< GPIO_BIT(gpio
));
246 val
|= lvl_type
<< GPIO_BIT(gpio
);
247 tegra_gpio_writel(val
, GPIO_INT_LVL(gpio
));
249 spin_unlock_irqrestore(&bank
->lvl_lock
[port
], flags
);
251 tegra_gpio_mask_write(GPIO_MSK_OE(gpio
), gpio
, 0);
252 tegra_gpio_enable(gpio
);
254 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
255 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
256 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
257 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
262 static void tegra_gpio_irq_shutdown(struct irq_data
*d
)
266 gpiochip_unlock_as_irq(&tegra_gpio_chip
, gpio
);
269 static void tegra_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
271 struct tegra_gpio_bank
*bank
;
275 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
277 chained_irq_enter(chip
, desc
);
279 bank
= irq_get_handler_data(irq
);
281 for (port
= 0; port
< 4; port
++) {
282 int gpio
= tegra_gpio_compose(bank
->bank
, port
, 0);
283 unsigned long sta
= tegra_gpio_readl(GPIO_INT_STA(gpio
)) &
284 tegra_gpio_readl(GPIO_INT_ENB(gpio
));
285 u32 lvl
= tegra_gpio_readl(GPIO_INT_LVL(gpio
));
287 for_each_set_bit(pin
, &sta
, 8) {
288 tegra_gpio_writel(1 << pin
, GPIO_INT_CLR(gpio
));
290 /* if gpio is edge triggered, clear condition
291 * before executing the hander so that we don't
294 if (lvl
& (0x100 << pin
)) {
296 chained_irq_exit(chip
, desc
);
299 generic_handle_irq(gpio_to_irq(gpio
+ pin
));
304 chained_irq_exit(chip
, desc
);
308 #ifdef CONFIG_PM_SLEEP
309 static int tegra_gpio_resume(struct device
*dev
)
315 local_irq_save(flags
);
317 for (b
= 0; b
< tegra_gpio_bank_count
; b
++) {
318 struct tegra_gpio_bank
*bank
= &tegra_gpio_banks
[b
];
320 for (p
= 0; p
< ARRAY_SIZE(bank
->oe
); p
++) {
321 unsigned int gpio
= (b
<<5) | (p
<<3);
322 tegra_gpio_writel(bank
->cnf
[p
], GPIO_CNF(gpio
));
323 tegra_gpio_writel(bank
->out
[p
], GPIO_OUT(gpio
));
324 tegra_gpio_writel(bank
->oe
[p
], GPIO_OE(gpio
));
325 tegra_gpio_writel(bank
->int_lvl
[p
], GPIO_INT_LVL(gpio
));
326 tegra_gpio_writel(bank
->int_enb
[p
], GPIO_INT_ENB(gpio
));
330 local_irq_restore(flags
);
334 static int tegra_gpio_suspend(struct device
*dev
)
340 local_irq_save(flags
);
341 for (b
= 0; b
< tegra_gpio_bank_count
; b
++) {
342 struct tegra_gpio_bank
*bank
= &tegra_gpio_banks
[b
];
344 for (p
= 0; p
< ARRAY_SIZE(bank
->oe
); p
++) {
345 unsigned int gpio
= (b
<<5) | (p
<<3);
346 bank
->cnf
[p
] = tegra_gpio_readl(GPIO_CNF(gpio
));
347 bank
->out
[p
] = tegra_gpio_readl(GPIO_OUT(gpio
));
348 bank
->oe
[p
] = tegra_gpio_readl(GPIO_OE(gpio
));
349 bank
->int_enb
[p
] = tegra_gpio_readl(GPIO_INT_ENB(gpio
));
350 bank
->int_lvl
[p
] = tegra_gpio_readl(GPIO_INT_LVL(gpio
));
352 /* Enable gpio irq for wake up source */
353 tegra_gpio_writel(bank
->wake_enb
[p
],
357 local_irq_restore(flags
);
361 static int tegra_gpio_irq_set_wake(struct irq_data
*d
, unsigned int enable
)
363 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
367 port
= GPIO_PORT(gpio
);
368 bit
= GPIO_BIT(gpio
);
372 bank
->wake_enb
[port
] |= mask
;
374 bank
->wake_enb
[port
] &= ~mask
;
376 return irq_set_irq_wake(bank
->irq
, enable
);
380 static struct irq_chip tegra_gpio_irq_chip
= {
382 .irq_ack
= tegra_gpio_irq_ack
,
383 .irq_mask
= tegra_gpio_irq_mask
,
384 .irq_unmask
= tegra_gpio_irq_unmask
,
385 .irq_set_type
= tegra_gpio_irq_set_type
,
386 .irq_shutdown
= tegra_gpio_irq_shutdown
,
387 #ifdef CONFIG_PM_SLEEP
388 .irq_set_wake
= tegra_gpio_irq_set_wake
,
392 static const struct dev_pm_ops tegra_gpio_pm_ops
= {
393 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend
, tegra_gpio_resume
)
396 struct tegra_gpio_soc_config
{
401 static struct tegra_gpio_soc_config tegra20_gpio_config
= {
403 .upper_offset
= 0x800,
406 static struct tegra_gpio_soc_config tegra30_gpio_config
= {
407 .bank_stride
= 0x100,
408 .upper_offset
= 0x80,
411 static const struct of_device_id tegra_gpio_of_match
[] = {
412 { .compatible
= "nvidia,tegra30-gpio", .data
= &tegra30_gpio_config
},
413 { .compatible
= "nvidia,tegra20-gpio", .data
= &tegra20_gpio_config
},
417 /* This lock class tells lockdep that GPIO irqs are in a different
418 * category than their parents, so it won't report false recursion.
420 static struct lock_class_key gpio_lock_class
;
422 static int tegra_gpio_probe(struct platform_device
*pdev
)
424 const struct of_device_id
*match
;
425 struct tegra_gpio_soc_config
*config
;
426 struct resource
*res
;
427 struct tegra_gpio_bank
*bank
;
435 match
= of_match_device(tegra_gpio_of_match
, &pdev
->dev
);
437 dev_err(&pdev
->dev
, "Error: No device match found\n");
440 config
= (struct tegra_gpio_soc_config
*)match
->data
;
442 tegra_gpio_bank_stride
= config
->bank_stride
;
443 tegra_gpio_upper_offset
= config
->upper_offset
;
446 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, tegra_gpio_bank_count
);
449 tegra_gpio_bank_count
++;
451 if (!tegra_gpio_bank_count
) {
452 dev_err(&pdev
->dev
, "Missing IRQ resource\n");
456 tegra_gpio_chip
.ngpio
= tegra_gpio_bank_count
* 32;
458 tegra_gpio_banks
= devm_kzalloc(&pdev
->dev
,
459 tegra_gpio_bank_count
* sizeof(*tegra_gpio_banks
),
461 if (!tegra_gpio_banks
)
464 irq_domain
= irq_domain_add_linear(pdev
->dev
.of_node
,
465 tegra_gpio_chip
.ngpio
,
466 &irq_domain_simple_ops
, NULL
);
470 for (i
= 0; i
< tegra_gpio_bank_count
; i
++) {
471 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, i
);
473 dev_err(&pdev
->dev
, "Missing IRQ resource\n");
477 bank
= &tegra_gpio_banks
[i
];
479 bank
->irq
= res
->start
;
482 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
483 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
485 return PTR_ERR(regs
);
487 for (i
= 0; i
< tegra_gpio_bank_count
; i
++) {
488 for (j
= 0; j
< 4; j
++) {
489 int gpio
= tegra_gpio_compose(i
, j
, 0);
490 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio
));
494 tegra_gpio_chip
.of_node
= pdev
->dev
.of_node
;
496 ret
= gpiochip_add(&tegra_gpio_chip
);
498 irq_domain_remove(irq_domain
);
502 for (gpio
= 0; gpio
< tegra_gpio_chip
.ngpio
; gpio
++) {
503 int irq
= irq_create_mapping(irq_domain
, gpio
);
504 /* No validity check; all Tegra GPIOs are valid IRQs */
506 bank
= &tegra_gpio_banks
[GPIO_BANK(gpio
)];
508 irq_set_lockdep_class(irq
, &gpio_lock_class
);
509 irq_set_chip_data(irq
, bank
);
510 irq_set_chip_and_handler(irq
, &tegra_gpio_irq_chip
,
512 set_irq_flags(irq
, IRQF_VALID
);
515 for (i
= 0; i
< tegra_gpio_bank_count
; i
++) {
516 bank
= &tegra_gpio_banks
[i
];
518 irq_set_chained_handler_and_data(bank
->irq
,
519 tegra_gpio_irq_handler
, bank
);
521 for (j
= 0; j
< 4; j
++)
522 spin_lock_init(&bank
->lvl_lock
[j
]);
528 static struct platform_driver tegra_gpio_driver
= {
530 .name
= "tegra-gpio",
531 .pm
= &tegra_gpio_pm_ops
,
532 .of_match_table
= tegra_gpio_of_match
,
534 .probe
= tegra_gpio_probe
,
537 static int __init
tegra_gpio_init(void)
539 return platform_driver_register(&tegra_gpio_driver
);
541 postcore_initcall(tegra_gpio_init
);
543 #ifdef CONFIG_DEBUG_FS
545 #include <linux/debugfs.h>
546 #include <linux/seq_file.h>
548 static int dbg_gpio_show(struct seq_file
*s
, void *unused
)
553 for (i
= 0; i
< tegra_gpio_bank_count
; i
++) {
554 for (j
= 0; j
< 4; j
++) {
555 int gpio
= tegra_gpio_compose(i
, j
, 0);
557 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
559 tegra_gpio_readl(GPIO_CNF(gpio
)),
560 tegra_gpio_readl(GPIO_OE(gpio
)),
561 tegra_gpio_readl(GPIO_OUT(gpio
)),
562 tegra_gpio_readl(GPIO_IN(gpio
)),
563 tegra_gpio_readl(GPIO_INT_STA(gpio
)),
564 tegra_gpio_readl(GPIO_INT_ENB(gpio
)),
565 tegra_gpio_readl(GPIO_INT_LVL(gpio
)));
571 static int dbg_gpio_open(struct inode
*inode
, struct file
*file
)
573 return single_open(file
, dbg_gpio_show
, &inode
->i_private
);
576 static const struct file_operations debug_fops
= {
577 .open
= dbg_gpio_open
,
580 .release
= single_release
,
583 static int __init
tegra_gpio_debuginit(void)
585 (void) debugfs_create_file("tegra_gpio", S_IRUGO
,
586 NULL
, NULL
, &debug_fops
);
589 late_initcall(tegra_gpio_debuginit
);